xeneva-source-reference/BootAA64_2gpio_8h_source.html

#ifndef __GPIO_H__

#define __GPIO_H__


#define GPFSEL0 ((volatile uint32_t*)(MMIO_BASE + 0x00200000))

#define GPFSEL1 ((volatile uint32_t*)(MMIO_BASE + 0x00200004))

#define GPFSEL2 ((volatile uint32_t*)(MMIO_BASE + 0x00200008))

#define GPFSEL3 ((volatile uint32_t*)(MMIO_BASE + 0x0020000C))

#define GPFSEL4 ((volatile uint32_t*)(MMIO_BASE + 0x00200010))

#define GPFSET0 ((volatile uint32_t*)(MMIO_BASE + 0x0020001C))

#define GPFSET1 ((volatile uint32_t*)(MMIO_BASE + 0x00200020))

#define GPFCLR0 ((volatile uint32_t*)(MMIO_BASE + 0x00200028))

#define GPLEV0 ((volatile uint32_t*)(MMIO_BASE + 0x00200034))

#define GPLEV1 ((volatile uint32_t*)(MMIO_BASE + 0x00200038))

#define GPEDS0 ((volatile uint32_t*)(MMIO_BASE + 0x00200040))

#define GPEDS1 ((volatile uint32_t*)(MMIO_BASE + 0x00200044))

#define GPHEN0 ((volatile uint32_t*)(MMIO_BASE + 0x00200064))

#define GPHEN1 ((volatile uint32_t*)(MMIO_BASE + 0x00200068))

#define GPPUD  ((volatile uint32_t*)(MMIO_BASE + 0x00200094))

#define GPPUDCLK0 ((volatile uint32_t*)(MMIO_BASE + 0x00200098))

#define GPPUDCLK1 ((volatile uint32_t*)(MMIO_BASE + 0x0020009C))


#endif