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XenevaOS
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Go to the source code of this file.
Classes | |
| struct | _hba_port_ |
| struct | _hba_mem_ |
| struct | _hba_cmd_prdt_ |
| struct | _hba_cmd_tbl_ |
| struct | _fis_data_ |
| struct | _fis_pio_setup_ |
| struct | _fis_reg_h2d_ |
| struct | _fis_reg_d2h_ |
| struct | _fis_dma_setup_ |
| struct | _hba_fis_ |
| struct | _cmd_list_hdr_ |
| struct | _AHCI_Controller_ |
Typedefs | |
| typedef struct _hba_port_ | HBA_PORT |
| typedef struct _hba_mem_ | HBA_MEM |
| typedef struct _hba_cmd_prdt_ | HBA_CMD_PRDT |
| typedef struct _hba_cmd_tbl_ | HBA_CMD_TABLE |
| typedef struct _fis_data_ | FIS_DATA |
| typedef struct _fis_pio_setup_ | FIS_PIO_SETUP |
| typedef struct _fis_reg_h2d_ | FIS_REG_H2D |
| typedef struct _fis_reg_d2h_ | FIS_REG_D2H |
| typedef struct _fis_dma_setup_ | FIS_DMA_SETUP |
| typedef struct _hba_fis_ | HBA_FIS |
| typedef struct _cmd_list_hdr_ | HBA_CMD_HEADER |
| typedef struct _AHCI_Controller_ | AHCIController |
Enumerations | |
| enum | PORT_REGISTERS { Px_CLB = 0 , Px_CLBU = 4 , Px_FB = 8 , Px_FBU = 0xC , Px_IS = 0x10 , Px_IE = 0x14 , Px_CMD = 0x18 , Px_TFD = 0x20 , Px_SIG = 0x24 , Px_SSTS = 0x28 , Px_SCTL = 0x2C , Px_SERR = 0x30 , Px_SACT = 0x34 , Px_CI = 0x38 , Px_SNTF = 0x3C , Px_FBS = 0x40 , Px_DEVSLP = 0x44 } |
| #define ATA_CMD_IDENTIFY 0xEC |
Ata commands.
| #define ATA_CMD_PACKET 0xA0 |
| #define ATA_CMD_READ_DMA 0xC8 |
| #define ATA_CMD_READ_DMA_EXT 0x25 |
| #define ATA_CMD_WRITE_DMA 0xCA |
| #define ATA_CMD_WRITE_DMA_EXT 0x35 |
| #define FIS_REG_H2D_CTRL_INTERRUPT (1<<7) |
| #define FIS_TYPE_BIST 0x58 |
| #define FIS_TYPE_DATA 0x46 |
| #define FIS_TYPE_DEV_BITS 0xA1 |
| #define FIS_TYPE_DMA_ACT 0x39 |
| #define FIS_TYPE_DMA_SETUP 0x41 |
| #define FIS_TYPE_PIO_SETUP 0x5F |
| #define FIS_TYPE_REG_D2H 0x34 |
| #define FIS_TYPE_REG_H2D 0x27 |
| #define GHC_BOHC_BB 0x10 |
| #define GHC_BOHC_BOS 1 |
| #define GHC_BOHC_OOC (1<<3) |
| #define GHC_BOHC_OOS (1<<1) |
| #define GHC_BOHC_SMIE 4 |
| #define GHC_CAP2_BOH 1 |
| #define HBA_CMD_PRDT_DBC_INTERRUPT (1<<31) |
| #define HBA_PX_CMD_ICC (0xf << 28) |
| #define HBA_PX_CMD_ICC_ACTIVE (1<<28) |
| #define HBA_PX_IS_TFES (1<<30) |
| #define HBA_PX_SSTS_DET 0xfULL |
| #define HBA_PX_SSTS_DET_INIT 1 |
| #define HBA_PX_SSTS_DET_PRESENT 3 |
| #define PX_CMD_ATAPI (1<<24) |
| #define PX_CMD_CR (1<<15) |
| #define PX_CMD_FR (1<<14) |
| #define PX_CMD_FRE (1<<4) |
| #define PX_CMD_POD 2 |
| #define PX_CMD_START 1 |
BSD 2-Clause License
Copyright (c) 2022-2024, Manas Kamal Choudhury All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
| #define PX_CMD_SUD 4 |
| #define PX_SCTL_DETECT 0x1 |
| #define PX_SCTL_IPM_ACTIVE 0x1 << 8 |
| #define PX_SCTL_IPM_MASK 0xf << 8 |
| #define PX_SCTL_IPM_NONE 0x3 << 8 |
| #define PX_SCTL_NODETECT 0x0 |
| #define PX_SCTL_NOSPEEDLIM 0x0 |
| #define PX_SCTL_PM_DISABLE (0x7 << 8) |
| #define PX_TFD_BUSY (1<<7) |
| #define PX_TFD_DRQ (1<<3) |
| #define PX_TFD_ERR 1 |
| #define SCTL_PORT_DET_INIT 0x1 |
| #define SCTL_PORT_IPM_NODSLP 0x400 |
| #define SCTL_PORT_IPM_NOPART 0x100 |
| #define SCTL_PORT_IPM_NOSLUM 0x200 |
| typedef struct _AHCI_Controller_ AHCIController |
| typedef struct _fis_data_ FIS_DATA |
| typedef struct _fis_dma_setup_ FIS_DMA_SETUP |
| typedef struct _fis_pio_setup_ FIS_PIO_SETUP |
| typedef struct _fis_reg_d2h_ FIS_REG_D2H |
| typedef struct _fis_reg_h2d_ FIS_REG_H2D |
| typedef struct _cmd_list_hdr_ HBA_CMD_HEADER |
| typedef struct _hba_cmd_prdt_ HBA_CMD_PRDT |
| typedef struct _hba_cmd_tbl_ HBA_CMD_TABLE |
| typedef struct _hba_port_ HBA_PORT |
| enum PORT_REGISTERS |