XenevaOS
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Classes | Macros | Typedefs
xhci.h File Reference
#include <stdint.h>
#include <list.h>
Include dependency graph for xhci.h:
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Go to the source code of this file.

Classes

struct  _xhci_cap_regs_
 
struct  _xhci_op_regs_
 
struct  _xhci_intr_reg_
 
struct  _xhci_runtime_regs_
 
struct  _xhci_doorbell_
 
struct  _xhci_trb_
 
struct  _xhci_ex_cap_
 
struct  _xhci_port_reg_
 
struct  _endp_
 
struct  _xhci_slot_
 
struct  _xhci_event_trb_
 
struct  _xhci_link_trb_
 
struct  _xhci_setup_trb_t_
 
struct  _xhci_data_trb_
 
struct  _xhci_status_trb_
 
struct  _xhci_ex_cap_protocol_
 
struct  _xhci_noop_trb_
 
struct  _xhci_erst_
 
struct  _xhci_input_ctx_
 

Macros

#define XHCI_USB_CMD_INTE   (1<<2)
 
#define XHCI_USB_CMD_HSEE   (1<<3)
 
#define XHCI_USB_STS_HCH   (1<<0)
 
#define XHCI_USB_STS_HSE   (1<<2)
 
#define XHCI_USB_STS_EINT   (1<<3)
 
#define XHCI_USB_STS_PCD   (1<<4)
 
#define XHCI_USB_STS_SSS   (1<<8)
 
#define XHCI_USB_STS_RSS   (1<<9)
 
#define XHCI_USB_STS_SRE   (1<<10)
 
#define XHCI_USB_STS_CNR   (1<<11)
 
#define XHCI_USB_STS_HCE   (1<<12)
 
#define XHCI_USB_CFG_MXSLOT_ENABLE   0xFF
 
#define XHCI_USB_CFG_U3_EN   (1<<8)
 
#define XHCI_USB_CFG_CINFO_EN   (1 << 9)
 
#define XHCI_USB_CCR_RCS   (1<<0)
 
#define XHCI_USB_CCR_CS   (1<<1)
 
#define XHCI_USB_CCR_CA   (1<<2)
 
#define XHCI_USB_CCR_CRR   (1<<3)
 
#define XHCI_USB_CCR_PTR_LO   0xFFFFFFC0
 
#define XCHI_USB_CCR_PTR   0xFFFFFFFFFFFFFFC0
 
#define XHCI_PORTSC_CCS   (1<<0)
 
#define XHCI_PORTSC_PED   (1<<1)
 
#define XHCI_PORTSC_OCA   (1<<3)
 
#define XHCI_PORTSC_PR   (1<<4)
 
#define XHCI_PORTSC_PP   (1<<9)
 
#define XHCI_PORTSC_CSC   (1<<17)
 
#define XHCI_PORTSC_PEC   (1<<18)
 
#define XHCI_PORTSC_PRC   (1<<21)
 
#define XHCI_PORTSC_WPR   (1<<31)
 
#define XHCI_INT_ERDP_BUSY   (1<<3)
 
#define XHCI_TRB_SIZE   16
 
#define XHCI_EVENT_RING_SEG_TBL_ENTRY_SIZE   16
 
#define XHCI_TRB_ENT   0x200000000
 
#define XHCI_TRB_ISP   0x400000000
 
#define XHCI_TRB_IOC   0x2000000000
 
#define XHCI_TRB_IDT   0x4000000000
 
#define XHCI_TRB_TRT(x)   ((uint64_t)x << 48)
 
#define XHCI_TRB_DIR_IN   ((uint64_t)1 << 48)
 
#define XHCI_DOORBELL_ENDPOINT_0   1
 
#define XHCI_DOORBELL_ENDPOINT_1   2
 
#define USB_SPEED_RESERVED   0
 
#define USB_FULL_SPEED   1
 
#define USB_LOW_SPEED   2
 
#define USB_HIGH_SPEED   3
 
#define USB_SUPER_SPEED   4
 
#define USB_SUPER_SPEED_PLUS   5
 

Typedefs

typedef void(* endpoint_callback) (void *dev, void *slot, void *Endp)
 
typedef struct _xhci_cap_regs_ xhci_cap_regs_t
 
typedef struct _xhci_op_regs_ xhci_op_regs_t
 
typedef struct _xhci_intr_reg_ xhci_interrupter_reg_t
 
typedef struct _xhci_runtime_regs_ xhci_runtime_regs_t
 
typedef struct _xhci_doorbell_ xhci_doorbell_regs_t
 
typedef struct _xhci_trb_ xhci_trb_t
 
typedef struct _xhci_ex_cap_ xhci_ext_cap_t
 
typedef struct _xhci_port_reg_ xhci_port_regs_t
 
typedef struct _endp_ XHCIEndpoint
 
typedef struct _xhci_slot_ XHCISlot
 
typedef struct _xhci_event_trb_ xhci_event_trb_t
 
typedef struct _xhci_link_trb_ xhci_link_trb_t
 
typedef struct _xhci_setup_trb_t_ xhci_setup_trb_t
 
typedef struct _xhci_data_trb_ xhci_data_trb_t
 
typedef struct _xhci_status_trb_ xhci_status_trb_t
 
typedef struct _xhci_ex_cap_protocol_ xhci_ex_cap_protocol_t
 
typedef struct _xhci_noop_trb_ xhci_noop_cmd_trb_t
 
typedef struct _xhci_erst_ xhci_erst_t
 
typedef struct _xhci_input_ctx_ XHCIInputContext
 

Macro Definition Documentation

◆ USB_FULL_SPEED

#define USB_FULL_SPEED   1

◆ USB_HIGH_SPEED

#define USB_HIGH_SPEED   3

◆ USB_LOW_SPEED

#define USB_LOW_SPEED   2

◆ USB_SPEED_RESERVED

#define USB_SPEED_RESERVED   0

◆ USB_SUPER_SPEED

#define USB_SUPER_SPEED   4

◆ USB_SUPER_SPEED_PLUS

#define USB_SUPER_SPEED_PLUS   5

◆ XCHI_USB_CCR_PTR

#define XCHI_USB_CCR_PTR   0xFFFFFFFFFFFFFFC0

◆ XHCI_DOORBELL_ENDPOINT_0

#define XHCI_DOORBELL_ENDPOINT_0   1

◆ XHCI_DOORBELL_ENDPOINT_1

#define XHCI_DOORBELL_ENDPOINT_1   2

◆ XHCI_EVENT_RING_SEG_TBL_ENTRY_SIZE

#define XHCI_EVENT_RING_SEG_TBL_ENTRY_SIZE   16

◆ XHCI_INT_ERDP_BUSY

#define XHCI_INT_ERDP_BUSY   (1<<3)

◆ XHCI_PORTSC_CCS

#define XHCI_PORTSC_CCS   (1<<0)

◆ XHCI_PORTSC_CSC

#define XHCI_PORTSC_CSC   (1<<17)

◆ XHCI_PORTSC_OCA

#define XHCI_PORTSC_OCA   (1<<3)

◆ XHCI_PORTSC_PEC

#define XHCI_PORTSC_PEC   (1<<18)

◆ XHCI_PORTSC_PED

#define XHCI_PORTSC_PED   (1<<1)

◆ XHCI_PORTSC_PP

#define XHCI_PORTSC_PP   (1<<9)

◆ XHCI_PORTSC_PR

#define XHCI_PORTSC_PR   (1<<4)

◆ XHCI_PORTSC_PRC

#define XHCI_PORTSC_PRC   (1<<21)

◆ XHCI_PORTSC_WPR

#define XHCI_PORTSC_WPR   (1<<31)

◆ XHCI_TRB_DIR_IN

#define XHCI_TRB_DIR_IN   ((uint64_t)1 << 48)

◆ XHCI_TRB_ENT

#define XHCI_TRB_ENT   0x200000000

◆ XHCI_TRB_IDT

#define XHCI_TRB_IDT   0x4000000000

◆ XHCI_TRB_IOC

#define XHCI_TRB_IOC   0x2000000000

◆ XHCI_TRB_ISP

#define XHCI_TRB_ISP   0x400000000

◆ XHCI_TRB_SIZE

#define XHCI_TRB_SIZE   16

◆ XHCI_TRB_TRT

#define XHCI_TRB_TRT (   x)    ((uint64_t)x << 48)

◆ XHCI_USB_CCR_CA

#define XHCI_USB_CCR_CA   (1<<2)

◆ XHCI_USB_CCR_CRR

#define XHCI_USB_CCR_CRR   (1<<3)

◆ XHCI_USB_CCR_CS

#define XHCI_USB_CCR_CS   (1<<1)

◆ XHCI_USB_CCR_PTR_LO

#define XHCI_USB_CCR_PTR_LO   0xFFFFFFC0

◆ XHCI_USB_CCR_RCS

#define XHCI_USB_CCR_RCS   (1<<0)

◆ XHCI_USB_CFG_CINFO_EN

#define XHCI_USB_CFG_CINFO_EN   (1 << 9)

◆ XHCI_USB_CFG_MXSLOT_ENABLE

#define XHCI_USB_CFG_MXSLOT_ENABLE   0xFF

◆ XHCI_USB_CFG_U3_EN

#define XHCI_USB_CFG_U3_EN   (1<<8)

◆ XHCI_USB_CMD_HSEE

#define XHCI_USB_CMD_HSEE   (1<<3)

◆ XHCI_USB_CMD_INTE

#define XHCI_USB_CMD_INTE   (1<<2)

BSD 2-Clause License

Copyright (c) 2022-2023, Manas Kamal Choudhury All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

◆ XHCI_USB_STS_CNR

#define XHCI_USB_STS_CNR   (1<<11)

◆ XHCI_USB_STS_EINT

#define XHCI_USB_STS_EINT   (1<<3)

◆ XHCI_USB_STS_HCE

#define XHCI_USB_STS_HCE   (1<<12)

◆ XHCI_USB_STS_HCH

#define XHCI_USB_STS_HCH   (1<<0)

◆ XHCI_USB_STS_HSE

#define XHCI_USB_STS_HSE   (1<<2)

◆ XHCI_USB_STS_PCD

#define XHCI_USB_STS_PCD   (1<<4)

◆ XHCI_USB_STS_RSS

#define XHCI_USB_STS_RSS   (1<<9)

◆ XHCI_USB_STS_SRE

#define XHCI_USB_STS_SRE   (1<<10)

◆ XHCI_USB_STS_SSS

#define XHCI_USB_STS_SSS   (1<<8)

Typedef Documentation

◆ endpoint_callback

typedef void(* endpoint_callback) (void *dev, void *slot, void *Endp)

◆ xhci_cap_regs_t

◆ xhci_data_trb_t

◆ xhci_doorbell_regs_t

◆ xhci_erst_t

typedef struct _xhci_erst_ xhci_erst_t

◆ xhci_event_trb_t

◆ xhci_ex_cap_protocol_t

◆ xhci_ext_cap_t

typedef struct _xhci_ex_cap_ xhci_ext_cap_t

◆ xhci_interrupter_reg_t

◆ xhci_link_trb_t

◆ xhci_noop_cmd_trb_t

◆ xhci_op_regs_t

◆ xhci_port_regs_t

◆ xhci_runtime_regs_t

◆ xhci_setup_trb_t

◆ xhci_status_trb_t

◆ xhci_trb_t

typedef struct _xhci_trb_ xhci_trb_t

◆ XHCIEndpoint

typedef struct _endp_ XHCIEndpoint

◆ XHCIInputContext

◆ XHCISlot

typedef struct _xhci_slot_ XHCISlot