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XenevaOS
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Go to the source code of this file.
Macros | |
| #define | ACPI_SIG_IORT "IORT" /* IO Remapping Table */ |
| #define | ACPI_SIG_IVRS "IVRS" /* I/O Virtualization Reporting Structure */ |
| #define | ACPI_SIG_LPIT "LPIT" /* Low Power Idle Table */ |
| #define | ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */ |
| #define | ACPI_SIG_MCFG "MCFG" /* PCI Memory Mapped Configuration table */ |
| #define | ACPI_SIG_MCHI "MCHI" /* Management Controller Host Interface table */ |
| #define | ACPI_SIG_MPST "MPST" /* Memory Power State Table */ |
| #define | ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics Table */ |
| #define | ACPI_SIG_MSDM "MSDM" /* Microsoft Data Management Table */ |
| #define | ACPI_SIG_MTMR "MTMR" /* MID Timer table */ |
| #define | ACPI_SIG_NFIT "NFIT" /* NVDIMM Firmware Interface Table */ |
| #define | ACPI_SIG_PCCT "PCCT" /* Platform Communications Channel Table */ |
| #define | ACPI_SIG_PDTT "PDTT" /* Platform Debug Trigger Table */ |
| #define | ACPI_SIG_PMTT "PMTT" /* Platform Memory Topology Table */ |
| #define | ACPI_SIG_PPTT "PPTT" /* Processor Properties Topology Table */ |
| #define | ACPI_SIG_RASF "RASF" /* RAS Feature table */ |
| #define | ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */ |
| #define | ACPI_SIG_SDEI "SDEI" /* Software Delegated Exception Interface Table */ |
| #define | ACPI_SIG_SDEV "SDEV" /* Secure Devices table */ |
| #define | ACPI_IORT_ID_SINGLE_MAPPING (1) |
| #define | ACPI_IORT_NODE_COHERENT 0x00000001 /* The device node is fully coherent */ |
| #define | ACPI_IORT_NODE_NOT_COHERENT 0x00000000 /* The device node is not coherent */ |
| #define | ACPI_IORT_HT_TRANSIENT (1) |
| #define | ACPI_IORT_HT_WRITE (1<<1) |
| #define | ACPI_IORT_HT_READ (1<<2) |
| #define | ACPI_IORT_HT_OVERRIDE (1<<3) |
| #define | ACPI_IORT_MF_COHERENCY (1) |
| #define | ACPI_IORT_MF_ATTRIBUTES (1<<1) |
| #define | ACPI_IORT_NC_STALL_SUPPORTED (1) |
| #define | ACPI_IORT_NC_PASID_BITS (31<<1) |
| #define | ACPI_IORT_ATS_SUPPORTED 0x00000001 /* The root complex supports ATS */ |
| #define | ACPI_IORT_ATS_UNSUPPORTED 0x00000000 /* The root complex doesn't support ATS */ |
| #define | ACPI_IORT_SMMU_V1 0x00000000 /* Generic SMMUv1 */ |
| #define | ACPI_IORT_SMMU_V2 0x00000001 /* Generic SMMUv2 */ |
| #define | ACPI_IORT_SMMU_CORELINK_MMU400 0x00000002 /* ARM Corelink MMU-400 */ |
| #define | ACPI_IORT_SMMU_CORELINK_MMU500 0x00000003 /* ARM Corelink MMU-500 */ |
| #define | ACPI_IORT_SMMU_CORELINK_MMU401 0x00000004 /* ARM Corelink MMU-401 */ |
| #define | ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x00000005 /* Cavium ThunderX SMMUv2 */ |
| #define | ACPI_IORT_SMMU_DVM_SUPPORTED (1) |
| #define | ACPI_IORT_SMMU_COHERENT_WALK (1<<1) |
| #define | ACPI_IORT_SMMU_V3_GENERIC 0x00000000 /* Generic SMMUv3 */ |
| #define | ACPI_IORT_SMMU_V3_HISILICON_HI161X 0x00000001 /* HiSilicon Hi161x SMMUv3 */ |
| #define | ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002 /* Cavium CN99xx SMMUv3 */ |
| #define | ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1) |
| #define | ACPI_IORT_SMMU_V3_HTTU_OVERRIDE (3<<1) |
| #define | ACPI_IORT_SMMU_V3_PXM_VALID (1<<3) |
| #define | ACPI_IVRS_PHYSICAL_SIZE 0x00007F00 /* 7 bits, physical address size */ |
| #define | ACPI_IVRS_VIRTUAL_SIZE 0x003F8000 /* 7 bits, virtual address size */ |
| #define | ACPI_IVRS_ATS_RESERVED 0x00400000 /* ATS address translation range reserved */ |
| #define | ACPI_IVHD_TT_ENABLE (1) |
| #define | ACPI_IVHD_PASS_PW (1<<1) |
| #define | ACPI_IVHD_RES_PASS_PW (1<<2) |
| #define | ACPI_IVHD_ISOC (1<<3) |
| #define | ACPI_IVHD_IOTLB (1<<4) |
| #define | ACPI_IVMD_UNITY (1) |
| #define | ACPI_IVMD_READ (1<<1) |
| #define | ACPI_IVMD_WRITE (1<<2) |
| #define | ACPI_IVMD_EXCLUSION_RANGE (1<<3) |
| #define | ACPI_IVHD_MSI_NUMBER_MASK 0x001F /* 5 bits, MSI message number */ |
| #define | ACPI_IVHD_UNIT_ID_MASK 0x1F00 /* 5 bits, UnitID */ |
| #define | ACPI_IVHD_ENTRY_LENGTH 0xC0 |
| #define | ACPI_IVHD_INIT_PASS (1) |
| #define | ACPI_IVHD_EINT_PASS (1<<1) |
| #define | ACPI_IVHD_NMI_PASS (1<<2) |
| #define | ACPI_IVHD_SYSTEM_MGMT (3<<4) |
| #define | ACPI_IVHD_LINT0_PASS (1<<6) |
| #define | ACPI_IVHD_LINT1_PASS (1<<7) |
| #define | ACPI_IVHD_ATS_DISABLED (1<<31) |
| #define | ACPI_IVHD_IOAPIC 1 |
| #define | ACPI_IVHD_HPET 2 |
| #define | ACPI_LPIT_STATE_DISABLED (1) |
| #define | ACPI_LPIT_NO_COUNTER (1<<1) |
| #define | ACPI_MADT_PCAT_COMPAT (1) /* 00: System also has dual 8259s */ |
| #define | ACPI_MADT_DUAL_PIC 1 |
| #define | ACPI_MADT_MULTIPLE_APIC 0 |
| #define | ACPI_MADT_CPEI_OVERRIDE (1) |
| #define | ACPI_MADT_PERFORMANCE_IRQ_MODE (1<<1) /* 01: Performance Interrupt Mode */ |
| #define | ACPI_MADT_VGIC_IRQ_MODE (1<<2) /* 02: VGIC Maintenance Interrupt mode */ |
| #define | ACPI_MADT_OVERRIDE_SPI_VALUES (1) |
| #define | ACPI_MADT_ENABLED (1) /* 00: Processor is usable if set */ |
| #define | ACPI_MADT_POLARITY_MASK (3) /* 00-01: Polarity of APIC I/O input signals */ |
| #define | ACPI_MADT_TRIGGER_MASK (3<<2) /* 02-03: Trigger mode of APIC input signals */ |
| #define | ACPI_MADT_POLARITY_CONFORMS 0 |
| #define | ACPI_MADT_POLARITY_ACTIVE_HIGH 1 |
| #define | ACPI_MADT_POLARITY_RESERVED 2 |
| #define | ACPI_MADT_POLARITY_ACTIVE_LOW 3 |
| #define | ACPI_MADT_TRIGGER_CONFORMS (0) |
| #define | ACPI_MADT_TRIGGER_EDGE (1<<2) |
| #define | ACPI_MADT_TRIGGER_RESERVED (2<<2) |
| #define | ACPI_MADT_TRIGGER_LEVEL (3<<2) |
| #define | ACPI_MPST_CHANNEL_INFO |
| #define | ACPI_MPST_ENABLED 1 |
| #define | ACPI_MPST_POWER_MANAGED 2 |
| #define | ACPI_MPST_HOT_PLUG_CAPABLE 4 |
| #define | ACPI_MPST_PRESERVE 1 |
| #define | ACPI_MPST_AUTOENTRY 2 |
| #define | ACPI_MPST_AUTOEXIT 4 |
| #define | ACPI_NFIT_ADD_ONLINE_ONLY (1) /* 00: Add/Online Operation Only */ |
| #define | ACPI_NFIT_PROXIMITY_VALID (1<<1) /* 01: Proximity Domain Valid */ |
| #define | ACPI_NFIT_MEM_SAVE_FAILED (1) /* 00: Last SAVE to Memory Device failed */ |
| #define | ACPI_NFIT_MEM_RESTORE_FAILED (1<<1) /* 01: Last RESTORE from Memory Device failed */ |
| #define | ACPI_NFIT_MEM_FLUSH_FAILED (1<<2) /* 02: Platform flush failed */ |
| #define | ACPI_NFIT_MEM_NOT_ARMED (1<<3) /* 03: Memory Device is not armed */ |
| #define | ACPI_NFIT_MEM_HEALTH_OBSERVED (1<<4) /* 04: Memory Device observed SMART/health events */ |
| #define | ACPI_NFIT_MEM_HEALTH_ENABLED (1<<5) /* 05: SMART/health events enabled */ |
| #define | ACPI_NFIT_MEM_MAP_FAILED (1<<6) /* 06: Mapping to SPA failed */ |
| #define | ACPI_NFIT_CONTROL_BUFFERED (1) /* Block Data Windows implementation is buffered */ |
| #define | ACPI_NFIT_CONTROL_MFG_INFO_VALID (1) /* Manufacturing fields are valid */ |
| #define | ACPI_NFIT_CAPABILITY_CACHE_FLUSH (1) /* 00: Cache Flush to NVDIMM capable */ |
| #define | ACPI_NFIT_CAPABILITY_MEM_FLUSH (1<<1) /* 01: Memory Flush to NVDIMM capable */ |
| #define | ACPI_NFIT_CAPABILITY_MEM_MIRRORING (1<<2) /* 02: Memory Mirroring capable */ |
| #define | ACPI_NFIT_DIMM_NUMBER_MASK 0x0000000F |
| #define | ACPI_NFIT_CHANNEL_NUMBER_MASK 0x000000F0 |
| #define | ACPI_NFIT_MEMORY_ID_MASK 0x00000F00 |
| #define | ACPI_NFIT_SOCKET_ID_MASK 0x0000F000 |
| #define | ACPI_NFIT_NODE_ID_MASK 0x0FFF0000 |
| #define | ACPI_NFIT_DIMM_NUMBER_OFFSET 0 |
| #define | ACPI_NFIT_CHANNEL_NUMBER_OFFSET 4 |
| #define | ACPI_NFIT_MEMORY_ID_OFFSET 8 |
| #define | ACPI_NFIT_SOCKET_ID_OFFSET 12 |
| #define | ACPI_NFIT_NODE_ID_OFFSET 16 |
| #define | ACPI_NFIT_BUILD_DEVICE_HANDLE(dimm, channel, memory, socket, node) |
| #define | ACPI_NFIT_GET_DIMM_NUMBER(handle) ((handle) & ACPI_NFIT_DIMM_NUMBER_MASK) |
| #define | ACPI_NFIT_GET_CHANNEL_NUMBER(handle) (((handle) & ACPI_NFIT_CHANNEL_NUMBER_MASK) >> ACPI_NFIT_CHANNEL_NUMBER_OFFSET) |
| #define | ACPI_NFIT_GET_MEMORY_ID(handle) (((handle) & ACPI_NFIT_MEMORY_ID_MASK) >> ACPI_NFIT_MEMORY_ID_OFFSET) |
| #define | ACPI_NFIT_GET_SOCKET_ID(handle) (((handle) & ACPI_NFIT_SOCKET_ID_MASK) >> ACPI_NFIT_SOCKET_ID_OFFSET) |
| #define | ACPI_NFIT_GET_NODE_ID(handle) (((handle) & ACPI_NFIT_NODE_ID_MASK) >> ACPI_NFIT_NODE_ID_OFFSET) |
| #define | ACPI_PCCT_DOORBELL 1 |
| #define | ACPI_PCCT_INTERRUPT_POLARITY (1) |
| #define | ACPI_PCCT_INTERRUPT_MODE (1<<1) |
| #define | ACPI_PDTT_RUNTIME_TRIGGER (1) |
| #define | ACPI_PDTT_WAIT_COMPLETION (1<<1) |
| #define | ACPI_PDTT_TRIGGER_ORDER (1<<2) |
| #define | ACPI_PMTT_TYPE_SOCKET 0 |
| #define | ACPI_PMTT_TYPE_CONTROLLER 1 |
| #define | ACPI_PMTT_TYPE_DIMM 2 |
| #define | ACPI_PMTT_TYPE_RESERVED 3 /* 0x03-0xFF are reserved */ |
| #define | ACPI_PMTT_TOP_LEVEL 0x0001 |
| #define | ACPI_PMTT_PHYSICAL 0x0002 |
| #define | ACPI_PMTT_MEMORY_TYPE 0x000C |
| #define | ACPI_PPTT_PHYSICAL_PACKAGE (1) |
| #define | ACPI_PPTT_ACPI_PROCESSOR_ID_VALID (1<<1) |
| #define | ACPI_PPTT_ACPI_PROCESSOR_IS_THREAD (1<<2) /* ACPI 6.3 */ |
| #define | ACPI_PPTT_ACPI_LEAF_NODE (1<<3) /* ACPI 6.3 */ |
| #define | ACPI_PPTT_ACPI_IDENTICAL (1<<4) /* ACPI 6.3 */ |
| #define | ACPI_PPTT_SIZE_PROPERTY_VALID (1) /* Physical property valid */ |
| #define | ACPI_PPTT_NUMBER_OF_SETS_VALID (1<<1) /* Number of sets valid */ |
| #define | ACPI_PPTT_ASSOCIATIVITY_VALID (1<<2) /* Associativity valid */ |
| #define | ACPI_PPTT_ALLOCATION_TYPE_VALID (1<<3) /* Allocation type valid */ |
| #define | ACPI_PPTT_CACHE_TYPE_VALID (1<<4) /* Cache type valid */ |
| #define | ACPI_PPTT_WRITE_POLICY_VALID (1<<5) /* Write policy valid */ |
| #define | ACPI_PPTT_LINE_SIZE_VALID (1<<6) /* Line size valid */ |
| #define | ACPI_PPTT_MASK_ALLOCATION_TYPE (0x03) /* Allocation type */ |
| #define | ACPI_PPTT_MASK_CACHE_TYPE (0x0C) /* Cache type */ |
| #define | ACPI_PPTT_MASK_WRITE_POLICY (0x10) /* Write policy */ |
| #define | ACPI_PPTT_CACHE_READ_ALLOCATE (0x0) /* Cache line is allocated on read */ |
| #define | ACPI_PPTT_CACHE_WRITE_ALLOCATE (0x01) /* Cache line is allocated on write */ |
| #define | ACPI_PPTT_CACHE_RW_ALLOCATE (0x02) /* Cache line is allocated on read and write */ |
| #define | ACPI_PPTT_CACHE_RW_ALLOCATE_ALT (0x03) /* Alternate representation of above */ |
| #define | ACPI_PPTT_CACHE_TYPE_DATA (0x0) /* Data cache */ |
| #define | ACPI_PPTT_CACHE_TYPE_INSTR (1<<2) /* Instruction cache */ |
| #define | ACPI_PPTT_CACHE_TYPE_UNIFIED (2<<2) /* Unified I & D cache */ |
| #define | ACPI_PPTT_CACHE_TYPE_UNIFIED_ALT (3<<2) /* Alternate representation of above */ |
| #define | ACPI_PPTT_CACHE_POLICY_WB (0x0) /* Cache is write back */ |
| #define | ACPI_PPTT_CACHE_POLICY_WT (1<<4) /* Cache is write through */ |
| #define | ACPI_RASF_SCRUBBER_RUNNING 1 |
| #define | ACPI_RASF_SPEED (7<<1) |
| #define | ACPI_RASF_SPEED_SLOW (0<<1) |
| #define | ACPI_RASF_SPEED_MEDIUM (4<<1) |
| #define | ACPI_RASF_SPEED_FAST (7<<1) |
| #define | ACPI_RASF_GENERATE_SCI (1<<15) |
| #define | ACPI_RASF_COMMAND_COMPLETE (1) |
| #define | ACPI_RASF_SCI_DOORBELL (1<<1) |
| #define | ACPI_RASF_ERROR (1<<2) |
| #define | ACPI_RASF_STATUS (0x1F<<3) |
| #define | ACPI_SDEV_HANDOFF_TO_UNSECURE_OS (1) |
| #define ACPI_IORT_ATS_SUPPORTED 0x00000001 /* The root complex supports ATS */ |
| #define ACPI_IORT_HT_OVERRIDE (1<<3) |
| #define ACPI_IORT_HT_READ (1<<2) |
| #define ACPI_IORT_HT_TRANSIENT (1) |
| #define ACPI_IORT_HT_WRITE (1<<1) |
| #define ACPI_IORT_ID_SINGLE_MAPPING (1) |
| #define ACPI_IORT_MF_ATTRIBUTES (1<<1) |
| #define ACPI_IORT_MF_COHERENCY (1) |
| #define ACPI_IORT_NC_PASID_BITS (31<<1) |
| #define ACPI_IORT_NC_STALL_SUPPORTED (1) |
| #define ACPI_IORT_NODE_COHERENT 0x00000001 /* The device node is fully coherent */ |
| #define ACPI_IORT_NODE_NOT_COHERENT 0x00000000 /* The device node is not coherent */ |
| #define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x00000005 /* Cavium ThunderX SMMUv2 */ |
| #define ACPI_IORT_SMMU_COHERENT_WALK (1<<1) |
| #define ACPI_IORT_SMMU_CORELINK_MMU400 0x00000002 /* ARM Corelink MMU-400 */ |
| #define ACPI_IORT_SMMU_CORELINK_MMU401 0x00000004 /* ARM Corelink MMU-401 */ |
| #define ACPI_IORT_SMMU_CORELINK_MMU500 0x00000003 /* ARM Corelink MMU-500 */ |
| #define ACPI_IORT_SMMU_DVM_SUPPORTED (1) |
| #define ACPI_IORT_SMMU_V1 0x00000000 /* Generic SMMUv1 */ |
| #define ACPI_IORT_SMMU_V2 0x00000001 /* Generic SMMUv2 */ |
| #define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002 /* Cavium CN99xx SMMUv3 */ |
| #define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1) |
| #define ACPI_IORT_SMMU_V3_GENERIC 0x00000000 /* Generic SMMUv3 */ |
| #define ACPI_IORT_SMMU_V3_HISILICON_HI161X 0x00000001 /* HiSilicon Hi161x SMMUv3 */ |
| #define ACPI_IORT_SMMU_V3_HTTU_OVERRIDE (3<<1) |
| #define ACPI_IORT_SMMU_V3_PXM_VALID (1<<3) |
| #define ACPI_IVHD_ATS_DISABLED (1<<31) |
| #define ACPI_IVHD_EINT_PASS (1<<1) |
| #define ACPI_IVHD_ENTRY_LENGTH 0xC0 |
| #define ACPI_IVHD_HPET 2 |
| #define ACPI_IVHD_INIT_PASS (1) |
| #define ACPI_IVHD_IOAPIC 1 |
| #define ACPI_IVHD_IOTLB (1<<4) |
| #define ACPI_IVHD_ISOC (1<<3) |
| #define ACPI_IVHD_LINT0_PASS (1<<6) |
| #define ACPI_IVHD_LINT1_PASS (1<<7) |
| #define ACPI_IVHD_MSI_NUMBER_MASK 0x001F /* 5 bits, MSI message number */ |
| #define ACPI_IVHD_NMI_PASS (1<<2) |
| #define ACPI_IVHD_PASS_PW (1<<1) |
| #define ACPI_IVHD_RES_PASS_PW (1<<2) |
| #define ACPI_IVHD_SYSTEM_MGMT (3<<4) |
| #define ACPI_IVHD_TT_ENABLE (1) |
| #define ACPI_IVHD_UNIT_ID_MASK 0x1F00 /* 5 bits, UnitID */ |
| #define ACPI_IVMD_EXCLUSION_RANGE (1<<3) |
| #define ACPI_IVMD_READ (1<<1) |
| #define ACPI_IVMD_UNITY (1) |
| #define ACPI_IVMD_WRITE (1<<2) |
| #define ACPI_IVRS_ATS_RESERVED 0x00400000 /* ATS address translation range reserved */ |
| #define ACPI_IVRS_PHYSICAL_SIZE 0x00007F00 /* 7 bits, physical address size */ |
| #define ACPI_IVRS_VIRTUAL_SIZE 0x003F8000 /* 7 bits, virtual address size */ |
| #define ACPI_LPIT_NO_COUNTER (1<<1) |
| #define ACPI_LPIT_STATE_DISABLED (1) |
| #define ACPI_MADT_CPEI_OVERRIDE (1) |
| #define ACPI_MADT_DUAL_PIC 1 |
| #define ACPI_MADT_ENABLED (1) /* 00: Processor is usable if set */ |
| #define ACPI_MADT_MULTIPLE_APIC 0 |
| #define ACPI_MADT_OVERRIDE_SPI_VALUES (1) |
| #define ACPI_MADT_PCAT_COMPAT (1) /* 00: System also has dual 8259s */ |
| #define ACPI_MADT_PERFORMANCE_IRQ_MODE (1<<1) /* 01: Performance Interrupt Mode */ |
| #define ACPI_MADT_POLARITY_ACTIVE_HIGH 1 |
| #define ACPI_MADT_POLARITY_ACTIVE_LOW 3 |
| #define ACPI_MADT_POLARITY_CONFORMS 0 |
| #define ACPI_MADT_POLARITY_RESERVED 2 |
| #define ACPI_MADT_TRIGGER_CONFORMS (0) |
| #define ACPI_MADT_TRIGGER_EDGE (1<<2) |
| #define ACPI_MADT_TRIGGER_LEVEL (3<<2) |
| #define ACPI_MADT_TRIGGER_MASK (3<<2) /* 02-03: Trigger mode of APIC input signals */ |
| #define ACPI_MADT_TRIGGER_RESERVED (2<<2) |
| #define ACPI_MADT_VGIC_IRQ_MODE (1<<2) /* 02: VGIC Maintenance Interrupt mode */ |
| #define ACPI_MPST_AUTOENTRY 2 |
| #define ACPI_MPST_AUTOEXIT 4 |
| #define ACPI_MPST_CHANNEL_INFO |
| #define ACPI_MPST_ENABLED 1 |
| #define ACPI_MPST_HOT_PLUG_CAPABLE 4 |
| #define ACPI_MPST_POWER_MANAGED 2 |
| #define ACPI_MPST_PRESERVE 1 |
| #define ACPI_NFIT_ADD_ONLINE_ONLY (1) /* 00: Add/Online Operation Only */ |
| #define ACPI_NFIT_BUILD_DEVICE_HANDLE | ( | dimm, | |
| channel, | |||
| memory, | |||
| socket, | |||
| node | |||
| ) |
| #define ACPI_NFIT_CAPABILITY_CACHE_FLUSH (1) /* 00: Cache Flush to NVDIMM capable */ |
| #define ACPI_NFIT_CAPABILITY_MEM_FLUSH (1<<1) /* 01: Memory Flush to NVDIMM capable */ |
| #define ACPI_NFIT_CAPABILITY_MEM_MIRRORING (1<<2) /* 02: Memory Mirroring capable */ |
| #define ACPI_NFIT_CHANNEL_NUMBER_MASK 0x000000F0 |
| #define ACPI_NFIT_CHANNEL_NUMBER_OFFSET 4 |
| #define ACPI_NFIT_CONTROL_BUFFERED (1) /* Block Data Windows implementation is buffered */ |
| #define ACPI_NFIT_CONTROL_MFG_INFO_VALID (1) /* Manufacturing fields are valid */ |
| #define ACPI_NFIT_DIMM_NUMBER_MASK 0x0000000F |
| #define ACPI_NFIT_DIMM_NUMBER_OFFSET 0 |
| #define ACPI_NFIT_GET_CHANNEL_NUMBER | ( | handle | ) | (((handle) & ACPI_NFIT_CHANNEL_NUMBER_MASK) >> ACPI_NFIT_CHANNEL_NUMBER_OFFSET) |
| #define ACPI_NFIT_GET_DIMM_NUMBER | ( | handle | ) | ((handle) & ACPI_NFIT_DIMM_NUMBER_MASK) |
| #define ACPI_NFIT_GET_MEMORY_ID | ( | handle | ) | (((handle) & ACPI_NFIT_MEMORY_ID_MASK) >> ACPI_NFIT_MEMORY_ID_OFFSET) |
| #define ACPI_NFIT_GET_NODE_ID | ( | handle | ) | (((handle) & ACPI_NFIT_NODE_ID_MASK) >> ACPI_NFIT_NODE_ID_OFFSET) |
| #define ACPI_NFIT_GET_SOCKET_ID | ( | handle | ) | (((handle) & ACPI_NFIT_SOCKET_ID_MASK) >> ACPI_NFIT_SOCKET_ID_OFFSET) |
| #define ACPI_NFIT_MEM_FLUSH_FAILED (1<<2) /* 02: Platform flush failed */ |
| #define ACPI_NFIT_MEM_HEALTH_ENABLED (1<<5) /* 05: SMART/health events enabled */ |
| #define ACPI_NFIT_MEM_HEALTH_OBSERVED (1<<4) /* 04: Memory Device observed SMART/health events */ |
| #define ACPI_NFIT_MEM_MAP_FAILED (1<<6) /* 06: Mapping to SPA failed */ |
| #define ACPI_NFIT_MEM_NOT_ARMED (1<<3) /* 03: Memory Device is not armed */ |
| #define ACPI_NFIT_MEM_RESTORE_FAILED (1<<1) /* 01: Last RESTORE from Memory Device failed */ |
| #define ACPI_NFIT_MEM_SAVE_FAILED (1) /* 00: Last SAVE to Memory Device failed */ |
| #define ACPI_NFIT_MEMORY_ID_MASK 0x00000F00 |
| #define ACPI_NFIT_MEMORY_ID_OFFSET 8 |
| #define ACPI_NFIT_NODE_ID_MASK 0x0FFF0000 |
| #define ACPI_NFIT_NODE_ID_OFFSET 16 |
| #define ACPI_NFIT_PROXIMITY_VALID (1<<1) /* 01: Proximity Domain Valid */ |
| #define ACPI_NFIT_SOCKET_ID_MASK 0x0000F000 |
| #define ACPI_NFIT_SOCKET_ID_OFFSET 12 |
| #define ACPI_PCCT_DOORBELL 1 |
| #define ACPI_PCCT_INTERRUPT_MODE (1<<1) |
| #define ACPI_PCCT_INTERRUPT_POLARITY (1) |
| #define ACPI_PDTT_RUNTIME_TRIGGER (1) |
| #define ACPI_PDTT_TRIGGER_ORDER (1<<2) |
| #define ACPI_PDTT_WAIT_COMPLETION (1<<1) |
| #define ACPI_PMTT_MEMORY_TYPE 0x000C |
| #define ACPI_PMTT_PHYSICAL 0x0002 |
| #define ACPI_PMTT_TOP_LEVEL 0x0001 |
| #define ACPI_PMTT_TYPE_CONTROLLER 1 |
| #define ACPI_PMTT_TYPE_DIMM 2 |
| #define ACPI_PMTT_TYPE_RESERVED 3 /* 0x03-0xFF are reserved */ |
| #define ACPI_PMTT_TYPE_SOCKET 0 |
| #define ACPI_PPTT_ACPI_IDENTICAL (1<<4) /* ACPI 6.3 */ |
| #define ACPI_PPTT_ACPI_LEAF_NODE (1<<3) /* ACPI 6.3 */ |
| #define ACPI_PPTT_ACPI_PROCESSOR_ID_VALID (1<<1) |
| #define ACPI_PPTT_ACPI_PROCESSOR_IS_THREAD (1<<2) /* ACPI 6.3 */ |
| #define ACPI_PPTT_ALLOCATION_TYPE_VALID (1<<3) /* Allocation type valid */ |
| #define ACPI_PPTT_ASSOCIATIVITY_VALID (1<<2) /* Associativity valid */ |
| #define ACPI_PPTT_CACHE_POLICY_WB (0x0) /* Cache is write back */ |
| #define ACPI_PPTT_CACHE_POLICY_WT (1<<4) /* Cache is write through */ |
| #define ACPI_PPTT_CACHE_READ_ALLOCATE (0x0) /* Cache line is allocated on read */ |
| #define ACPI_PPTT_CACHE_RW_ALLOCATE_ALT (0x03) /* Alternate representation of above */ |
| #define ACPI_PPTT_CACHE_TYPE_DATA (0x0) /* Data cache */ |
| #define ACPI_PPTT_CACHE_TYPE_INSTR (1<<2) /* Instruction cache */ |
| #define ACPI_PPTT_CACHE_TYPE_UNIFIED (2<<2) /* Unified I & D cache */ |
| #define ACPI_PPTT_CACHE_TYPE_UNIFIED_ALT (3<<2) /* Alternate representation of above */ |
| #define ACPI_PPTT_CACHE_TYPE_VALID (1<<4) /* Cache type valid */ |
| #define ACPI_PPTT_CACHE_WRITE_ALLOCATE (0x01) /* Cache line is allocated on write */ |
| #define ACPI_PPTT_LINE_SIZE_VALID (1<<6) /* Line size valid */ |
| #define ACPI_PPTT_MASK_ALLOCATION_TYPE (0x03) /* Allocation type */ |
| #define ACPI_PPTT_MASK_CACHE_TYPE (0x0C) /* Cache type */ |
| #define ACPI_PPTT_MASK_WRITE_POLICY (0x10) /* Write policy */ |
| #define ACPI_PPTT_NUMBER_OF_SETS_VALID (1<<1) /* Number of sets valid */ |
| #define ACPI_PPTT_PHYSICAL_PACKAGE (1) |
| #define ACPI_PPTT_SIZE_PROPERTY_VALID (1) /* Physical property valid */ |
| #define ACPI_PPTT_WRITE_POLICY_VALID (1<<5) /* Write policy valid */ |
| #define ACPI_RASF_COMMAND_COMPLETE (1) |
| #define ACPI_RASF_ERROR (1<<2) |
| #define ACPI_RASF_GENERATE_SCI (1<<15) |
| #define ACPI_RASF_SCI_DOORBELL (1<<1) |
| #define ACPI_RASF_SCRUBBER_RUNNING 1 |
| #define ACPI_RASF_SPEED (7<<1) |
| #define ACPI_RASF_SPEED_FAST (7<<1) |
| #define ACPI_RASF_SPEED_MEDIUM (4<<1) |
| #define ACPI_RASF_SPEED_SLOW (0<<1) |
| #define ACPI_RASF_STATUS (0x1F<<3) |
| #define ACPI_SDEV_HANDOFF_TO_UNSECURE_OS (1) |
| #define ACPI_SIG_IORT "IORT" /* IO Remapping Table */ |
| #define ACPI_SIG_IVRS "IVRS" /* I/O Virtualization Reporting Structure */ |
| #define ACPI_SIG_LPIT "LPIT" /* Low Power Idle Table */ |
| #define ACPI_SIG_MADT "APIC" /* Multiple APIC Description Table */ |
| #define ACPI_SIG_MCFG "MCFG" /* PCI Memory Mapped Configuration table */ |
| #define ACPI_SIG_MCHI "MCHI" /* Management Controller Host Interface table */ |
| #define ACPI_SIG_MPST "MPST" /* Memory Power State Table */ |
| #define ACPI_SIG_MSCT "MSCT" /* Maximum System Characteristics Table */ |
| #define ACPI_SIG_MSDM "MSDM" /* Microsoft Data Management Table */ |
| #define ACPI_SIG_MTMR "MTMR" /* MID Timer table */ |
| #define ACPI_SIG_NFIT "NFIT" /* NVDIMM Firmware Interface Table */ |
| #define ACPI_SIG_PCCT "PCCT" /* Platform Communications Channel Table */ |
| #define ACPI_SIG_PDTT "PDTT" /* Platform Debug Trigger Table */ |
| #define ACPI_SIG_PMTT "PMTT" /* Platform Memory Topology Table */ |
| #define ACPI_SIG_PPTT "PPTT" /* Processor Properties Topology Table */ |
| #define ACPI_SIG_RASF "RASF" /* RAS Feature table */ |
| #define ACPI_SIG_SBST "SBST" /* Smart Battery Specification Table */ |
| #define ACPI_SIG_SDEI "SDEI" /* Software Delegated Exception Interface Table */ |
| #define ACPI_SIG_SDEV "SDEV" /* Secure Devices table */ |
| typedef struct acpi_iort_id_mapping ACPI_IORT_ID_MAPPING |
| typedef struct acpi_iort_its_group ACPI_IORT_ITS_GROUP |
| typedef struct acpi_iort_memory_access ACPI_IORT_MEMORY_ACCESS |
| typedef struct acpi_iort_named_component ACPI_IORT_NAMED_COMPONENT |
| typedef struct acpi_iort_node ACPI_IORT_NODE |
| typedef struct acpi_iort_pmcg ACPI_IORT_PMCG |
| typedef struct acpi_iort_root_complex ACPI_IORT_ROOT_COMPLEX |
| typedef struct acpi_iort_smmu ACPI_IORT_SMMU |
| typedef struct acpi_iort_smmu_gsi ACPI_IORT_SMMU_GSI |
| typedef struct acpi_iort_smmu_v3 ACPI_IORT_SMMU_V3 |
| typedef struct acpi_ivrs_de_header ACPI_IVRS_DE_HEADER |
| typedef struct acpi_ivrs_device4 ACPI_IVRS_DEVICE4 |
| typedef struct acpi_ivrs_device8a ACPI_IVRS_DEVICE8A |
| typedef struct acpi_ivrs_device8b ACPI_IVRS_DEVICE8B |
| typedef struct acpi_ivrs_device8c ACPI_IVRS_DEVICE8C |
| typedef struct acpi_ivrs_hardware ACPI_IVRS_HARDWARE |
| typedef struct acpi_ivrs_header ACPI_IVRS_HEADER |
| typedef struct acpi_ivrs_memory ACPI_IVRS_MEMORY |
| typedef struct acpi_lpit_header ACPI_LPIT_HEADER |
| typedef struct acpi_lpit_native ACPI_LPIT_NATIVE |
| typedef struct acpi_madt_generic_distributor ACPI_MADT_GENERIC_DISTRIBUTOR |
| typedef struct acpi_madt_generic_interrupt ACPI_MADT_GENERIC_INTERRUPT |
| typedef struct acpi_madt_generic_msi_frame ACPI_MADT_GENERIC_MSI_FRAME |
| typedef struct acpi_madt_generic_redistributor ACPI_MADT_GENERIC_REDISTRIBUTOR |
| typedef struct acpi_madt_generic_translator ACPI_MADT_GENERIC_TRANSLATOR |
| typedef struct acpi_madt_interrupt_override ACPI_MADT_INTERRUPT_OVERRIDE |
| typedef struct acpi_madt_interrupt_source ACPI_MADT_INTERRUPT_SOURCE |
| typedef struct acpi_madt_io_apic ACPI_MADT_IO_APIC |
| typedef struct acpi_madt_io_sapic ACPI_MADT_IO_SAPIC |
| typedef struct acpi_madt_local_apic ACPI_MADT_LOCAL_APIC |
| typedef struct acpi_madt_local_apic_nmi ACPI_MADT_LOCAL_APIC_NMI |
| typedef struct acpi_madt_local_apic_override ACPI_MADT_LOCAL_APIC_OVERRIDE |
| typedef struct acpi_madt_local_sapic ACPI_MADT_LOCAL_SAPIC |
| typedef struct acpi_madt_local_x2apic ACPI_MADT_LOCAL_X2APIC |
| typedef struct acpi_madt_local_x2apic_nmi ACPI_MADT_LOCAL_X2APIC_NMI |
| typedef struct acpi_madt_nmi_source ACPI_MADT_NMI_SOURCE |
| typedef struct acpi_mcfg_allocation ACPI_MCFG_ALLOCATION |
| typedef struct acpi_mpst_channel ACPI_MPST_CHANNEL |
| typedef struct acpi_mpst_component ACPI_MPST_COMPONENT |
| typedef struct acpi_mpst_data_hdr ACPI_MPST_DATA_HDR |
| typedef struct acpi_mpst_power_data ACPI_MPST_POWER_DATA |
| typedef struct acpi_mpst_power_node ACPI_MPST_POWER_NODE |
| typedef struct acpi_mpst_power_state ACPI_MPST_POWER_STATE |
| typedef struct acpi_mpst_shared ACPI_MPST_SHARED |
| typedef struct acpi_msct_proximity ACPI_MSCT_PROXIMITY |
| typedef struct acpi_mtmr_entry ACPI_MTMR_ENTRY |
| typedef struct acpi_nfit_capabilities ACPI_NFIT_CAPABILITIES |
| typedef struct acpi_nfit_control_region ACPI_NFIT_CONTROL_REGION |
| typedef struct acpi_nfit_data_region ACPI_NFIT_DATA_REGION |
| typedef struct acpi_nfit_flush_address ACPI_NFIT_FLUSH_ADDRESS |
| typedef struct acpi_nfit_header ACPI_NFIT_HEADER |
| typedef struct acpi_nfit_interleave ACPI_NFIT_INTERLEAVE |
| typedef struct acpi_nfit_memory_map ACPI_NFIT_MEMORY_MAP |
| typedef struct acpi_nfit_smbios ACPI_NFIT_SMBIOS |
| typedef struct acpi_nfit_system_address ACPI_NFIT_SYSTEM_ADDRESS |
| typedef struct acpi_pcct_ext_pcc_master ACPI_PCCT_EXT_PCC_MASTER |
| typedef struct acpi_pcct_ext_pcc_shared_memory ACPI_PCCT_EXT_PCC_SHARED_MEMORY |
| typedef struct acpi_pcct_ext_pcc_slave ACPI_PCCT_EXT_PCC_SLAVE |
| typedef struct acpi_pcct_hw_reduced ACPI_PCCT_HW_REDUCED |
| typedef struct acpi_pcct_hw_reduced_type2 ACPI_PCCT_HW_REDUCED_TYPE2 |
| typedef struct acpi_pcct_shared_memory ACPI_PCCT_SHARED_MEMORY |
| typedef struct acpi_pcct_subspace ACPI_PCCT_SUBSPACE |
| typedef struct acpi_pdtt_channel ACPI_PDTT_CHANNEL |
| typedef struct acpi_pmtt_controller ACPI_PMTT_CONTROLLER |
| typedef struct acpi_pmtt_domain ACPI_PMTT_DOMAIN |
| typedef struct acpi_pmtt_header ACPI_PMTT_HEADER |
| typedef struct acpi_pmtt_physical_component ACPI_PMTT_PHYSICAL_COMPONENT |
| typedef struct acpi_pmtt_socket ACPI_PMTT_SOCKET |
| typedef struct acpi_pptt_cache ACPI_PPTT_CACHE |
| typedef struct acpi_pptt_id ACPI_PPTT_ID |
| typedef struct acpi_pptt_processor ACPI_PPTT_PROCESSOR |
| typedef struct acpi_rasf_parameter_block ACPI_RASF_PARAMETER_BLOCK |
| typedef struct acpi_rasf_patrol_scrub_parameter ACPI_RASF_PATROL_SCRUB_PARAMETER |
| typedef struct acpi_rasf_shared_memory ACPI_RASF_SHARED_MEMORY |
| typedef struct acpi_sdev_header ACPI_SDEV_HEADER |
| typedef struct acpi_sdev_namespace ACPI_SDEV_NAMESPACE |
| typedef struct acpi_sdev_pcie ACPI_SDEV_PCIE |
| typedef struct acpi_sdev_pcie_path ACPI_SDEV_PCIE_PATH |
| typedef struct acpi_table_iort ACPI_TABLE_IORT |
| typedef struct acpi_table_ivrs ACPI_TABLE_IVRS |
| typedef struct acpi_table_lpit ACPI_TABLE_LPIT |
| typedef struct acpi_table_madt ACPI_TABLE_MADT |
| typedef struct acpi_table_mcfg ACPI_TABLE_MCFG |
| typedef struct acpi_table_mchi ACPI_TABLE_MCHI |
| typedef struct acpi_table_mpst ACPI_TABLE_MPST |
| typedef struct acpi_table_msct ACPI_TABLE_MSCT |
| typedef struct acpi_table_msdm ACPI_TABLE_MSDM |
| typedef struct acpi_table_mtmr ACPI_TABLE_MTMR |
| typedef struct acpi_table_nfit ACPI_TABLE_NFIT |
| typedef struct acpi_table_pcct ACPI_TABLE_PCCT |
| typedef struct acpi_table_pdtt ACPI_TABLE_PDTT |
| typedef struct acpi_table_pmtt ACPI_TABLE_PMTT |
| typedef struct acpi_table_pptt ACPI_TABLE_PPTT |
| typedef struct acpi_table_rasf ACPI_TABLE_RASF |
| typedef struct acpi_table_sbst ACPI_TABLE_SBST |
| typedef struct acpi_table_sdei ACPI_TABLE_SDEI |
| typedef struct acpi_table_sdev ACPI_TABLE_SDEV |
| typedef struct nfit_device_handle NFIT_DEVICE_HANDLE |
| enum AcpiIortNodeType |
| enum AcpiIvrsType |
| enum AcpiLpitType |
| enum AcpiMadtGicVersion |
| enum AcpiMadtType |
| enum AcpiNfitType |
| enum AcpiPcctType |
| enum AcpiPpttType |
| enum AcpiRasfCommands |
| enum AcpiRasfStatus |
| enum AcpiSdevType |