virtgpu_drm.h File Reference

#include "drm.h"

Include dependency graph for virtgpu_drm.h:

Go to the source code of this file.

Classes
struct	drm_virtgpu_map
struct	drm_virtgpu_execbuffer_syncobj
struct	drm_virtgpu_execbuffer
struct	drm_virtgpu_getparam
struct	drm_virtgpu_resource_create
struct	drm_virtgpu_resource_info
struct	drm_virtgpu_3d_box
struct	drm_virtgpu_3d_transfer_to_host
struct	drm_virtgpu_3d_transfer_from_host
struct	drm_virtgpu_3d_wait
struct	drm_virtgpu_get_caps
struct	drm_virtgpu_resource_create_blob
struct	drm_virtgpu_context_set_param
struct	drm_virtgpu_context_init

Macros
#define	DRM_VIRTGPU_MAP   0x01
#define	DRM_VIRTGPU_EXECBUFFER   0x02
#define	DRM_VIRTGPU_GETPARAM   0x03
#define	DRM_VIRTGPU_RESOURCE_CREATE   0x04
#define	DRM_VIRTGPU_RESOURCE_INFO   0x05
#define	DRM_VIRTGPU_TRANSFER_FROM_HOST   0x06
#define	DRM_VIRTGPU_TRANSFER_TO_HOST   0x07
#define	DRM_VIRTGPU_WAIT   0x08
#define	DRM_VIRTGPU_GET_CAPS   0x09
#define	DRM_VIRTGPU_RESOURCE_CREATE_BLOB   0x0a
#define	DRM_VIRTGPU_CONTEXT_INIT   0x0b
#define	VIRTGPU_EXECBUF_FENCE_FD_IN   0x01
#define	VIRTGPU_EXECBUF_FENCE_FD_OUT   0x02
#define	VIRTGPU_EXECBUF_RING_IDX   0x04
#define	VIRTGPU_EXECBUF_FLAGS
#define	VIRTGPU_EXECBUF_SYNCOBJ_RESET   0x01
#define	VIRTGPU_EXECBUF_SYNCOBJ_FLAGS
#define	VIRTGPU_PARAM_3D_FEATURES   1 /* do we have 3D features in the hw */
#define	VIRTGPU_PARAM_CAPSET_QUERY_FIX   2 /* do we have the capset fix */
#define	VIRTGPU_PARAM_RESOURCE_BLOB   3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */
#define	VIRTGPU_PARAM_HOST_VISIBLE   4 /* Host blob resources are mappable */
#define	VIRTGPU_PARAM_CROSS_DEVICE   5 /* Cross virtio-device resource sharing */
#define	VIRTGPU_PARAM_CONTEXT_INIT   6 /* DRM_VIRTGPU_CONTEXT_INIT */
#define	VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs   7 /* Bitmask of supported capability set ids */
#define	VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME   8 /* Ability to set debug name from userspace */
#define	VIRTGPU_PARAM_BLOB_ALIGNMENT   9 /* Device alignment requirements for blobs */
#define	VIRTGPU_WAIT_NOWAIT   1 /* like it */
#define	VIRTGPU_DRM_CAPSET_VIRGL   1
#define	VIRTGPU_DRM_CAPSET_VIRGL2   2
#define	VIRTGPU_DRM_CAPSET_GFXSTREAM_VULKAN   3
#define	VIRTGPU_DRM_CAPSET_VENUS   4
#define	VIRTGPU_DRM_CAPSET_CROSS_DOMAIN   5
#define	VIRTGPU_DRM_CAPSET_DRM   6
#define	VIRTGPU_BLOB_MEM_GUEST   0x0001
#define	VIRTGPU_BLOB_MEM_HOST3D   0x0002
#define	VIRTGPU_BLOB_MEM_HOST3D_GUEST   0x0003
#define	VIRTGPU_BLOB_FLAG_USE_MAPPABLE   0x0001
#define	VIRTGPU_BLOB_FLAG_USE_SHAREABLE   0x0002
#define	VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE   0x0004
#define	DRM_VIRTGPU_BLOB_FLAG_HINT_DEFER_MAPPING   0x0001
#define	VIRTGPU_CONTEXT_PARAM_CAPSET_ID   0x0001
#define	VIRTGPU_CONTEXT_PARAM_NUM_RINGS   0x0002
#define	VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK   0x0003
#define	VIRTGPU_CONTEXT_PARAM_DEBUG_NAME   0x0004
#define	VIRTGPU_EVENT_FENCE_SIGNALED   0x90000000
#define	DRM_IOCTL_VIRTGPU_MAP    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
#define	DRM_IOCTL_VIRTGPU_EXECBUFFER
#define	DRM_IOCTL_VIRTGPU_GETPARAM
#define	DRM_IOCTL_VIRTGPU_RESOURCE_CREATE
#define	DRM_IOCTL_VIRTGPU_RESOURCE_INFO
#define	DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST
#define	DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST
#define	DRM_IOCTL_VIRTGPU_WAIT
#define	DRM_IOCTL_VIRTGPU_GET_CAPS
#define	DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB
#define	DRM_IOCTL_VIRTGPU_CONTEXT_INIT

Macro Definition Documentation

DRM_IOCTL_VIRTGPU_CONTEXT_INIT

#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT,       \
        struct drm_virtgpu_context_init)

DRM_IOCTL_VIRTGPU_EXECBUFFER

#define DRM_IOCTL_VIRTGPU_EXECBUFFER

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
        struct drm_virtgpu_execbuffer)

DRM_IOCTL_VIRTGPU_GET_CAPS

#define DRM_IOCTL_VIRTGPU_GET_CAPS

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
    struct drm_virtgpu_get_caps)

DRM_IOCTL_VIRTGPU_GETPARAM

#define DRM_IOCTL_VIRTGPU_GETPARAM

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\
        struct drm_virtgpu_getparam)

DRM_IOCTL_VIRTGPU_MAP

#define DRM_IOCTL_VIRTGPU_MAP    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)

DRM_IOCTL_VIRTGPU_RESOURCE_CREATE

#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE,    \
        struct drm_virtgpu_resource_create)

DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB

#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB,   \
        struct drm_virtgpu_resource_create_blob)

DRM_IOCTL_VIRTGPU_RESOURCE_INFO

#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \
         struct drm_virtgpu_resource_info)

DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST

#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \
        struct drm_virtgpu_3d_transfer_from_host)

DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST

#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST,   \
        struct drm_virtgpu_3d_transfer_to_host)

DRM_IOCTL_VIRTGPU_WAIT

#define DRM_IOCTL_VIRTGPU_WAIT

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT,   \
        struct drm_virtgpu_3d_wait)

DRM_VIRTGPU_BLOB_FLAG_HINT_DEFER_MAPPING

#define DRM_VIRTGPU_BLOB_FLAG_HINT_DEFER_MAPPING   0x0001

DRM_VIRTGPU_CONTEXT_INIT

#define DRM_VIRTGPU_CONTEXT_INIT   0x0b

DRM_VIRTGPU_EXECBUFFER

#define DRM_VIRTGPU_EXECBUFFER   0x02

DRM_VIRTGPU_GET_CAPS

#define DRM_VIRTGPU_GET_CAPS   0x09

DRM_VIRTGPU_GETPARAM

#define DRM_VIRTGPU_GETPARAM   0x03

DRM_VIRTGPU_MAP

#define DRM_VIRTGPU_MAP   0x01

DRM_VIRTGPU_RESOURCE_CREATE

#define DRM_VIRTGPU_RESOURCE_CREATE   0x04

DRM_VIRTGPU_RESOURCE_CREATE_BLOB

#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB   0x0a

DRM_VIRTGPU_RESOURCE_INFO

#define DRM_VIRTGPU_RESOURCE_INFO   0x05

DRM_VIRTGPU_TRANSFER_FROM_HOST

#define DRM_VIRTGPU_TRANSFER_FROM_HOST   0x06

DRM_VIRTGPU_TRANSFER_TO_HOST

#define DRM_VIRTGPU_TRANSFER_TO_HOST   0x07

DRM_VIRTGPU_WAIT

#define DRM_VIRTGPU_WAIT   0x08

VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE

#define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE   0x0004

VIRTGPU_BLOB_FLAG_USE_MAPPABLE

#define VIRTGPU_BLOB_FLAG_USE_MAPPABLE   0x0001

VIRTGPU_BLOB_FLAG_USE_SHAREABLE

#define VIRTGPU_BLOB_FLAG_USE_SHAREABLE   0x0002

VIRTGPU_BLOB_MEM_GUEST

#define VIRTGPU_BLOB_MEM_GUEST   0x0001

VIRTGPU_BLOB_MEM_HOST3D

#define VIRTGPU_BLOB_MEM_HOST3D   0x0002

VIRTGPU_BLOB_MEM_HOST3D_GUEST

#define VIRTGPU_BLOB_MEM_HOST3D_GUEST   0x0003

VIRTGPU_CONTEXT_PARAM_CAPSET_ID

#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID   0x0001

VIRTGPU_CONTEXT_PARAM_DEBUG_NAME

#define VIRTGPU_CONTEXT_PARAM_DEBUG_NAME   0x0004

VIRTGPU_CONTEXT_PARAM_NUM_RINGS

#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS   0x0002

VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK

#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK   0x0003

VIRTGPU_DRM_CAPSET_CROSS_DOMAIN

#define VIRTGPU_DRM_CAPSET_CROSS_DOMAIN   5

VIRTGPU_DRM_CAPSET_DRM

#define VIRTGPU_DRM_CAPSET_DRM   6

VIRTGPU_DRM_CAPSET_GFXSTREAM_VULKAN

#define VIRTGPU_DRM_CAPSET_GFXSTREAM_VULKAN   3

VIRTGPU_DRM_CAPSET_VENUS

#define VIRTGPU_DRM_CAPSET_VENUS   4

VIRTGPU_DRM_CAPSET_VIRGL

#define VIRTGPU_DRM_CAPSET_VIRGL   1

VIRTGPU_DRM_CAPSET_VIRGL2

#define VIRTGPU_DRM_CAPSET_VIRGL2   2

VIRTGPU_EVENT_FENCE_SIGNALED

#define VIRTGPU_EVENT_FENCE_SIGNALED   0x90000000

VIRTGPU_EXECBUF_FENCE_FD_IN

#define VIRTGPU_EXECBUF_FENCE_FD_IN   0x01

VIRTGPU_EXECBUF_FENCE_FD_OUT

#define VIRTGPU_EXECBUF_FENCE_FD_OUT   0x02

VIRTGPU_EXECBUF_FLAGS

#define VIRTGPU_EXECBUF_FLAGS

Value:

        (\
        VIRTGPU_EXECBUF_FENCE_FD_IN |\
        VIRTGPU_EXECBUF_FENCE_FD_OUT |\
        VIRTGPU_EXECBUF_RING_IDX |\
        0)

VIRTGPU_EXECBUF_RING_IDX

#define VIRTGPU_EXECBUF_RING_IDX   0x04

VIRTGPU_EXECBUF_SYNCOBJ_FLAGS

#define VIRTGPU_EXECBUF_SYNCOBJ_FLAGS

Value:

        ( \
        VIRTGPU_EXECBUF_SYNCOBJ_RESET | \
        0)

VIRTGPU_EXECBUF_SYNCOBJ_RESET

#define VIRTGPU_EXECBUF_SYNCOBJ_RESET   0x01

VIRTGPU_PARAM_3D_FEATURES

#define VIRTGPU_PARAM_3D_FEATURES   1 /* do we have 3D features in the hw */

VIRTGPU_PARAM_BLOB_ALIGNMENT

#define VIRTGPU_PARAM_BLOB_ALIGNMENT   9 /* Device alignment requirements for blobs */

VIRTGPU_PARAM_CAPSET_QUERY_FIX

#define VIRTGPU_PARAM_CAPSET_QUERY_FIX   2 /* do we have the capset fix */

VIRTGPU_PARAM_CONTEXT_INIT

#define VIRTGPU_PARAM_CONTEXT_INIT   6 /* DRM_VIRTGPU_CONTEXT_INIT */

VIRTGPU_PARAM_CROSS_DEVICE

#define VIRTGPU_PARAM_CROSS_DEVICE   5 /* Cross virtio-device resource sharing */

VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME

#define VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME   8 /* Ability to set debug name from userspace */

VIRTGPU_PARAM_HOST_VISIBLE

#define VIRTGPU_PARAM_HOST_VISIBLE   4 /* Host blob resources are mappable */

VIRTGPU_PARAM_RESOURCE_BLOB

#define VIRTGPU_PARAM_RESOURCE_BLOB   3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */

VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs

#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs   7 /* Bitmask of supported capability set ids */

VIRTGPU_WAIT_NOWAIT

#define VIRTGPU_WAIT_NOWAIT   1 /* like it */