xeneva-source-reference/dwc2__reg_8h_source.html

#ifndef __DWC2_REG_H__

#define __DWC2_REG_H__


#include <stdint.h>


struct dwc2_hc_regs {

    uint32_t hcchar;

    uint32_t hcsplt;

    uint32_t hcint;

    uint32_t hcintmsk;

    uint32_t hctsiz;

    uint32_t hcdma;

    uint32_t reserved;

    uint32_t hcdmab;

};


struct dwc2_host_regs {

    uint32_t hcfg;

    uint32_t hfir;

    uint32_t hdnum;

    uint32_t _pad_0x40c;

    uint32_t hptxsts;

    uint32_t haint;

    uint32_t haintmsk;

    uint32_t hflbaddr;

};


struct dwc2_core_regs {

    uint32_t gotgctl;

    uint32_t gotgint;

    uint32_t gahbcfg;

    uint32_t gusbcfg;

    uint32_t grstctl;

    uint32_t gintsts;

    uint32_t gintmsk;

    uint32_t grxstsr;

    uint32_t grxstsp;

    uint32_t grxfsiz;

    uint32_t gnptxfsiz;

    uint32_t gnptxsts;

    uint32_t gi2cctl;

    uint32_t gpvndctl;

    uint32_t ggpio;

    uint32_t guid;

    uint32_t gsnpsid;

    uint32_t ghwcfg1;

    uint32_t ghwcfg2;

    uint32_t ghwcfg3;

    uint32_t ghwcfg4;

    uint32_t glpmcfg;

    uint32_t _pad_0x58_0x9c[42];

    uint32_t hptxfsiz;

    uint32_t dptxfsiz_dieptxf[15];

    uint32_t _pad_0x140_0x3fc[176];

    struct dwc2_host_regs host_regs;

    uint32_t _pad_0x420_0x43c[8];

    uint32_t hprt0;

    uint32_t _pad_0x444_0x4fc[47];

    struct dwc2_hc_regs hc_regs[16];

    uint32_t _pad_0x700_0xe00[448];

    uint32_t pcgcctl;

};


typedef union {

    struct {

        uint32_t prtaddr : 7;

        uint32_t hubaddr : 7;

        uint32_t xactpos : 2;

        uint32_t compsplt : 1;

        uint32_t reserved : 14;

        uint32_t spltena : 1;

    };

    uint32_t val;

}dwc2_hcsplit_t;


#define DWC2_GOTGCTL_SESREQSCS              (1ULL << 0)

#define DWC2_GOTGCTL_SESREQSCS_OFFSET           0UL

#define DWC2_GOTGCTL_SESREQ             (1ULL << 1)

#define DWC2_GOTGCTL_SESREQ_OFFSET          1UL

#define DWC2_GOTGCTL_HSTNEGSCS              (1ULL << 8)

#define DWC2_GOTGCTL_HSTNEGSCS_OFFSET           8UL

#define DWC2_GOTGCTL_HNPREQ             (1ULL << 9)

#define DWC2_GOTGCTL_HNPREQ_OFFSET          9ULL

#define DWC2_GOTGCTL_HSTSETHNPEN            (1ULL << 10)

#define DWC2_GOTGCTL_HSTSETHNPEN_OFFSET         10ULL

#define DWC2_GOTGCTL_DEVHNPEN               (1ULL << 11)

#define DWC2_GOTGCTL_DEVHNPEN_OFFSET            11ULL

#define DWC2_GOTGCTL_CONIDSTS               (1ULL << 16)

#define DWC2_GOTGCTL_CONIDSTS_OFFSET            16ULL

#define DWC2_GOTGCTL_DBNCTIME               (1ULL << 17)

#define DWC2_GOTGCTL_DBNCTIME_OFFSET            17ULL

#define DWC2_GOTGCTL_ASESVLD                (1ULL << 18)

#define DWC2_GOTGCTL_ASESVLD_OFFSET         18ULL

#define DWC2_GOTGCTL_BSESVLD                (1ULL << 19)

#define DWC2_GOTGCTL_BSESVLD_OFFSET         19ULL

#define DWC2_GOTGCTL_OTGVER             (1ULL << 20)

#define DWC2_GOTGCTL_OTGVER_OFFSET          20ULL

#define DWC2_GOTGINT_SESENDDET              (1ULL << 2)

#define DWC2_GOTGINT_SESENDDET_OFFSET           2ULL

#define DWC2_GOTGINT_SESREQSUCSTSCHNG           (1ULL << 8)

#define DWC2_GOTGINT_SESREQSUCSTSCHNG_OFFSET        8ULL

#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG           (1ULL << 9)

#define DWC2_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET        9ULL

#define DWC2_GOTGINT_RESERVER10_16_MASK         (0x7F << 10)

#define DWC2_GOTGINT_RESERVER10_16_OFFSET       10ULL

#define DWC2_GOTGINT_HSTNEGDET              (1ULL << 17)

#define DWC2_GOTGINT_HSTNEGDET_OFFSET           17ULL

#define DWC2_GOTGINT_ADEVTOUTCHNG           (1ULL << 18)

#define DWC2_GOTGINT_ADEVTOUTCHNG_OFFSET        18ULL

#define DWC2_GOTGINT_DEBDONE                (1ULL << 19)

#define DWC2_GOTGINT_DEBDONE_OFFSET         19ULL

#define DWC2_GAHBCFG_GLBLINTRMSK            (1ULL << 0)

#define DWC2_GAHBCFG_GLBLINTRMSK_OFFSET         0ULL

#define DWC2_GAHBCFG_HBURSTLEN_SINGLE           (0ULL << 1)

#define DWC2_GAHBCFG_HBURSTLEN_INCR         (1ULL << 1)

#define DWC2_GAHBCFG_HBURSTLEN_INCR4            (3ULL << 1)

#define DWC2_GAHBCFG_HBURSTLEN_INCR8            (5ULL << 1)

#define DWC2_GAHBCFG_HBURSTLEN_INCR16           (7ULL << 1)

#define DWC2_GAHBCFG_HBURSTLEN_MASK         (0xF << 1)

#define DWC2_GAHBCFG_HBURSTLEN_OFFSET           1ULL

#define DWC2_GAHBCFG_DMAENABLE              (1ULL << 5)

#define DWC2_GAHBCFG_DMAENABLE_OFFSET           5ULL

#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL      (1ULL << 7)

#define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL_OFFSET   7ULL

#define DWC2_GAHBCFG_PTXFEMPLVL             (1ULL << 8)

#define DWC2_GAHBCFG_PTXFEMPLVL_OFFSET          8ULL

#define DWC2_GUSBCFG_TOUTCAL_MASK           (0x7 << 0)

#define DWC2_GUSBCFG_TOUTCAL_OFFSET         0ULL

#define DWC2_GUSBCFG_PHYIF              (1ULL << 3)

#define DWC2_GUSBCFG_PHYIF_OFFSET           3ULL

#define DWC2_GUSBCFG_ULPI_UTMI_SEL          (1ULL << 4)

#define DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET       4ULL

#define DWC2_GUSBCFG_FSINTF             (1ULL << 5)

#define DWC2_GUSBCFG_FSINTF_OFFSET          5ULL

#define DWC2_GUSBCFG_PHYSEL             (1ULL << 6)

#define DWC2_GUSBCFG_PHYSEL_OFFSET          6ULL

#define DWC2_GUSBCFG_DDRSEL             (1ULL << 7)

#define DWC2_GUSBCFG_DDRSEL_OFFSET          7ULL

#define DWC2_GUSBCFG_SRPCAP             (1ULL << 8)

#define DWC2_GUSBCFG_SRPCAP_OFFSET          8ULL

#define DWC2_GUSBCFG_HNPCAP             (1ULL << 9)

#define DWC2_GUSBCFG_HNPCAP_OFFSET          9ULL

#define DWC2_GUSBCFG_USBTRDTIM_MASK         (0xF << 10)

#define DWC2_GUSBCFG_USBTRDTIM_OFFSET           10ULL

#define DWC2_GUSBCFG_NPTXFRWNDEN            (1ULL << 14)

#define DWC2_GUSBCFG_NPTXFRWNDEN_OFFSET         14ULL

#define DWC2_GUSBCFG_PHYLPWRCLKSEL          (1ULL << 15)

#define DWC2_GUSBCFG_PHYLPWRCLKSEL_OFFSET       15ULL

#define DWC2_GUSBCFG_OTGUTMIFSSEL           (1ULL << 16)

#define DWC2_GUSBCFG_OTGUTMIFSSEL_OFFSET        16ULL

#define DWC2_GUSBCFG_ULPI_FSLS              (1ULL << 17)

#define DWC2_GUSBCFG_ULPI_FSLS_OFFSET           17ULL

#define DWC2_GUSBCFG_ULPI_AUTO_RES          (1ULL << 18)

#define DWC2_GUSBCFG_ULPI_AUTO_RES_OFFSET       18ULL

#define DWC2_GUSBCFG_ULPI_CLK_SUS_M         (1ULL << 19)

#define DWC2_GUSBCFG_ULPI_CLK_SUS_M_OFFSET      19ULL

#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV          (1ULL << 20)

#define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV_OFFSET       20ULL

#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR        (1ULL << 21)

#define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR_OFFSET 21ULL

#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE          (1ULL << 22)

#define DWC2_GUSBCFG_TERM_SEL_DL_PULSE_OFFSET       22ULL

#define DWC2_GUSBCFG_INDICATOR_PASSTHROUGH      (1ULL << 24)

#define DWC2_GUSBCFG_INDICATOR_PASSTHROUGH_OFFSET   24ULL

#define DWC2_GUSBCFG_IC_USB_CAP             (1ULL << 26)

#define DWC2_GUSBCFG_IC_USB_CAP_OFFSET          26ULL

#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE     (1ULL << 27)

#define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE_OFFSET  27ULL

#define DWC2_GUSBCFG_TX_END_DELAY           (1ULL << 28)

#define DWC2_GUSBCFG_TX_END_DELAY_OFFSET        28ULL

#define DWC2_GUSBCFG_FORCEHOSTMODE          (1ULL << 29)

#define DWC2_GUSBCFG_FORCEHOSTMODE_OFFSET       29ULL

#define DWC2_GUSBCFG_FORCEDEVMODE           (1ULL << 30)

#define DWC2_GUSBCFG_FORCEDEVMODE_OFFSET        30ULL

#define DWC2_GLPMCTL_LPM_CAP_EN             (1ULL << 0)

#define DWC2_GLPMCTL_LPM_CAP_EN_OFFSET          0ULL

#define DWC2_GLPMCTL_APPL_RESP              (1ULL << 1)

#define DWC2_GLPMCTL_APPL_RESP_OFFSET           1ULL

#define DWC2_GLPMCTL_HIRD_MASK              (0xF << 2)

#define DWC2_GLPMCTL_HIRD_OFFSET            2ULL

#define DWC2_GLPMCTL_REM_WKUP_EN            (1ULL << 6)

#define DWC2_GLPMCTL_REM_WKUP_EN_OFFSET         6ULL

#define DWC2_GLPMCTL_EN_UTMI_SLEEP          (1ULL << 7)

#define DWC2_GLPMCTL_EN_UTMI_SLEEP_OFFSET       7ULL

#define DWC2_GLPMCTL_HIRD_THRES_MASK            (0x1F << 8)

#define DWC2_GLPMCTL_HIRD_THRES_OFFSET          8ULL

#define DWC2_GLPMCTL_LPM_RESP_MASK          (0x3 << 13)

#define DWC2_GLPMCTL_LPM_RESP_OFFSET            13ULL

#define DWC2_GLPMCTL_PRT_SLEEP_STS          (1ULL << 15)

#define DWC2_GLPMCTL_PRT_SLEEP_STS_OFFSET       15ULL

#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK       (1ULL << 16)

#define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK_OFFSET    16ULL

#define DWC2_GLPMCTL_LPM_CHAN_INDEX_MASK        (0xF << 17)

#define DWC2_GLPMCTL_LPM_CHAN_INDEX_OFFSET      17ULL

#define DWC2_GLPMCTL_RETRY_COUNT_MASK           (0x7 << 21)

#define DWC2_GLPMCTL_RETRY_COUNT_OFFSET         21ULL

#define DWC2_GLPMCTL_SEND_LPM               (1ULL << 24)

#define DWC2_GLPMCTL_SEND_LPM_OFFSET            24ULL

#define DWC2_GLPMCTL_RETRY_COUNT_STS_MASK       (0x7 << 25)

#define DWC2_GLPMCTL_RETRY_COUNT_STS_OFFSET     25ULL

#define DWC2_GLPMCTL_HSIC_CONNECT           (1ULL << 30)

#define DWC2_GLPMCTL_HSIC_CONNECT_OFFSET        30ULL

#define DWC2_GLPMCTL_INV_SEL_HSIC           (1ULL << 31)

#define DWC2_GLPMCTL_INV_SEL_HSIC_OFFSET        31ULL

#define DWC2_GRSTCTL_CSFTRST                (1ULL << 0)

#define DWC2_GRSTCTL_CSFTRST_OFFSET         0ULL

#define DWC2_GRSTCTL_HSFTRST                (1ULL << 1)

#define DWC2_GRSTCTL_HSFTRST_OFFSET         1ULL

#define DWC2_GRSTCTL_HSTFRM             (1ULL << 2)

#define DWC2_GRSTCTL_HSTFRM_OFFSET          2ULL

#define DWC2_GRSTCTL_INTKNQFLSH             (1ULL << 3)

#define DWC2_GRSTCTL_INTKNQFLSH_OFFSET          3ULL

#define DWC2_GRSTCTL_RXFFLSH                (1ULL << 4)

#define DWC2_GRSTCTL_RXFFLSH_OFFSET         4ULL

#define DWC2_GRSTCTL_TXFFLSH                (1ULL << 5)

#define DWC2_GRSTCTL_TXFFLSH_OFFSET         5ULL

#define DWC2_GRSTCTL_TXFNUM_MASK            (0x1F << 6)

#define DWC2_GRSTCTL_TXFNUM_OFFSET          6ULL

#define DWC2_GRSTCTL_DMAREQ             (1ULL << 30)

#define DWC2_GRSTCTL_DMAREQ_OFFSET          30ULL

#define DWC2_GRSTCTL_AHBIDLE                (1ULL << 31)

#define DWC2_GRSTCTL_AHBIDLE_OFFSET         31ULL

#define DWC2_GINTMSK_MODEMISMATCH           (1ULL << 1)

#define DWC2_GINTMSK_MODEMISMATCH_OFFSET        1ULL

#define DWC2_GINTMSK_OTGINTR                (1ULL << 2)

#define DWC2_GINTMSK_OTGINTR_OFFSET         2ULL

#define DWC2_GINTMSK_SOFINTR                (1ULL << 3)

#define DWC2_GINTMSK_SOFINTR_OFFSET         3ULL

#define DWC2_GINTMSK_RXSTSQLVL              (1ULL << 4)

#define DWC2_GINTMSK_RXSTSQLVL_OFFSET           4ULL

#define DWC2_GINTMSK_NPTXFEMPTY             (1ULL << 5)

#define DWC2_GINTMSK_NPTXFEMPTY_OFFSET          5ULL

#define DWC2_GINTMSK_GINNAKEFF              (1ULL << 6)

#define DWC2_GINTMSK_GINNAKEFF_OFFSET           6ULL

#define DWC2_GINTMSK_GOUTNAKEFF             (1ULL << 7)

#define DWC2_GINTMSK_GOUTNAKEFF_OFFSET          7ULL

#define DWC2_GINTMSK_I2CINTR                (1ULL << 9)

#define DWC2_GINTMSK_I2CINTR_OFFSET         9ULL

#define DWC2_GINTMSK_ERLYSUSPEND            (1ULL << 10)

#define DWC2_GINTMSK_ERLYSUSPEND_OFFSET         10ULL

#define DWC2_GINTMSK_USBSUSPEND             (1ULL << 11)

#define DWC2_GINTMSK_USBSUSPEND_OFFSET          11ULL

#define DWC2_GINTMSK_USBRESET               (1ULL << 12)

#define DWC2_GINTMSK_USBRESET_OFFSET            12ULL

#define DWC2_GINTMSK_ENUMDONE               (1ULL << 13)

#define DWC2_GINTMSK_ENUMDONE_OFFSET            13ULL

#define DWC2_GINTMSK_ISOOUTDROP             (1ULL << 14)

#define DWC2_GINTMSK_ISOOUTDROP_OFFSET          14ULL

#define DWC2_GINTMSK_EOPFRAME               (1ULL << 15)

#define DWC2_GINTMSK_EOPFRAME_OFFSET            15ULL

#define DWC2_GINTMSK_EPMISMATCH             (1ULL << 17)

#define DWC2_GINTMSK_EPMISMATCH_OFFSET          17ULL

#define DWC2_GINTMSK_INEPINTR               (1ULL << 18)

#define DWC2_GINTMSK_INEPINTR_OFFSET            18ULL

#define DWC2_GINTMSK_OUTEPINTR              (1ULL << 19)

#define DWC2_GINTMSK_OUTEPINTR_OFFSET           19ULL

#define DWC2_GINTMSK_INCOMPLISOIN           (1ULL << 20)

#define DWC2_GINTMSK_INCOMPLISOIN_OFFSET        20ULL

#define DWC2_GINTMSK_INCOMPLISOOUT          (1ULL << 21)

#define DWC2_GINTMSK_INCOMPLISOOUT_OFFSET       21ULL

#define DWC2_GINTMSK_PORTINTR               (1ULL << 24)

#define DWC2_GINTMSK_PORTINTR_OFFSET            24ULL

#define DWC2_GINTMSK_HCINTR             (1ULL << 25)

#define DWC2_GINTMSK_HCINTR_OFFSET          25ULL

#define DWC2_GINTMSK_PTXFEMPTY              (1ULL << 26)

#define DWC2_GINTMSK_PTXFEMPTY_OFFSET           26ULL

#define DWC2_GINTMSK_LPMTRANRCVD            (1ULL << 27)

#define DWC2_GINTMSK_LPMTRANRCVD_OFFSET         27ULL

#define DWC2_GINTMSK_CONIDSTSCHNG           (1ULL << 28)

#define DWC2_GINTMSK_CONIDSTSCHNG_OFFSET        28ULL

#define DWC2_GINTMSK_DISCONNECT             (1ULL << 29)

#define DWC2_GINTMSK_DISCONNECT_OFFSET          29ULL

#define DWC2_GINTMSK_SESSREQINTR            (1ULL << 30)

#define DWC2_GINTMSK_SESSREQINTR_OFFSET         30ULL

#define DWC2_GINTMSK_WKUPINTR               (1ULL << 31)

#define DWC2_GINTMSK_WKUPINTR_OFFSET            31ULL

#define DWC2_GINTSTS_CURMODE_DEVICE         (0ULL << 0)

#define DWC2_GINTSTS_CURMODE_HOST           (1ULL << 0)

#define DWC2_GINTSTS_CURMODE                (1ULL << 0)

#define DWC2_GINTSTS_CURMODE_OFFSET         0ULL

#define DWC2_GINTSTS_MODEMISMATCH           (1ULL << 1)

#define DWC2_GINTSTS_MODEMISMATCH_OFFSET        1ULL

#define DWC2_GINTSTS_OTGINTR                (1ULL << 2)

#define DWC2_GINTSTS_OTGINTR_OFFSET         2ULL

#define DWC2_GINTSTS_SOFINTR                (1ULL << 3)

#define DWC2_GINTSTS_SOFINTR_OFFSET         3ULL

#define DWC2_GINTSTS_RXSTSQLVL              (1ULL << 4)

#define DWC2_GINTSTS_RXSTSQLVL_OFFSET           4ULL

#define DWC2_GINTSTS_NPTXFEMPTY             (1ULL << 5)

#define DWC2_GINTSTS_NPTXFEMPTY_OFFSET          5ULL

#define DWC2_GINTSTS_GINNAKEFF              (1ULL << 6)

#define DWC2_GINTSTS_GINNAKEFF_OFFSET           6ULL

#define DWC2_GINTSTS_GOUTNAKEFF             (1ULL << 7)

#define DWC2_GINTSTS_GOUTNAKEFF_OFFSET          7ULL

#define DWC2_GINTSTS_I2CINTR                (1ULL << 9)

#define DWC2_GINTSTS_I2CINTR_OFFSET         9ULL

#define DWC2_GINTSTS_ERLYSUSPEND            (1ULL << 10)

#define DWC2_GINTSTS_ERLYSUSPEND_OFFSET         10ULL

#define DWC2_GINTSTS_USBSUSPEND             (1ULL << 11)

#define DWC2_GINTSTS_USBSUSPEND_OFFSET          11ULL

#define DWC2_GINTSTS_USBRESET               (1ULL << 12)

#define DWC2_GINTSTS_USBRESET_OFFSET            12ULL

#define DWC2_GINTSTS_ENUMDONE               (1ULL << 13)

#define DWC2_GINTSTS_ENUMDONE_OFFSET            13ULL

#define DWC2_GINTSTS_ISOOUTDROP             (1ULL << 14)

#define DWC2_GINTSTS_ISOOUTDROP_OFFSET          14ULL

#define DWC2_GINTSTS_EOPFRAME               (1ULL << 15)

#define DWC2_GINTSTS_EOPFRAME_OFFSET            15ULL

#define DWC2_GINTSTS_INTOKENRX              (1ULL << 16)

#define DWC2_GINTSTS_INTOKENRX_OFFSET           16ULL

#define DWC2_GINTSTS_EPMISMATCH             (1ULL << 17)

#define DWC2_GINTSTS_EPMISMATCH_OFFSET          17ULL

#define DWC2_GINTSTS_INEPINT                (1ULL << 18)

#define DWC2_GINTSTS_INEPINT_OFFSET         18ULL

#define DWC2_GINTSTS_OUTEPINTR              (1ULL << 19)

#define DWC2_GINTSTS_OUTEPINTR_OFFSET           19ULL

#define DWC2_GINTSTS_INCOMPLISOIN           (1ULL << 20)

#define DWC2_GINTSTS_INCOMPLISOIN_OFFSET        20ULL

#define DWC2_GINTSTS_INCOMPLISOOUT          (1ULL << 21)

#define DWC2_GINTSTS_INCOMPLISOOUT_OFFSET       21ULL

#define DWC2_GINTSTS_PORTINTR               (1ULL << 24)

#define DWC2_GINTSTS_PORTINTR_OFFSET            24ULL

#define DWC2_GINTSTS_HCINTR             (1ULL << 25)

#define DWC2_GINTSTS_HCINTR_OFFSET          25ULL

#define DWC2_GINTSTS_PTXFEMPTY              (1ULL << 26)

#define DWC2_GINTSTS_PTXFEMPTY_OFFSET           26ULL

#define DWC2_GINTSTS_LPMTRANRCVD            (1ULL << 27)

#define DWC2_GINTSTS_LPMTRANRCVD_OFFSET         27ULL

#define DWC2_GINTSTS_CONIDSTSCHNG           (1ULL << 28)

#define DWC2_GINTSTS_CONIDSTSCHNG_OFFSET        28ULL

#define DWC2_GINTSTS_DISCONNECT             (1ULL << 29)

#define DWC2_GINTSTS_DISCONNECT_OFFSET          29ULL

#define DWC2_GINTSTS_SESSREQINTR            (1ULL << 30)

#define DWC2_GINTSTS_SESSREQINTR_OFFSET         30ULL

#define DWC2_GINTSTS_WKUPINTR               (1ULL << 31)

#define DWC2_GINTSTS_WKUPINTR_OFFSET            31ULL

#define DWC2_GRXSTS_EPNUM_MASK              (0xF << 0)

#define DWC2_GRXSTS_EPNUM_OFFSET            0ULL

#define DWC2_GRXSTS_BCNT_MASK               (0x7FF << 4)

#define DWC2_GRXSTS_BCNT_OFFSET             4ULL

#define DWC2_GRXSTS_DPID_MASK               (0x3 << 15)

#define DWC2_GRXSTS_DPID_OFFSET             15ULL

#define DWC2_GRXSTS_PKTSTS_MASK             (0xF << 17)

#define DWC2_GRXSTS_PKTSTS_OFFSET           17ULL

#define DWC2_GRXSTS_FN_MASK             (0xF << 21)

#define DWC2_GRXSTS_FN_OFFSET               21

#define DWC2_FIFOSIZE_STARTADDR_MASK            (0xFFFF << 0)

#define DWC2_FIFOSIZE_STARTADDR_OFFSET          0

#define DWC2_FIFOSIZE_DEPTH_MASK            (0xFFFF << 16)

#define DWC2_FIFOSIZE_DEPTH_OFFSET          16

#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_MASK        (0xFFFF << 0)

#define DWC2_GNPTXSTS_NPTXFSPCAVAIL_OFFSET      0

#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_MASK        (0xFF << 16)

#define DWC2_GNPTXSTS_NPTXQSPCAVAIL_OFFSET      16

#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE        (1 << 24)

#define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE_OFFSET     24

#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_MASK       (0x3 << 25)

#define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_OFFSET     25

#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_MASK       (0xF << 27)

#define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_OFFSET     27

#define DWC2_DTXFSTS_TXFSPCAVAIL_MASK           (0xFFFF << 0)

#define DWC2_DTXFSTS_TXFSPCAVAIL_OFFSET         0

#define DWC2_GI2CCTL_RWDATA_MASK            (0xFF << 0)

#define DWC2_GI2CCTL_RWDATA_OFFSET          0

#define DWC2_GI2CCTL_REGADDR_MASK           (0xFF << 8)

#define DWC2_GI2CCTL_REGADDR_OFFSET         8

#define DWC2_GI2CCTL_ADDR_MASK              (0x7F << 16)

#define DWC2_GI2CCTL_ADDR_OFFSET            16

#define DWC2_GI2CCTL_I2CEN              (1 << 23)

#define DWC2_GI2CCTL_I2CEN_OFFSET           23

#define DWC2_GI2CCTL_ACK                (1 << 24)

#define DWC2_GI2CCTL_ACK_OFFSET             24

#define DWC2_GI2CCTL_I2CSUSPCTL             (1 << 25)

#define DWC2_GI2CCTL_I2CSUSPCTL_OFFSET          25

#define DWC2_GI2CCTL_I2CDEVADDR_MASK            (0x3 << 26)

#define DWC2_GI2CCTL_I2CDEVADDR_OFFSET          26

#define DWC2_GI2CCTL_RW                 (1 << 30)

#define DWC2_GI2CCTL_RW_OFFSET              30

#define DWC2_GI2CCTL_BSYDNE             (1 << 31)

#define DWC2_GI2CCTL_BSYDNE_OFFSET          31

#define DWC2_HWCFG1_EP_DIR0_MASK            (0x3 << 0)

#define DWC2_HWCFG1_EP_DIR0_OFFSET          0

#define DWC2_HWCFG1_EP_DIR1_MASK            (0x3 << 2)

#define DWC2_HWCFG1_EP_DIR1_OFFSET          2

#define DWC2_HWCFG1_EP_DIR2_MASK            (0x3 << 4)

#define DWC2_HWCFG1_EP_DIR2_OFFSET          4

#define DWC2_HWCFG1_EP_DIR3_MASK            (0x3 << 6)

#define DWC2_HWCFG1_EP_DIR3_OFFSET          6

#define DWC2_HWCFG1_EP_DIR4_MASK            (0x3 << 8)

#define DWC2_HWCFG1_EP_DIR4_OFFSET          8

#define DWC2_HWCFG1_EP_DIR5_MASK            (0x3 << 10)

#define DWC2_HWCFG1_EP_DIR5_OFFSET          10

#define DWC2_HWCFG1_EP_DIR6_MASK            (0x3 << 12)

#define DWC2_HWCFG1_EP_DIR6_OFFSET          12

#define DWC2_HWCFG1_EP_DIR7_MASK            (0x3 << 14)

#define DWC2_HWCFG1_EP_DIR7_OFFSET          14

#define DWC2_HWCFG1_EP_DIR8_MASK            (0x3 << 16)

#define DWC2_HWCFG1_EP_DIR8_OFFSET          16

#define DWC2_HWCFG1_EP_DIR9_MASK            (0x3 << 18)

#define DWC2_HWCFG1_EP_DIR9_OFFSET          18

#define DWC2_HWCFG1_EP_DIR10_MASK           (0x3 << 20)

#define DWC2_HWCFG1_EP_DIR10_OFFSET         20

#define DWC2_HWCFG1_EP_DIR11_MASK           (0x3 << 22)

#define DWC2_HWCFG1_EP_DIR11_OFFSET         22

#define DWC2_HWCFG1_EP_DIR12_MASK           (0x3 << 24)

#define DWC2_HWCFG1_EP_DIR12_OFFSET         24

#define DWC2_HWCFG1_EP_DIR13_MASK           (0x3 << 26)

#define DWC2_HWCFG1_EP_DIR13_OFFSET         26

#define DWC2_HWCFG1_EP_DIR14_MASK           (0x3 << 28)

#define DWC2_HWCFG1_EP_DIR14_OFFSET         28

#define DWC2_HWCFG1_EP_DIR15_MASK           (0x3 << 30)

#define DWC2_HWCFG1_EP_DIR15_OFFSET         30

#define DWC2_HWCFG2_OP_MODE_MASK            (0x7 << 0)

#define DWC2_HWCFG2_OP_MODE_OFFSET          0

#define DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY     (0x0 << 3)

#define DWC2_HWCFG2_ARCHITECTURE_EXT_DMA        (0x1 << 3)

#define DWC2_HWCFG2_ARCHITECTURE_INT_DMA        (0x2 << 3)

#define DWC2_HWCFG2_ARCHITECTURE_MASK           (0x3 << 3)

#define DWC2_HWCFG2_ARCHITECTURE_OFFSET         3

#define DWC2_HWCFG2_POINT2POINT             (1 << 5)

#define DWC2_HWCFG2_POINT2POINT_OFFSET          5

#define DWC2_HWCFG2_HS_PHY_TYPE_MASK            (0x3 << 6)

#define DWC2_HWCFG2_HS_PHY_TYPE_OFFSET          6

#define DWC2_HWCFG2_FS_PHY_TYPE_MASK            (0x3 << 8)

#define DWC2_HWCFG2_FS_PHY_TYPE_OFFSET          8

#define DWC2_HWCFG2_NUM_DEV_EP_MASK         (0xF << 10)

#define DWC2_HWCFG2_NUM_DEV_EP_OFFSET           10

#define DWC2_HWCFG2_NUM_HOST_CHAN_MASK          (0xF << 14)

#define DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET        14

#define DWC2_HWCFG2_PERIO_EP_SUPPORTED          (1 << 18)

#define DWC2_HWCFG2_PERIO_EP_SUPPORTED_OFFSET       18

#define DWC2_HWCFG2_DYNAMIC_FIFO            (1 << 19)

#define DWC2_HWCFG2_DYNAMIC_FIFO_OFFSET         19

#define DWC2_HWCFG2_MULTI_PROC_INT          (1 << 20)

#define DWC2_HWCFG2_MULTI_PROC_INT_OFFSET       20

#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_MASK        (0x3 << 22)

#define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_OFFSET      22

#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK      (0x3 << 24)

#define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_OFFSET    24

#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_MASK      (0x1F << 26)

#define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_OFFSET        26

#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_MASK       (0xF << 0)

#define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_OFFSET     0

#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK     (0x7 << 4)

#define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_OFFSET   4

#define DWC2_HWCFG3_OTG_FUNC                (1 << 7)

#define DWC2_HWCFG3_OTG_FUNC_OFFSET         7

#define DWC2_HWCFG3_I2C                 (1 << 8)

#define DWC2_HWCFG3_I2C_OFFSET              8

#define DWC2_HWCFG3_VENDOR_CTRL_IF          (1 << 9)

#define DWC2_HWCFG3_VENDOR_CTRL_IF_OFFSET       9

#define DWC2_HWCFG3_OPTIONAL_FEATURES           (1 << 10)

#define DWC2_HWCFG3_OPTIONAL_FEATURES_OFFSET        10

#define DWC2_HWCFG3_SYNCH_RESET_TYPE            (1 << 11)

#define DWC2_HWCFG3_SYNCH_RESET_TYPE_OFFSET     11

#define DWC2_HWCFG3_OTG_ENABLE_IC_USB           (1 << 12)

#define DWC2_HWCFG3_OTG_ENABLE_IC_USB_OFFSET        12

#define DWC2_HWCFG3_OTG_ENABLE_HSIC         (1 << 13)

#define DWC2_HWCFG3_OTG_ENABLE_HSIC_OFFSET      13

#define DWC2_HWCFG3_OTG_LPM_EN              (1 << 15)

#define DWC2_HWCFG3_OTG_LPM_EN_OFFSET           15

#define DWC2_HWCFG3_DFIFO_DEPTH_MASK            (0xFFFF << 16)

#define DWC2_HWCFG3_DFIFO_DEPTH_OFFSET          16

#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_MASK        (0xF << 0)

#define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_OFFSET      0

#define DWC2_HWCFG4_POWER_OPTIMIZ           (1 << 4)

#define DWC2_HWCFG4_POWER_OPTIMIZ_OFFSET        4

#define DWC2_HWCFG4_MIN_AHB_FREQ_MASK           (0x1FF << 5)

#define DWC2_HWCFG4_MIN_AHB_FREQ_OFFSET         5

#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_MASK        (0x3 << 14)

#define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_OFFSET      14

#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_MASK       (0xF << 16)

#define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_OFFSET     16

#define DWC2_HWCFG4_IDDIG_FILT_EN           (1 << 20)

#define DWC2_HWCFG4_IDDIG_FILT_EN_OFFSET        20

#define DWC2_HWCFG4_VBUS_VALID_FILT_EN          (1 << 21)

#define DWC2_HWCFG4_VBUS_VALID_FILT_EN_OFFSET       21

#define DWC2_HWCFG4_A_VALID_FILT_EN         (1 << 22)

#define DWC2_HWCFG4_A_VALID_FILT_EN_OFFSET      22

#define DWC2_HWCFG4_B_VALID_FILT_EN         (1 << 23)

#define DWC2_HWCFG4_B_VALID_FILT_EN_OFFSET      23

#define DWC2_HWCFG4_SESSION_END_FILT_EN         (1 << 24)

#define DWC2_HWCFG4_SESSION_END_FILT_EN_OFFSET      24

#define DWC2_HWCFG4_DED_FIFO_EN             (1 << 25)

#define DWC2_HWCFG4_DED_FIFO_EN_OFFSET          25

#define DWC2_HWCFG4_NUM_IN_EPS_MASK         (0xF << 26)

#define DWC2_HWCFG4_NUM_IN_EPS_OFFSET           26

#define DWC2_HWCFG4_DESC_DMA                (1 << 30)

#define DWC2_HWCFG4_DESC_DMA_OFFSET         30

#define DWC2_HWCFG4_DESC_DMA_DYN            (1 << 31)

#define DWC2_HWCFG4_DESC_DMA_DYN_OFFSET         31

#define DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ         0

#define DWC2_HCFG_FSLSPCLKSEL_48_MHZ            1

#define DWC2_HCFG_FSLSPCLKSEL_6_MHZ         2

#define DWC2_HCFG_FSLSPCLKSEL_MASK          (0x3 << 0)

#define DWC2_HCFG_FSLSPCLKSEL_OFFSET            0

#define DWC2_HCFG_FSLSSUPP              (1 << 2)

#define DWC2_HCFG_FSLSSUPP_OFFSET           2

#define DWC2_HCFG_DESCDMA               (1 << 23)

#define DWC2_HCFG_DESCDMA_OFFSET            23

#define DWC2_HCFG_FRLISTEN_MASK             (0x3 << 24)

#define DWC2_HCFG_FRLISTEN_OFFSET           24

#define DWC2_HCFG_PERSCHEDENA               (1 << 26)

#define DWC2_HCFG_PERSCHEDENA_OFFSET            26

#define DWC2_HCFG_PERSCHEDSTAT              (1 << 27)

#define DWC2_HCFG_PERSCHEDSTAT_OFFSET           27

#define DWC2_HFIR_FRINT_MASK                (0xFFFF << 0)

#define DWC2_HFIR_FRINT_OFFSET              0

#define DWC2_HFNUM_FRNUM_MASK               (0xFFFF << 0)

#define DWC2_HFNUM_FRNUM_OFFSET             0

#define DWC2_HFNUM_FRREM_MASK               (0xFFFF << 16)

#define DWC2_HFNUM_FRREM_OFFSET             16

#define DWC2_HFNUM_MAX_FRNUM                0x3FFF

#define DWC2_HPTXSTS_PTXFSPCAVAIL_MASK          (0xFFFF << 0)

#define DWC2_HPTXSTS_PTXFSPCAVAIL_OFFSET        0

#define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK          (0xFF << 16)

#define DWC2_HPTXSTS_PTXQSPCAVAIL_OFFSET        16

#define DWC2_HPTXSTS_PTXQTOP_TERMINATE          (1 << 24)

#define DWC2_HPTXSTS_PTXQTOP_TERMINATE_OFFSET       24

#define DWC2_HPTXSTS_PTXQTOP_TOKEN_MASK         (0x3 << 25)

#define DWC2_HPTXSTS_PTXQTOP_TOKEN_OFFSET       25

#define DWC2_HPTXSTS_PTXQTOP_CHNUM_MASK         (0xF << 27)

#define DWC2_HPTXSTS_PTXQTOP_CHNUM_OFFSET       27

#define DWC2_HPTXSTS_PTXQTOP_ODD            (1 << 31)

#define DWC2_HPTXSTS_PTXQTOP_ODD_OFFSET         31

#define DWC2_HPRT0_PRTCONNSTS               (1 << 0)

#define DWC2_HPRT0_PRTCONNSTS_OFFSET            0

#define DWC2_HPRT0_PRTCONNDET               (1 << 1)

#define DWC2_HPRT0_PRTCONNDET_OFFSET            1

#define DWC2_HPRT0_PRTENA               (1 << 2)

#define DWC2_HPRT0_PRTENA_OFFSET            2

#define DWC2_HPRT0_PRTENCHNG                (1 << 3)

#define DWC2_HPRT0_PRTENCHNG_OFFSET         3

#define DWC2_HPRT0_PRTOVRCURRACT            (1 << 4)

#define DWC2_HPRT0_PRTOVRCURRACT_OFFSET         4

#define DWC2_HPRT0_PRTOVRCURRCHNG           (1 << 5)

#define DWC2_HPRT0_PRTOVRCURRCHNG_OFFSET        5

#define DWC2_HPRT0_PRTRES               (1 << 6)

#define DWC2_HPRT0_PRTRES_OFFSET            6

#define DWC2_HPRT0_PRTSUSP              (1 << 7)

#define DWC2_HPRT0_PRTSUSP_OFFSET           7

#define DWC2_HPRT0_PRTRST               (1 << 8)

#define DWC2_HPRT0_PRTRST_OFFSET            8

#define DWC2_HPRT0_PRTLNSTS_MASK            (0x3 << 10)

#define DWC2_HPRT0_PRTLNSTS_OFFSET          10

#define DWC2_HPRT0_PRTPWR               (1 << 12)

#define DWC2_HPRT0_PRTPWR_OFFSET            12

#define DWC2_HPRT0_PRTTSTCTL_MASK           (0xF << 13)

#define DWC2_HPRT0_PRTTSTCTL_OFFSET         13

#define DWC2_HPRT0_PRTSPD_HIGH              (0 << 17)

#define DWC2_HPRT0_PRTSPD_FULL              (1 << 17)

#define DWC2_HPRT0_PRTSPD_LOW               (2 << 17)

#define DWC2_HPRT0_PRTSPD_MASK              (0x3 << 17)

#define DWC2_HPRT0_PRTSPD_OFFSET            17


#define DWC2_HPRT0_W1C_MASK             (DWC2_HPRT0_PRTCONNDET | \

                            DWC2_HPRT0_PRTENA | \

                            DWC2_HPRT0_PRTENCHNG | \

                            DWC2_HPRT0_PRTOVRCURRCHNG)


#define DWC2_HAINT_CH0                  (1 << 0)

#define DWC2_HAINT_CH0_OFFSET               0

#define DWC2_HAINT_CH1                  (1 << 1)

#define DWC2_HAINT_CH1_OFFSET               1

#define DWC2_HAINT_CH2                  (1 << 2)

#define DWC2_HAINT_CH2_OFFSET               2

#define DWC2_HAINT_CH3                  (1 << 3)

#define DWC2_HAINT_CH3_OFFSET               3

#define DWC2_HAINT_CH4                  (1 << 4)

#define DWC2_HAINT_CH4_OFFSET               4

#define DWC2_HAINT_CH5                  (1 << 5)

#define DWC2_HAINT_CH5_OFFSET               5

#define DWC2_HAINT_CH6                  (1 << 6)

#define DWC2_HAINT_CH6_OFFSET               6

#define DWC2_HAINT_CH7                  (1 << 7)

#define DWC2_HAINT_CH7_OFFSET               7

#define DWC2_HAINT_CH8                  (1 << 8)

#define DWC2_HAINT_CH8_OFFSET               8

#define DWC2_HAINT_CH9                  (1 << 9)

#define DWC2_HAINT_CH9_OFFSET               9

#define DWC2_HAINT_CH10                 (1 << 10)

#define DWC2_HAINT_CH10_OFFSET              10

#define DWC2_HAINT_CH11                 (1 << 11)

#define DWC2_HAINT_CH11_OFFSET              11

#define DWC2_HAINT_CH12                 (1 << 12)

#define DWC2_HAINT_CH12_OFFSET              12

#define DWC2_HAINT_CH13                 (1 << 13)

#define DWC2_HAINT_CH13_OFFSET              13

#define DWC2_HAINT_CH14                 (1 << 14)

#define DWC2_HAINT_CH14_OFFSET              14

#define DWC2_HAINT_CH15                 (1 << 15)

#define DWC2_HAINT_CH15_OFFSET              15

#define DWC2_HAINT_CHINT_MASK               0xffff

#define DWC2_HAINT_CHINT_OFFSET             0

#define DWC2_HAINTMSK_CH0               (1 << 0)

#define DWC2_HAINTMSK_CH0_OFFSET            0

#define DWC2_HAINTMSK_CH1               (1 << 1)

#define DWC2_HAINTMSK_CH1_OFFSET            1

#define DWC2_HAINTMSK_CH2               (1 << 2)

#define DWC2_HAINTMSK_CH2_OFFSET            2

#define DWC2_HAINTMSK_CH3               (1 << 3)

#define DWC2_HAINTMSK_CH3_OFFSET            3

#define DWC2_HAINTMSK_CH4               (1 << 4)

#define DWC2_HAINTMSK_CH4_OFFSET            4

#define DWC2_HAINTMSK_CH5               (1 << 5)

#define DWC2_HAINTMSK_CH5_OFFSET            5

#define DWC2_HAINTMSK_CH6               (1 << 6)

#define DWC2_HAINTMSK_CH6_OFFSET            6

#define DWC2_HAINTMSK_CH7               (1 << 7)

#define DWC2_HAINTMSK_CH7_OFFSET            7

#define DWC2_HAINTMSK_CH8               (1 << 8)

#define DWC2_HAINTMSK_CH8_OFFSET            8

#define DWC2_HAINTMSK_CH9               (1 << 9)

#define DWC2_HAINTMSK_CH9_OFFSET            9

#define DWC2_HAINTMSK_CH10              (1 << 10)

#define DWC2_HAINTMSK_CH10_OFFSET           10

#define DWC2_HAINTMSK_CH11              (1 << 11)

#define DWC2_HAINTMSK_CH11_OFFSET           11

#define DWC2_HAINTMSK_CH12              (1 << 12)

#define DWC2_HAINTMSK_CH12_OFFSET           12

#define DWC2_HAINTMSK_CH13              (1 << 13)

#define DWC2_HAINTMSK_CH13_OFFSET           13

#define DWC2_HAINTMSK_CH14              (1 << 14)

#define DWC2_HAINTMSK_CH14_OFFSET           14

#define DWC2_HAINTMSK_CH15              (1 << 15)

#define DWC2_HAINTMSK_CH15_OFFSET           15

#define DWC2_HAINTMSK_CHINT_MASK            0xffff

#define DWC2_HAINTMSK_CHINT_OFFSET          0

#define DWC2_HCCHAR_MPS_MASK                (0x7FF << 0)

#define DWC2_HCCHAR_MPS_OFFSET              0

#define DWC2_HCCHAR_EPNUM_MASK              (0xF << 11)

#define DWC2_HCCHAR_EPNUM_OFFSET            11

#define DWC2_HCCHAR_EPDIR               (1 << 15)

#define DWC2_HCCHAR_EPDIR_OFFSET            15

#define DWC2_HCCHAR_LSPDDEV             (1 << 17)

#define DWC2_HCCHAR_LSPDDEV_OFFSET          17

#define DWC2_HCCHAR_EPTYPE_CONTROL          0

#define DWC2_HCCHAR_EPTYPE_ISOC             1

#define DWC2_HCCHAR_EPTYPE_BULK             2

#define DWC2_HCCHAR_EPTYPE_INTR             3

#define DWC2_HCCHAR_EPTYPE_MASK             (0x3 << 18)

#define DWC2_HCCHAR_EPTYPE_OFFSET           18

#define DWC2_HCCHAR_MULTICNT_MASK           (0x3 << 20)

#define DWC2_HCCHAR_MULTICNT_OFFSET         20

#define DWC2_HCCHAR_DEVADDR_MASK            (0x7F << 22)

#define DWC2_HCCHAR_DEVADDR_OFFSET          22

#define DWC2_HCCHAR_ODDFRM              (1 << 29)

#define DWC2_HCCHAR_ODDFRM_OFFSET           29

#define DWC2_HCCHAR_CHDIS               (1 << 30)

#define DWC2_HCCHAR_CHDIS_OFFSET            30

#define DWC2_HCCHAR_CHEN                (1 << 31)

#define DWC2_HCCHAR_CHEN_OFFSET             31

#define DWC2_HCSPLT_PRTADDR_MASK            (0x7F << 0)

#define DWC2_HCSPLT_PRTADDR_OFFSET          0

#define DWC2_HCSPLT_HUBADDR_MASK            (0x7F << 7)

#define DWC2_HCSPLT_HUBADDR_OFFSET          7

#define DWC2_HCSPLT_XACTPOS_MASK            (0x3 << 14)

#define DWC2_HCSPLT_XACTPOS_OFFSET          14

#define DWC2_HCSPLT_COMPSPLT                (1 << 16)

#define DWC2_HCSPLT_COMPSPLT_OFFSET         16

#define DWC2_HCSPLT_SPLTENA             (1 << 31)

#define DWC2_HCSPLT_SPLTENA_OFFSET          31

#define DWC2_HCINT_XFERCOMP             (1 << 0)

#define DWC2_HCINT_XFERCOMP_OFFSET          0

#define DWC2_HCINT_CHHLTD               (1 << 1)

#define DWC2_HCINT_CHHLTD_OFFSET            1

#define DWC2_HCINT_AHBERR               (1 << 2)

#define DWC2_HCINT_AHBERR_OFFSET            2

#define DWC2_HCINT_STALL                (1 << 3)

#define DWC2_HCINT_STALL_OFFSET             3

#define DWC2_HCINT_NAK                  (1 << 4)

#define DWC2_HCINT_NAK_OFFSET               4

#define DWC2_HCINT_ACK                  (1 << 5)

#define DWC2_HCINT_ACK_OFFSET               5

#define DWC2_HCINT_NYET                 (1 << 6)

#define DWC2_HCINT_NYET_OFFSET              6

#define DWC2_HCINT_XACTERR              (1 << 7)

#define DWC2_HCINT_XACTERR_OFFSET           7

#define DWC2_HCINT_BBLERR               (1 << 8)

#define DWC2_HCINT_BBLERR_OFFSET            8

#define DWC2_HCINT_FRMOVRUN             (1 << 9)

#define DWC2_HCINT_FRMOVRUN_OFFSET          9

#define DWC2_HCINT_DATATGLERR               (1 << 10)

#define DWC2_HCINT_DATATGLERR_OFFSET            10

#define DWC2_HCINT_BNA                  (1 << 11)

#define DWC2_HCINT_BNA_OFFSET               11

#define DWC2_HCINT_XCS_XACT             (1 << 12)

#define DWC2_HCINT_XCS_XACT_OFFSET          12

#define DWC2_HCINT_FRM_LIST_ROLL            (1 << 13)

#define DWC2_HCINT_FRM_LIST_ROLL_OFFSET         13

#define DWC2_HCINTMSK_XFERCOMPL             (1 << 0)

#define DWC2_HCINTMSK_XFERCOMPL_OFFSET          0

#define DWC2_HCINTMSK_CHHLTD                (1 << 1)

#define DWC2_HCINTMSK_CHHLTD_OFFSET         1

#define DWC2_HCINTMSK_AHBERR                (1 << 2)

#define DWC2_HCINTMSK_AHBERR_OFFSET         2

#define DWC2_HCINTMSK_STALL             (1 << 3)

#define DWC2_HCINTMSK_STALL_OFFSET          3

#define DWC2_HCINTMSK_NAK               (1 << 4)

#define DWC2_HCINTMSK_NAK_OFFSET            4

#define DWC2_HCINTMSK_ACK               (1 << 5)

#define DWC2_HCINTMSK_ACK_OFFSET            5

#define DWC2_HCINTMSK_NYET              (1 << 6)

#define DWC2_HCINTMSK_NYET_OFFSET           6

#define DWC2_HCINTMSK_XACTERR               (1 << 7)

#define DWC2_HCINTMSK_XACTERR_OFFSET            7

#define DWC2_HCINTMSK_BBLERR                (1 << 8)

#define DWC2_HCINTMSK_BBLERR_OFFSET         8

#define DWC2_HCINTMSK_FRMOVRUN              (1 << 9)

#define DWC2_HCINTMSK_FRMOVRUN_OFFSET           9

#define DWC2_HCINTMSK_DATATGLERR            (1 << 10)

#define DWC2_HCINTMSK_DATATGLERR_OFFSET         10

#define DWC2_HCINTMSK_BNA               (1 << 11)

#define DWC2_HCINTMSK_BNA_OFFSET            11

#define DWC2_HCINTMSK_XCS_XACT              (1 << 12)

#define DWC2_HCINTMSK_XCS_XACT_OFFSET           12

#define DWC2_HCINTMSK_FRM_LIST_ROLL         (1 << 13)

#define DWC2_HCINTMSK_FRM_LIST_ROLL_OFFSET      13

#define DWC2_HCTSIZ_XFERSIZE_MASK           0x7ffff

#define DWC2_HCTSIZ_XFERSIZE_OFFSET         0

#define DWC2_HCTSIZ_SCHINFO_MASK            0xff

#define DWC2_HCTSIZ_SCHINFO_OFFSET          0

#define DWC2_HCTSIZ_NTD_MASK                (0xff << 8)

#define DWC2_HCTSIZ_NTD_OFFSET              8

#define DWC2_HCTSIZ_PKTCNT_MASK             (0x3ff << 19)

#define DWC2_HCTSIZ_PKTCNT_OFFSET           19

#define DWC2_HCTSIZ_PID_MASK                (0x3 << 29)

#define DWC2_HCTSIZ_PID_OFFSET              29

#define DWC2_HCTSIZ_DOPNG               (1 << 31)

#define DWC2_HCTSIZ_DOPNG_OFFSET            31

#define DWC2_HCDMA_CTD_MASK             (0xFF << 3)

#define DWC2_HCDMA_CTD_OFFSET               3

#define DWC2_HCDMA_DMA_ADDR_MASK            (0x1FFFFF << 11)

#define DWC2_HCDMA_DMA_ADDR_OFFSET          11

#define DWC2_PCGCCTL_STOPPCLK               (1 << 0)

#define DWC2_PCGCCTL_STOPPCLK_OFFSET            0

#define DWC2_PCGCCTL_GATEHCLK               (1 << 1)

#define DWC2_PCGCCTL_GATEHCLK_OFFSET            1

#define DWC2_PCGCCTL_PWRCLMP                (1 << 2)

#define DWC2_PCGCCTL_PWRCLMP_OFFSET         2

#define DWC2_PCGCCTL_RSTPDWNMODULE          (1 << 3)

#define DWC2_PCGCCTL_RSTPDWNMODULE_OFFSET       3

#define DWC2_PCGCCTL_PHYSUSPENDED           (1 << 4)

#define DWC2_PCGCCTL_PHYSUSPENDED_OFFSET        4

#define DWC2_PCGCCTL_ENBL_SLEEP_GATING          (1 << 5)

#define DWC2_PCGCCTL_ENBL_SLEEP_GATING_OFFSET       5

#define DWC2_PCGCCTL_PHY_IN_SLEEP           (1 << 6)

#define DWC2_PCGCCTL_PHY_IN_SLEEP_OFFSET        6

#define DWC2_PCGCCTL_DEEP_SLEEP             (1 << 7)

#define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET          7

#define DWC2_SNPSID_DEVID_VER_2xx           (0x4f542 << 12)

#define DWC2_SNPSID_DEVID_VER_3xx           (0x4f543 << 12)

#define DWC2_SNPSID_DEVID_MASK              (0xfffff << 12)

#define DWC2_SNPSID_DEVID_OFFSET            12


#endif

uint32_t
unsigned int uint32_t
Definition acefiex.h:163

dwc2_core_regs
Definition dwc2_reg.h:59

dwc2_core_regs::gintmsk
uint32_t gintmsk
Definition dwc2_reg.h:66

dwc2_core_regs::grxfsiz
uint32_t grxfsiz
Definition dwc2_reg.h:69

dwc2_core_regs::ggpio
uint32_t ggpio
Definition dwc2_reg.h:74

dwc2_core_regs::gotgint
uint32_t gotgint
Definition dwc2_reg.h:61

dwc2_core_regs::hptxfsiz
uint32_t hptxfsiz
Definition dwc2_reg.h:83

dwc2_core_regs::dptxfsiz_dieptxf
uint32_t dptxfsiz_dieptxf[15]
Definition dwc2_reg.h:84

dwc2_core_regs::pcgcctl
uint32_t pcgcctl
Definition dwc2_reg.h:92

dwc2_core_regs::ghwcfg2
uint32_t ghwcfg2
Definition dwc2_reg.h:78

dwc2_core_regs::gintsts
uint32_t gintsts
Definition dwc2_reg.h:65

dwc2_core_regs::host_regs
struct dwc2_host_regs host_regs
Definition dwc2_reg.h:86

dwc2_core_regs::guid
uint32_t guid
Definition dwc2_reg.h:75

dwc2_core_regs::ghwcfg4
uint32_t ghwcfg4
Definition dwc2_reg.h:80

dwc2_core_regs::grstctl
uint32_t grstctl
Definition dwc2_reg.h:64

dwc2_core_regs::hc_regs
struct dwc2_hc_regs hc_regs[16]
Definition dwc2_reg.h:90

dwc2_core_regs::gnptxfsiz
uint32_t gnptxfsiz
Definition dwc2_reg.h:70

dwc2_core_regs::_pad_0x700_0xe00
uint32_t _pad_0x700_0xe00[448]
Definition dwc2_reg.h:91

dwc2_core_regs::gnptxsts
uint32_t gnptxsts
Definition dwc2_reg.h:71

dwc2_core_regs::_pad_0x420_0x43c
uint32_t _pad_0x420_0x43c[8]
Definition dwc2_reg.h:87

dwc2_core_regs::ghwcfg1
uint32_t ghwcfg1
Definition dwc2_reg.h:77

dwc2_core_regs::gi2cctl
uint32_t gi2cctl
Definition dwc2_reg.h:72

dwc2_core_regs::_pad_0x140_0x3fc
uint32_t _pad_0x140_0x3fc[176]
Definition dwc2_reg.h:85

dwc2_core_regs::gahbcfg
uint32_t gahbcfg
Definition dwc2_reg.h:62

dwc2_core_regs::gotgctl
uint32_t gotgctl
Definition dwc2_reg.h:60

dwc2_core_regs::grxstsp
uint32_t grxstsp
Definition dwc2_reg.h:68

dwc2_core_regs::gpvndctl
uint32_t gpvndctl
Definition dwc2_reg.h:73

dwc2_core_regs::_pad_0x444_0x4fc
uint32_t _pad_0x444_0x4fc[47]
Definition dwc2_reg.h:89

dwc2_core_regs::_pad_0x58_0x9c
uint32_t _pad_0x58_0x9c[42]
Definition dwc2_reg.h:82

dwc2_core_regs::gsnpsid
uint32_t gsnpsid
Definition dwc2_reg.h:76

dwc2_core_regs::grxstsr
uint32_t grxstsr
Definition dwc2_reg.h:67

dwc2_core_regs::gusbcfg
uint32_t gusbcfg
Definition dwc2_reg.h:63

dwc2_core_regs::glpmcfg
uint32_t glpmcfg
Definition dwc2_reg.h:81

dwc2_core_regs::hprt0
uint32_t hprt0
Definition dwc2_reg.h:88

dwc2_core_regs::ghwcfg3
uint32_t ghwcfg3
Definition dwc2_reg.h:79

dwc2_hc_regs
Definition dwc2_reg.h:37

dwc2_hc_regs::hctsiz
uint32_t hctsiz
Definition dwc2_reg.h:42

dwc2_hc_regs::hcint
uint32_t hcint
Definition dwc2_reg.h:40

dwc2_hc_regs::hcdma
uint32_t hcdma
Definition dwc2_reg.h:43

dwc2_hc_regs::hcintmsk
uint32_t hcintmsk
Definition dwc2_reg.h:41

dwc2_hc_regs::hcchar
uint32_t hcchar
Definition dwc2_reg.h:38

dwc2_hc_regs::hcsplt
uint32_t hcsplt
Definition dwc2_reg.h:39

dwc2_hc_regs::hcdmab
uint32_t hcdmab
Definition dwc2_reg.h:45

dwc2_hc_regs::reserved
uint32_t reserved
Definition dwc2_reg.h:44

dwc2_host_regs
Definition dwc2_reg.h:48

dwc2_host_regs::hdnum
uint32_t hdnum
Definition dwc2_reg.h:51

dwc2_host_regs::hptxsts
uint32_t hptxsts
Definition dwc2_reg.h:53

dwc2_host_regs::hflbaddr
uint32_t hflbaddr
Definition dwc2_reg.h:56

dwc2_host_regs::_pad_0x40c
uint32_t _pad_0x40c
Definition dwc2_reg.h:52

dwc2_host_regs::haintmsk
uint32_t haintmsk
Definition dwc2_reg.h:55

dwc2_host_regs::hfir
uint32_t hfir
Definition dwc2_reg.h:50

dwc2_host_regs::hcfg
uint32_t hcfg
Definition dwc2_reg.h:49

dwc2_host_regs::haint
uint32_t haint
Definition dwc2_reg.h:54

dwc2_hcsplit_t
Definition dwc2_reg.h:95

dwc2_hcsplit_t::spltena
uint32_t spltena
Definition dwc2_reg.h:102

dwc2_hcsplit_t::compsplt
uint32_t compsplt
Definition dwc2_reg.h:100

dwc2_hcsplit_t::xactpos
uint32_t xactpos
Definition dwc2_reg.h:99

dwc2_hcsplit_t::hubaddr
uint32_t hubaddr
Definition dwc2_reg.h:98

dwc2_hcsplit_t::val
uint32_t val
Definition dwc2_reg.h:104

dwc2_hcsplit_t::reserved
uint32_t reserved
Definition dwc2_reg.h:101

dwc2_hcsplit_t::prtaddr
uint32_t prtaddr
Definition dwc2_reg.h:97