#include "drm.h"

Include dependency graph for etnaviv_drm.h:

Classes
struct	drm_etnaviv_timespec

struct	drm_etnaviv_param

struct	drm_etnaviv_gem_new

struct	drm_etnaviv_gem_info

struct	drm_etnaviv_gem_cpu_prep

struct	drm_etnaviv_gem_cpu_fini

struct	drm_etnaviv_gem_submit_reloc

struct	drm_etnaviv_gem_submit_bo

struct	drm_etnaviv_gem_submit_pmr

struct	drm_etnaviv_gem_submit

struct	drm_etnaviv_wait_fence

struct	drm_etnaviv_gem_userptr

struct	drm_etnaviv_gem_wait

struct	drm_etnaviv_pm_domain

struct	drm_etnaviv_pm_signal

Macros
#define	ETNAVIV_PARAM_GPU_MODEL 0x01

#define	ETNAVIV_PARAM_GPU_REVISION 0x02

#define	ETNAVIV_PARAM_GPU_FEATURES_0 0x03

#define	ETNAVIV_PARAM_GPU_FEATURES_1 0x04

#define	ETNAVIV_PARAM_GPU_FEATURES_2 0x05

#define	ETNAVIV_PARAM_GPU_FEATURES_3 0x06

#define	ETNAVIV_PARAM_GPU_FEATURES_4 0x07

#define	ETNAVIV_PARAM_GPU_FEATURES_5 0x08

#define	ETNAVIV_PARAM_GPU_FEATURES_6 0x09

#define	ETNAVIV_PARAM_GPU_FEATURES_7 0x0a

#define	ETNAVIV_PARAM_GPU_FEATURES_8 0x0b

#define	ETNAVIV_PARAM_GPU_FEATURES_9 0x0c

#define	ETNAVIV_PARAM_GPU_FEATURES_10 0x0d

#define	ETNAVIV_PARAM_GPU_FEATURES_11 0x0e

#define	ETNAVIV_PARAM_GPU_FEATURES_12 0x0f

#define	ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10

#define	ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11

#define	ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12

#define	ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13

#define	ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14

#define	ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15

#define	ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16

#define	ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17

#define	ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18

#define	ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19

#define	ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a

#define	ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b

#define	ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c

#define	ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d

#define	ETNAVIV_PARAM_GPU_ECO_ID 0x1e

#define	ETNA_MAX_PIPES 4

#define	ETNA_BO_CACHE_MASK 0x000f0000

#define	ETNA_BO_CACHED 0x00010000

#define	ETNA_BO_WC 0x00020000

#define	ETNA_BO_UNCACHED 0x00040000

#define	ETNA_BO_FORCE_MMU 0x00100000

#define	ETNA_PREP_READ 0x01

#define	ETNA_PREP_WRITE 0x02

#define	ETNA_PREP_NOSYNC 0x04

#define	ETNA_SUBMIT_BO_READ 0x0001

#define	ETNA_SUBMIT_BO_WRITE 0x0002

#define	ETNA_PM_PROCESS_PRE 0x0001

#define	ETNA_PM_PROCESS_POST 0x0002

#define	ETNA_SUBMIT_NO_IMPLICIT 0x0001

#define	ETNA_SUBMIT_FENCE_FD_IN 0x0002

#define	ETNA_SUBMIT_FENCE_FD_OUT 0x0004

#define	ETNA_SUBMIT_SOFTPIN 0x0008

#define	ETNA_SUBMIT_FLAGS

#define	ETNA_PIPE_3D 0x00

#define	ETNA_PIPE_2D 0x01

#define	ETNA_PIPE_VG 0x02

#define	ETNA_WAIT_NONBLOCK 0x01

#define	ETNA_USERPTR_READ 0x01

#define	ETNA_USERPTR_WRITE 0x02

#define	DRM_ETNAVIV_GET_PARAM 0x00

#define	DRM_ETNAVIV_GEM_NEW 0x02

#define	DRM_ETNAVIV_GEM_INFO 0x03

#define	DRM_ETNAVIV_GEM_CPU_PREP 0x04

#define	DRM_ETNAVIV_GEM_CPU_FINI 0x05

#define	DRM_ETNAVIV_GEM_SUBMIT 0x06

#define	DRM_ETNAVIV_WAIT_FENCE 0x07

#define	DRM_ETNAVIV_GEM_USERPTR 0x08

#define	DRM_ETNAVIV_GEM_WAIT 0x09

#define	DRM_ETNAVIV_PM_QUERY_DOM 0x0a

#define	DRM_ETNAVIV_PM_QUERY_SIG 0x0b

#define	DRM_ETNAVIV_NUM_IOCTLS 0x0c

#define	DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)

#define	DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)

#define	DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)

#define	DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)

#define	DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)

#define	DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)

#define	DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)

#define	DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)

#define	DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)

#define	DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)

#define	DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)

Macro Definition Documentation

◆ DRM_ETNAVIV_GEM_CPU_FINI

#define DRM_ETNAVIV_GEM_CPU_FINI 0x05

◆ DRM_ETNAVIV_GEM_CPU_PREP

#define DRM_ETNAVIV_GEM_CPU_PREP 0x04

◆ DRM_ETNAVIV_GEM_INFO

#define DRM_ETNAVIV_GEM_INFO 0x03

◆ DRM_ETNAVIV_GEM_NEW

#define DRM_ETNAVIV_GEM_NEW 0x02

◆ DRM_ETNAVIV_GEM_SUBMIT

#define DRM_ETNAVIV_GEM_SUBMIT 0x06

◆ DRM_ETNAVIV_GEM_USERPTR

#define DRM_ETNAVIV_GEM_USERPTR 0x08

◆ DRM_ETNAVIV_GEM_WAIT

#define DRM_ETNAVIV_GEM_WAIT 0x09

◆ DRM_ETNAVIV_GET_PARAM

#define DRM_ETNAVIV_GET_PARAM 0x00

◆ DRM_ETNAVIV_NUM_IOCTLS

#define DRM_ETNAVIV_NUM_IOCTLS 0x0c

◆ DRM_ETNAVIV_PM_QUERY_DOM

#define DRM_ETNAVIV_PM_QUERY_DOM 0x0a

◆ DRM_ETNAVIV_PM_QUERY_SIG

#define DRM_ETNAVIV_PM_QUERY_SIG 0x0b

◆ DRM_ETNAVIV_WAIT_FENCE

#define DRM_ETNAVIV_WAIT_FENCE 0x07

◆ DRM_IOCTL_ETNAVIV_GEM_CPU_FINI

#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)

◆ DRM_IOCTL_ETNAVIV_GEM_CPU_PREP

#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)

◆ DRM_IOCTL_ETNAVIV_GEM_INFO

#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)

◆ DRM_IOCTL_ETNAVIV_GEM_NEW

#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)

◆ DRM_IOCTL_ETNAVIV_GEM_SUBMIT

#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)

◆ DRM_IOCTL_ETNAVIV_GEM_USERPTR

#define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)

◆ DRM_IOCTL_ETNAVIV_GEM_WAIT

#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)

◆ DRM_IOCTL_ETNAVIV_GET_PARAM

#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)

◆ DRM_IOCTL_ETNAVIV_PM_QUERY_DOM

#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)

◆ DRM_IOCTL_ETNAVIV_PM_QUERY_SIG

#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)

◆ DRM_IOCTL_ETNAVIV_WAIT_FENCE

#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)

◆ ETNA_BO_CACHE_MASK

#define ETNA_BO_CACHE_MASK 0x000f0000

◆ ETNA_BO_CACHED

#define ETNA_BO_CACHED 0x00010000

◆ ETNA_BO_FORCE_MMU

#define ETNA_BO_FORCE_MMU 0x00100000

◆ ETNA_BO_UNCACHED

#define ETNA_BO_UNCACHED 0x00040000

◆ ETNA_BO_WC

#define ETNA_BO_WC 0x00020000

◆ ETNA_MAX_PIPES

#define ETNA_MAX_PIPES 4

◆ ETNA_PIPE_2D

#define ETNA_PIPE_2D 0x01

◆ ETNA_PIPE_3D

#define ETNA_PIPE_3D 0x00

◆ ETNA_PIPE_VG

#define ETNA_PIPE_VG 0x02

◆ ETNA_PM_PROCESS_POST

#define ETNA_PM_PROCESS_POST 0x0002

◆ ETNA_PM_PROCESS_PRE

#define ETNA_PM_PROCESS_PRE 0x0001

◆ ETNA_PREP_NOSYNC

#define ETNA_PREP_NOSYNC 0x04

◆ ETNA_PREP_READ

#define ETNA_PREP_READ 0x01

◆ ETNA_PREP_WRITE

#define ETNA_PREP_WRITE 0x02

◆ ETNA_SUBMIT_BO_READ

#define ETNA_SUBMIT_BO_READ 0x0001

◆ ETNA_SUBMIT_BO_WRITE

#define ETNA_SUBMIT_BO_WRITE 0x0002

◆ ETNA_SUBMIT_FENCE_FD_IN

#define ETNA_SUBMIT_FENCE_FD_IN 0x0002

◆ ETNA_SUBMIT_FENCE_FD_OUT

#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004

◆ ETNA_SUBMIT_FLAGS

#define ETNA_SUBMIT_FLAGS

Value:

                     (ETNA_SUBMIT_NO_IMPLICIT | \
                     ETNA_SUBMIT_FENCE_FD_IN | \
                     ETNA_SUBMIT_FENCE_FD_OUT| \
                     ETNA_SUBMIT_SOFTPIN)

◆ ETNA_SUBMIT_NO_IMPLICIT

#define ETNA_SUBMIT_NO_IMPLICIT 0x0001

◆ ETNA_SUBMIT_SOFTPIN

#define ETNA_SUBMIT_SOFTPIN 0x0008

◆ ETNA_USERPTR_READ

#define ETNA_USERPTR_READ 0x01

◆ ETNA_USERPTR_WRITE

#define ETNA_USERPTR_WRITE 0x02

◆ ETNA_WAIT_NONBLOCK

#define ETNA_WAIT_NONBLOCK 0x01

◆ ETNAVIV_PARAM_GPU_BUFFER_SIZE

#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17

◆ ETNAVIV_PARAM_GPU_CUSTOMER_ID

#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d

◆ ETNAVIV_PARAM_GPU_ECO_ID

#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e

◆ ETNAVIV_PARAM_GPU_FEATURES_0

#define ETNAVIV_PARAM_GPU_FEATURES_0 0x03

◆ ETNAVIV_PARAM_GPU_FEATURES_1

#define ETNAVIV_PARAM_GPU_FEATURES_1 0x04

◆ ETNAVIV_PARAM_GPU_FEATURES_10

#define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d

◆ ETNAVIV_PARAM_GPU_FEATURES_11

#define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e

◆ ETNAVIV_PARAM_GPU_FEATURES_12

#define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f

◆ ETNAVIV_PARAM_GPU_FEATURES_2

#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05

◆ ETNAVIV_PARAM_GPU_FEATURES_3

#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06

◆ ETNAVIV_PARAM_GPU_FEATURES_4

#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07

◆ ETNAVIV_PARAM_GPU_FEATURES_5

#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08

◆ ETNAVIV_PARAM_GPU_FEATURES_6

#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09

◆ ETNAVIV_PARAM_GPU_FEATURES_7

#define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a

◆ ETNAVIV_PARAM_GPU_FEATURES_8

#define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b

◆ ETNAVIV_PARAM_GPU_FEATURES_9

#define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c

◆ ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT

#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18

◆ ETNAVIV_PARAM_GPU_MODEL

#define ETNAVIV_PARAM_GPU_MODEL 0x01

◆ ETNAVIV_PARAM_GPU_NUM_CONSTANTS

#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19

◆ ETNAVIV_PARAM_GPU_NUM_VARYINGS

#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a

◆ ETNAVIV_PARAM_GPU_PIXEL_PIPES

#define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15

◆ ETNAVIV_PARAM_GPU_PRODUCT_ID

#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c

◆ ETNAVIV_PARAM_GPU_REGISTER_MAX

#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11

◆ ETNAVIV_PARAM_GPU_REVISION

#define ETNAVIV_PARAM_GPU_REVISION 0x02

◆ ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT

#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14

◆ ETNAVIV_PARAM_GPU_STREAM_COUNT

#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10

◆ ETNAVIV_PARAM_GPU_THREAD_COUNT

#define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12

◆ ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE

#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13

◆ ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE

#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16

◆ ETNAVIV_PARAM_SOFTPIN_START_ADDR

#define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b

Classes

Macros