ihda.h File Reference

#include <stdint.h>
#include <Hal\serial.h>
#include "widget.h"

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Classes
struct	_bdl_
struct	_hd_audio_

Macros
#define	GCAP   0x00
	Device Registers.
#define	VMIN   0x02
#define	VMAJ   0x03
#define	OUTPAY   0x04
#define	INPAY   0x06
#define	GCTL   0x08
#define	WAKEEN   0x0C
#define	STATESTS   0x0E
#define	GSTS   0x10
#define	OUTSTRMPAY   0x18
#define	INSTRMPAY   0x1A
#define	INTCTL   0x20
#define	INTSTS   0x24
#define	WALCLK   0x30
#define	SSYNC   0x38
#define	CORBLBASE   0x40
#define	CORBUBASE   0x44
#define	CORBWP   0x48
#define	CORBRP   0x4A
#define	CORBCTL   0x4C
#define	CORBSTS   0x4D
#define	CORBSIZE   0x4E
#define	RIRBLBASE   0x50
#define	RIRBUBASE   0x54
#define	RIRBWP   0x58
#define	RINTCNT   0x5A
#define	RIRBCTL   0x5C
#define	RIRBSTS   0x5D
#define	RIRBSIZE   0x5E
#define	ICOI   0x60
#define	ICII   0x64
#define	ICIS   0x68
#define	DPIBLBASE   0x70
#define	DPIBUBASE   0x74
#define	SD0CTL   0x80
#define	SD0STS   0x83
#define	SD0LPIB   0x84
#define	SD0CBL   0x88
#define	SD0LVI   0x8C
#define	SD0FIFOD   0x90
#define	SD0FMT   0x92
#define	SDBDPL   0x98
#define	SDBDPU   0x9C
#define	REG_O0_CTLL   0x100
	Output 0 - Control Lower.
#define	REG_O0_CTLU   0x102
	Output 0 - Control Upper.
#define	REG_O0_STS   0x103
	Output 0 - Status.
#define	REG_O0_CBL   0x108
	Output 0 - Cyclic Buffer Length.
#define	REG_O0_STLVI   0x10c
	Output 0 - Last Valid Index.
#define	REG_O0_FIFOD   0x110
	Output 0 - FIFO Size.
#define	REG_O0_FMT   0x112
	Output 0 - Format.
#define	REG_O0_BDLPL   0x118
	Output 0 - BDL Pointer Lower.
#define	REG_O0_BDLPU   0x11c
	Output 0 - BDL Pointer Upper.
#define	REG_I0_CTLL   0x80
	Input 0 - Control Lower.
#define	REG_I0_STS   0x83
	Input 0 - Status.
#define	REG_I0_LPIB   0x84
	Input 0 - Link position in current buffer.
#define	REG_I0_CBL   0x88
	Input 0 - Cyclic Buffer Length.
#define	REG_I0_LVI   0x8C
	Input 0 - Last Valid Index.
#define	REG_I0_FIFOD   0x90
	Input 0 - FIFO.
#define	REG_I0_FMT   0x92
	Input 0 - Format.
#define	REG_I0_BDPL   0x98
	Input 0 - BDL Pointer Lower.
#define	REG_I0_BDPU   0x9C
	Input 0 - BDL Pointer Upper.
#define	BDL_SIZE   4
#define	BUFFER_SIZE   1024
#define	HDA_GCAP_OSS_MASK   0xf000
#define	HDA_GCAP_OSS_SHIFT   12
#define	HDA_GCAP_ISS_SHIFT   8
#define	HDA_GCAP_ISS_MASK   0x0f00
#define	HDA_GCAP_BSS_SHIFT   3
#define	HDA_GCAP_BSS_MASK   0x00f8
#define	HDA_GCAP_NSD0_SHIFT   1
#define	HDA_GCAP_NSD0_MASK   0x0006
#define	HDA_GCAP_BSS(gcap)   (((gcap) & HDA_GCAP_BSS_MASK) >> HDA_GCAP_BSS_SHIFT)
#define	HDA_GCAP_ISS(gcap)   (((gcap) & HDA_GCAP_ISS_MASK) >> HDA_GCAP_ISS_SHIFT)
#define	HDA_GCAP_OSS(gcap)   (((gcap) & HDA_GCAP_OSS_MASK) >> HDA_GCAP_OSS_SHIFT)
#define	HDA_INTCTL_CIE   0x40000000
#define	HDA_INTCTL_GIE   0x80000000
#define	HDAC_SDCTL_RUN   0x000002
#define	HDAC_SDCTL_IOCE   0x000004
#define	HDAC_SDCTL_FEIE   0x000008
#define	HDAC_SDCTL_DEIE   0x000010
#define	HDAC_SDSTS_DESE   (1<<4)
#define	HDAC_SDSTS_FIFOE   (1<<3)
#define	HDAC_SDSTS_BCIS   (1<<2)

Typedefs
typedef struct _bdl_	HDABDLEntry
typedef struct _hd_audio_	HDAudio

Enumerations
enum	reg_gctl { GCTL_RESET = (1 << 0) }
enum	reg_corbctl { CORBCTL_CORBRUN = (1 << 1) }
enum	reg_rirbctl { RIRBCTL_RIRBRUN = (1 << 1) }
enum	codec_verbs {   VERB_GET_PARAMETER = 0xf0000 , VERB_GET_STREAM_CHANNEL = 0xf0600 , VERB_SET_STREAM_CHANNEL = 0x70600 , VERB_SET_FORMAT = 0x20000 ,   VERB_GET_AMP_GAIN_MUTE = 0xb0000 , VERB_SET_AMP_GAIN_MUTE = 0x30000 , VERB_GET_CONFIG_DEFAULT = 0xf1c00 , VERB_GET_CONN_LIST = 0xf0200 ,   VERB_GET_CONN_SELECT = 0xf0100 , VERB_SET_CONN_SELECT = 0x70100 , VERB_GET_PIN_CONTROL = 0xf0700 , VERB_SET_PIN_CONTROL = 0x70700 ,   VERB_GET_EAPD_BTL = 0xf0c00 , VERB_SET_EAPD_BTL = 0x70c00 , VERB_GET_POWER_STATE = 0xf0500 , VERB_SET_POWER_STATE = 0x70500 ,   VERB_SET_BEEP_GEN = 0x70A00 , VERB_GET_CONV_CHANNEL_COUNT = 0xF2D00 , VERB_SET_CONV_CHANNEL_COUNT = 0x72D00 , VERB_GET_VOLUME_CONTROL = 0xF0F00 ,   VERB_SET_VOLUME_CONTROL = 0x70F00 }
enum	codec_parameters {   PARAM_VENDOR_ID = 0x00 , PARAM_REV_ID = 0x02 , PARAM_NODE_COUNT = 0x04 , PARAM_FN_GROUP_TYPE = 0x05 ,   PARAM_AUDIO_WID_CAP = 0x09 , PARAM_PIN_CAP = 0x0c , PARAM_CONN_LIST_LEN = 0x0e , PARAM_OUT_AMP_CAP = 0x12 }
enum	fn_group_type { FN_GROUP_AUDIO = 0x01 }
enum	widget_type {   WIDGET_OUTPUT = 0x0 , WIDGET_INPUT = 0x1 , WIDGET_MIXER = 0x2 , WIDGET_SELECTOR = 0x3 ,   WIDGET_PIN = 0x4 , WIDGET_POWER = 0x5 , WIDGET_VOLUME_KNOB = 0x6 , WIDGET_BEEP_GEN = 0x7 ,   WIDGET_VENDOR_DEFINED = 0xf }
enum	widget_capabilities { WIDGET_CAP_POWER_CNTRL = (1 << 10) , WIDGET_CAP_TYPE_SHIFT = 20 , WIDGET_CAP_TYPE_MASK = (0xf << 20) }
enum	pin_capabilities { PIN_CAP_OUTPUT = (1 << 4) , PIN_CAP_INPUT = (1 << 5) }
enum	pin_ctl_flags {   PIN_CTL_ENABLE_HPHN = (1 << 7) , PIN_CTL_ENABLE_OUTPUT = (1 << 6) , PIN_CTL_ENABLE_INPUT = (1 << 5) , PIN_CTL_ENABLE_VREFEN = (1 << 2) ,   PIN_CTL_ENABLE_VREF_EN = (1 << 0) , PIN_CTL_ENABLE_VREF_EN2 = (1 << 1) }
enum	sample_format {   SR_48_KHZ = (0 << 14) , SR_44_KHZ = (1 << 14) , BITS_32 = (4 << 4) , BITS_16 = (1 << 4) ,   BITS_24 = (3 << 4) , BITS_8 = (0 << 4) }

Functions
uint8_t	_aud_inb_ (int reg)
void	_aud_outb_ (int reg, uint8_t value)
uint16_t	_aud_inw_ (int reg)
void	_aud_outw_ (int reg, uint16_t value)
uint32_t	_aud_inl_ (int reg)
void	_aud_outl_ (int reg, uint32_t value)
void	HDAudioSetDMAPos (uint64_t dma_buff)
uint64_t	HDAudioGetDMAPos ()
void	HDAudioSetSampleBuffer (uint64_t buffer)
void	CORBWrite (uint32_t verb)
void	RIRBRead (uint64_t *response)
void	HDAAddPath (HDAAudioPath *path)
void	HDASetVolumeFunc (void(*set_vol)(uint8_t volume, int codec))
void	HDASetCodecInitFunc (void(*init_func)(int codec, int nid))
void	HDASetVolume (uint8_t volume)

Macro Definition Documentation

BDL_SIZE

#define BDL_SIZE   4

BUFFER_SIZE

#define BUFFER_SIZE   1024

CORBCTL

#define CORBCTL   0x4C

CORBLBASE

#define CORBLBASE   0x40

CORBRP

#define CORBRP   0x4A

CORBSIZE

#define CORBSIZE   0x4E

CORBSTS

#define CORBSTS   0x4D

CORBUBASE

#define CORBUBASE   0x44

CORBWP

#define CORBWP   0x48

DPIBLBASE

#define DPIBLBASE   0x70

DPIBUBASE

#define DPIBUBASE   0x74

GCAP

#define GCAP   0x00

Device Registers.

BSD 2-Clause License

Copyright (c) 2022-2023, Manas Kamal Choudhury All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

GCTL

#define GCTL   0x08

GSTS

#define GSTS   0x10

HDA_GCAP_BSS

#define HDA_GCAP_BSS

(

gcap

)

(((gcap) & HDA_GCAP_BSS_MASK) >> HDA_GCAP_BSS_SHIFT)

HDA_GCAP_BSS_MASK

#define HDA_GCAP_BSS_MASK   0x00f8

HDA_GCAP_BSS_SHIFT

#define HDA_GCAP_BSS_SHIFT   3

HDA_GCAP_ISS

#define HDA_GCAP_ISS

(

gcap

)

(((gcap) & HDA_GCAP_ISS_MASK) >> HDA_GCAP_ISS_SHIFT)

HDA_GCAP_ISS_MASK

#define HDA_GCAP_ISS_MASK   0x0f00

HDA_GCAP_ISS_SHIFT

#define HDA_GCAP_ISS_SHIFT   8

HDA_GCAP_NSD0_MASK

#define HDA_GCAP_NSD0_MASK   0x0006

HDA_GCAP_NSD0_SHIFT

#define HDA_GCAP_NSD0_SHIFT   1

HDA_GCAP_OSS

#define HDA_GCAP_OSS

(

gcap

)

(((gcap) & HDA_GCAP_OSS_MASK) >> HDA_GCAP_OSS_SHIFT)

HDA_GCAP_OSS_MASK

#define HDA_GCAP_OSS_MASK   0xf000

HDA_GCAP_OSS_SHIFT

#define HDA_GCAP_OSS_SHIFT   12

HDA_INTCTL_CIE

#define HDA_INTCTL_CIE   0x40000000

HDA_INTCTL_GIE

#define HDA_INTCTL_GIE   0x80000000

HDAC_SDCTL_DEIE

#define HDAC_SDCTL_DEIE   0x000010

HDAC_SDCTL_FEIE

#define HDAC_SDCTL_FEIE   0x000008

HDAC_SDCTL_IOCE

#define HDAC_SDCTL_IOCE   0x000004

HDAC_SDCTL_RUN

#define HDAC_SDCTL_RUN   0x000002

HDAC_SDSTS_BCIS

#define HDAC_SDSTS_BCIS   (1<<2)

HDAC_SDSTS_DESE

#define HDAC_SDSTS_DESE   (1<<4)

HDAC_SDSTS_FIFOE

#define HDAC_SDSTS_FIFOE   (1<<3)

ICII

#define ICII   0x64

ICIS

#define ICIS   0x68

ICOI

#define ICOI   0x60

INPAY

#define INPAY   0x06

INSTRMPAY

#define INSTRMPAY   0x1A

INTCTL

#define INTCTL   0x20

INTSTS

#define INTSTS   0x24

OUTPAY

#define OUTPAY   0x04

OUTSTRMPAY

#define OUTSTRMPAY   0x18

REG_I0_BDPL

#define REG_I0_BDPL   0x98

Input 0 - BDL Pointer Lower.

REG_I0_BDPU

#define REG_I0_BDPU   0x9C

Input 0 - BDL Pointer Upper.

REG_I0_CBL

#define REG_I0_CBL   0x88

Input 0 - Cyclic Buffer Length.

REG_I0_CTLL

#define REG_I0_CTLL   0x80

Input 0 - Control Lower.

REG_I0_FIFOD

#define REG_I0_FIFOD   0x90

Input 0 - FIFO.

REG_I0_FMT

#define REG_I0_FMT   0x92

Input 0 - Format.

REG_I0_LPIB

#define REG_I0_LPIB   0x84

Input 0 - Link position in current buffer.

REG_I0_LVI

#define REG_I0_LVI   0x8C

Input 0 - Last Valid Index.

REG_I0_STS

#define REG_I0_STS   0x83

Input 0 - Status.

REG_O0_BDLPL

#define REG_O0_BDLPL   0x118

Output 0 - BDL Pointer Lower.

REG_O0_BDLPU

#define REG_O0_BDLPU   0x11c

Output 0 - BDL Pointer Upper.

REG_O0_CBL

#define REG_O0_CBL   0x108

Output 0 - Cyclic Buffer Length.

REG_O0_CTLL

#define REG_O0_CTLL   0x100

Output 0 - Control Lower.

REG_O0_CTLU

#define REG_O0_CTLU   0x102

Output 0 - Control Upper.

REG_O0_FIFOD

#define REG_O0_FIFOD   0x110

Output 0 - FIFO Size.

REG_O0_FMT

#define REG_O0_FMT   0x112

Output 0 - Format.

REG_O0_STLVI

#define REG_O0_STLVI   0x10c

Output 0 - Last Valid Index.

REG_O0_STS

#define REG_O0_STS   0x103

Output 0 - Status.

RINTCNT

#define RINTCNT   0x5A

RIRBCTL

#define RIRBCTL   0x5C

RIRBLBASE

#define RIRBLBASE   0x50

RIRBSIZE

#define RIRBSIZE   0x5E

RIRBSTS

#define RIRBSTS   0x5D

RIRBUBASE

#define RIRBUBASE   0x54

RIRBWP

#define RIRBWP   0x58

SD0CBL

#define SD0CBL   0x88

SD0CTL

#define SD0CTL   0x80

SD0FIFOD

#define SD0FIFOD   0x90

SD0FMT

#define SD0FMT   0x92

SD0LPIB

#define SD0LPIB   0x84

SD0LVI

#define SD0LVI   0x8C

SD0STS

#define SD0STS   0x83

SDBDPL

#define SDBDPL   0x98

SDBDPU

#define SDBDPU   0x9C

SSYNC

#define SSYNC   0x38

STATESTS

#define STATESTS   0x0E

VMAJ

#define VMAJ   0x03

VMIN

#define VMIN   0x02

WAKEEN

#define WAKEEN   0x0C

WALCLK

#define WALCLK   0x30

Typedef Documentation

HDABDLEntry

typedef struct _bdl_ HDABDLEntry

HDAudio

typedef struct _hd_audio_ HDAudio

Enumeration Type Documentation

codec_parameters

enum codec_parameters

Enumerator
PARAM_VENDOR_ID
PARAM_REV_ID
PARAM_NODE_COUNT
PARAM_FN_GROUP_TYPE
PARAM_AUDIO_WID_CAP
PARAM_PIN_CAP
PARAM_CONN_LIST_LEN
PARAM_OUT_AMP_CAP

codec_verbs

enum codec_verbs

Enumerator
VERB_GET_PARAMETER
VERB_GET_STREAM_CHANNEL
VERB_SET_STREAM_CHANNEL
VERB_SET_FORMAT
VERB_GET_AMP_GAIN_MUTE
VERB_SET_AMP_GAIN_MUTE
VERB_GET_CONFIG_DEFAULT
VERB_GET_CONN_LIST
VERB_GET_CONN_SELECT
VERB_SET_CONN_SELECT
VERB_GET_PIN_CONTROL
VERB_SET_PIN_CONTROL
VERB_GET_EAPD_BTL
VERB_SET_EAPD_BTL
VERB_GET_POWER_STATE
VERB_SET_POWER_STATE
VERB_SET_BEEP_GEN
VERB_GET_CONV_CHANNEL_COUNT
VERB_SET_CONV_CHANNEL_COUNT
VERB_GET_VOLUME_CONTROL
VERB_SET_VOLUME_CONTROL

fn_group_type

enum fn_group_type

Enumerator
FN_GROUP_AUDIO

pin_capabilities

enum pin_capabilities

Enumerator
PIN_CAP_OUTPUT
PIN_CAP_INPUT

pin_ctl_flags

enum pin_ctl_flags

Enumerator
PIN_CTL_ENABLE_HPHN
PIN_CTL_ENABLE_OUTPUT
PIN_CTL_ENABLE_INPUT
PIN_CTL_ENABLE_VREFEN
PIN_CTL_ENABLE_VREF_EN
PIN_CTL_ENABLE_VREF_EN2

reg_corbctl

enum reg_corbctl

Enumerator
CORBCTL_CORBRUN

reg_gctl

enum reg_gctl

Enumerator
GCTL_RESET

reg_rirbctl

enum reg_rirbctl

Enumerator
RIRBCTL_RIRBRUN

sample_format

enum sample_format

Enumerator
SR_48_KHZ
SR_44_KHZ
BITS_32
BITS_16
BITS_24
BITS_8

widget_capabilities

enum widget_capabilities

Enumerator
WIDGET_CAP_POWER_CNTRL
WIDGET_CAP_TYPE_SHIFT
WIDGET_CAP_TYPE_MASK

widget_type

enum widget_type

Enumerator
WIDGET_OUTPUT
WIDGET_INPUT
WIDGET_MIXER
WIDGET_SELECTOR
WIDGET_PIN
WIDGET_POWER
WIDGET_VOLUME_KNOB
WIDGET_BEEP_GEN
WIDGET_VENDOR_DEFINED

Function Documentation

_aud_inb_()

uint8_t _aud_inb_ ( int  reg )

extern

_aud_inl_()

uint32_t _aud_inl_ ( int  reg )

extern

_aud_inw_()

uint16_t _aud_inw_ ( int  reg )

extern

_aud_outb_()

void _aud_outb_ ( int  reg, uint8_t  value  )

extern

_aud_outl_()

void _aud_outl_ ( int  reg, uint32_t  value  )

extern

_aud_outw_()

void _aud_outw_ ( int  reg, uint16_t  value  )

extern

CORBWrite()

void CORBWrite ( uint32_t  verb )

extern

Check for immediate use

else use standard command transmitting method

HDAAddPath()

void HDAAddPath ( HDAAudioPath *  path )

extern

HDASetCodecInitFunc()

void HDASetCodecInitFunc ( void(*)(int codec, int nid)  init_func )

extern

HDASetVolume()

void HDASetVolume ( uint8_t  volume )

extern

HDASetVolumeFunc()

void HDASetVolumeFunc ( void(*)(uint8_t volume, int codec)  set_vol )

extern

HDAudioGetDMAPos()

uint64_t HDAudioGetDMAPos ( )

extern

HDAudioSetDMAPos()

void HDAudioSetDMAPos ( uint64_t  dma_buff )

extern

HDAudioSetSampleBuffer()

void HDAudioSetSampleBuffer ( uint64_t  buffer )

extern

RIRBRead()

void RIRBRead ( uint64_t *  response )

extern

RIRBRead - read a response from RIRB

Parameters

response

- address to where the controller will write response