imx8mp_clk.h

Go to the documentation of this file.

 
#ifndef __IMX8MP_CLK_H__
#define __IMX8MP_CLK_H__
 
#include <aurora.h>
// as per nxp ref
#define CCM_BASE 0x30380000
 
typedef enum _clock_root_select_ {
    ARM_A53_CLK_ROOT = 0,
    ARM_M7_CLK_ROOT,
    ML_CLK_ROOT,
    GPU3D_CORE_CLK_ROOT,
    GPU3D_SHADER_CLK_ROOT,
    GPU2D_CLK_ROOT,
    AUDIO_AXI_CLK_ROOT,
    HSIO_AXI_CLK_ROOT,
    MEDIA_ISP_CLK_ROOT,
    MAIN_AXI_CLK_ROOT = 16,
    ENET_AXI_CLK_ROOT,
    NAND_USDHC_BUS_CLK_ROOT,
    VPU_BUS_CLK_ROOT,
    MEDIA_AXI_CLK_ROOT,
    MEDIA_APB_CLK_ROOT,
    HDMI_APB_CLK_ROOT,
    HDMI_AXI_CLK_ROOT,
    GPU_AXI_CLK_ROOT,
    GPU_AHB_CLK_ROOT,
    NOC_CLK_ROOT,
    NOC_IO_CLK_ROOT,
    ML_AXI_CLK_ROOT,
    ML_AHB_CLK_ROOT,
    AHB_CLK_ROOT = 32,
    IPG_CLK_ROOT,
    AUDIO_AHB_CLK_ROOT,
    MEDIA_DISP2_CLK_ROOT = 38,
    DRAM_CLK_ROOT_SEL = 48,
    ARM_A53_CLK_ROOT_SEL,
    DRAM_ALT_CLK_ROOT = 64,
    DRAM_APB_CLK_ROOT, 
    VPU_G1_CLK_ROOT,
    VPU_G2_CLK_ROOT,
    CAN1_CLK_ROOT,
    CAN2_CLK_ROOT,
    MEMREPAIR_CLK_ROOT = 70,
    PCIE_PHY_CLK_ROOT,
    PCIE_AUX_CLK_ROOT,
    I2C5_CLK_ROOT,
    I2C6_CLK_ROOT,
    SAI1_CLK_ROOT,
    HDMI_FDCC_TST_CLK_ROOT = 118,
    HDMI_24M_ROOT,
    HDMI_REF_266M_ROOT,
    USDHC3_CLK_ROOT,
    MEDIA_CAM1_PIX_CLK_ROOT,
    MEDIA_MIPI_PHY1_REF_CLK_ROOT,
    MEDIA_DISP1_PIX_CLK_ROOT,
    MEDIA_CAM2_PIX_CLK_ROOT,
    MEDIA_LDB_CLK_ROOT,
    MEDIA_MIPI_TEST_BYTE_CLK = 130,
    ECSPI3_CLK_ROOT,
    PDM_CLK_ROOT,
    VPU_VC8000E_CLK_ROOT,
    SAI7_CLK_ROOT
    /* incomplete */
}imx8mp_clock_root_select;
 
typedef enum _root_id_ {
    IMX8MP_CLK_GPC_ROOT = 183,
    IMX8MP_CLK_ANAMIX_ROOT,
    IMX8MP_CLK_CPU_ROOT,
    IMX8MP_CLK_CSU_ROOT,
    IMX8MP_CLK_DEBUG_ROOT,
    IMX8MP_CLK_DRAM1_ROOT,
    IMX8MP_CLK_ECSPI1_ROOT,
    IMX8MP_CLK_ECSPI2_ROOT,
    IMX8MP_CLK_ECSPI3_ROOT,
    IMX8MP_CLK_ENET1_ROOT,
    IMX8MP_CLK_GPIO1_ROOT,
    IMX8MP_CLK_GPIO2_ROOT,
    IMX8MP_CLK_GPIO3_ROOT,
    IMX8MP_CLK_GPIO4_ROOT,
    IMX8MP_CLK_GPIO5_ROOT,
    IMX8MP_CLK_GPT1_ROOT,
    IMX8MP_CLK_GPT2_ROOT,
    IMX8MP_CLK_GPT3_ROOT,
    IMX8MP_CLK_GPT4_ROOT,
    IMX8MP_CLK_GPT5_ROOT,
    IMX8MP_CLK_GPT6_ROOT,
    IMX8MP_CLK_HS_ROOT,
    IMX8MP_CLK_I2C1_ROOT,
    IMX8MP_CLK_I2C2_ROOT,
    IMX8MP_CLK_I2C3_ROOT,
    IMX8MP_CLK_I2C4_ROOT,
    IMX8MP_CLK_IOMUX_ROOT,
    IMX8MP_CLK_IPMUX1_ROOT,
    IMX8MP_CLK_IPMUX2_ROOT,
    IMX8MP_CLK_MU_ROOT,
    IMX8MP_CLK_OCOTP_ROOT,
    IMX8MP_CLK_OCRAM_ROOT,
    IMX8MP_CLK_PCIE_ROOT,
    IMX8MP_CLK_PERFMON1_ROOT,
    IMX8MP_CLK_PERFMON2_ROOT,
    IMX8MP_CLK_PWM1_ROOT,
    IMX8MP_CLK_PWM2_ROOT,
    IMX8MP_CLK_PWM3_ROOT,
    IMX8MP_CLK_PWM4_ROOT,
    IMX8MP_CLK_QOS_ROOT,
    IMX8MP_CLK_QOS_ENET_ROOT,
    IMX8MP_CLK_QSPI_ROOT,
    IMX8MP_CLK_NAND_ROOT,
    IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK,
    IMX8MP_CLK_RDC_ROOT,
    IMX8MP_CLK_ROM_ROOT,
    IMX8MP_CLK_I2C5_ROOT,
    IMX8MP_CLK_I2C6_ROOT,
    IMX8MP_CLK_CAN1_ROOT,
    IMX8MP_CLK_CAN2_ROOT,
    IMX8MP_CLK_SCTR_ROOT,
    IMX8MP_CLK_SDMA1_ROOT,
    IMX8MP_CLK_ENET_QOS_ROOT,
    IMX8MP_CLK_SEC_DEBUG_ROOT,
    IMX8MP_CLK_SEMA1_ROOT,
    IMX8MP_CLK_SEMA2_ROOT,
    IMX8MP_CLK_IRQ_STEER_ROOT,
    IMX8MP_CLK_SIM_ENET_ROOT,
    IMX8MP_CLK_SIM_M_ROOT,
    IMX8MP_CLK_SIM_MAIN_ROOT,
    IMX8MP_CLK_SIM_S_ROOT,
    IMX8MP_CLK_SIM_WAKEUP_ROOT,
    IMX8MP_CLK_GPU2D_ROOT,
    IMX8MP_CLK_GPU3D_ROOT,
    IMX8MP_CLK_SNVS_ROOT,
    IMX8MP_CLK_TRACE_ROOT,
    IMX8MP_CLK_UART1_ROOT,
    IMX8MP_CLK_UART2_ROOT,
    IMX8MP_CLK_UART3_ROOT,
    IMX8MP_CLK_UART4_ROOT,
    IMX8MP_CLK_USB_ROOT,
    IMX8MP_CLK_USB_PHY_ROOT,
    IMX8MP_CLK_USDHC1_ROOT,
    IMX8MP_CLK_USDHC2_ROOT,
    IMX8MP_CLK_WDOG1_ROOT,
    IMX8MP_CLK_WDOG2_ROOT,
    IMX8MP_CLK_WDOG3_ROOT,
    IMX8MP_CLK_VPU_G1_ROOT,
    IMX8MP_CLK_GPU_ROOT,
    IMX8MP_CLK_NOC_WRAPPER_ROOT,
    IMX8MP_CLK_VPU_VC8KE_ROOT,
    IMX8MP_CLK_VPU_G2_ROOT,
    IMX8MP_CLK_NPU_ROOT,
    IMX8MP_CLK_HSIO_ROOT,
    IMX8MP_CLK_MEDIA_APB_ROOT,
    IMX8MP_CLK_MEDIA_AXI_ROOT,
    IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT,
    IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT,
    IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT,
    IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT,
    IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT,
    IMX8MP_CLK_MEDIA_ISP_ROOT,
    IMX8MP_CLK_USDHC3_ROOT,
    IMX8MP_CLK_HDMI_ROOT,
    IMX8MP_CLK_XTAL_ROOT,
    IMX8MP_CLK_PLL_ROOT,
    IMX8MP_CLK_TSENSOR_ROOT,
    IMX8MP_CLK_VPU_ROOT,
    IMX8MP_CLK_MRPR_ROOT,
    IMX8MP_CLK_AUDIO_ROOT,
    IMX8MP_CLK_DRAM_ALT_ROOT,
    IMX8MP_CLK_MEDIA_LDB_ROOT,
    IMX8MP_CLK_AUDIO_AHB_ROOT,
    IMX8MP_CLK_AUDIO_AXI_ROOT,
    IMX8MP_CLK_SAI1_ROOT,
    IMX8MP_CLK_SAI2_ROOT,
    IMX8MP_CLK_SAI3_ROOT,
    IMX8MP_CLK_SAI5_ROOT,
    IMX8MP_CLK_SAI6_ROOT,
    IMX8MP_CLK_SAI7_ROOT,
    IMX8MP_CLK_PDM_ROOT,
    IMX8MP_CLK_USB_SUSP,
}imx8mp_clk_root_id;
 
#define DT_IMX8MP_CLK_GPC_ROOT 183
#define DT_IMX8MP_CLK_ANAMIX_ROOT  184
#define DT_IMX8MP_CLK_CPU_ROOT 185
#define DT_IMX8MP_CLK_CSU_ROOT 186
#define DT_IMX8MP_CLK_DEBUG_ROOT 187
#define DT_IMX8MP_CLK_DRAM1_ROOT 188
#define DT_IMX8MP_CLK_ECSPI1_ROOT 189
#define DT_IMX8MP_CLK_ECSPI2_ROOT 190
#define DT_IMX8MP_CLK_ECSPI3_ROOT 191
#define DT_IMX8MP_CLK_ENET1_ROOT  192
#define DT_IMX8MP_CLK_GPIO1_ROOT 193
#define DT_IMX8MP_CLK_GPIO2_ROOT 194
#define DT_IMX8MP_CLK_GPIO3_ROOT 195
#define DT_IMX8MP_CLK_GPIO4_ROOT 196
#define DT_IMX8MP_CLK_GPIO5_ROOT 197
#define DT_IMX8MP_CLK_GPT1_ROOT  198
#define DT_IMX8MP_CLK_GPT2_ROOT 199
#define DT_IMX8MP_CLK_GPT3_ROOT 200
#define DT_IMX8MP_CLK_GPT4_ROOT 201
#define DT_IMX8MP_CLK_GPT5_ROOT 202
#define DT_IMX8MP_CLK_GPT6_ROOT 203
#define DT_IMX8MP_CLK_HS_ROOT 204
#define DT_IMX8MP_CLK_I2C1_ROOT 205
#define DT_IMX8MP_CLK_I2C2_ROOT 206
#define DT_IMX8MP_CLK_I2C3_ROOT 207
#define DT_IMX8MP_CLK_I2C4_ROOT 208
#define DT_IMX8MP_CLK_IOMUX_ROOT 209
#define DT_IMX8MP_CLK_IPMUX1_ROOT 210
#define DT_IMX8MP_CLK_IPMUX2_ROOT 211
#define DT_IMX8MP_CLK_IPMUX3_ROOT 212
#define DT_IMX8MP_CLK_MU_ROOT 213
#define DT_IMX8MP_CLK_OCUTP_ROOT 214
#define DT_IMX8MP_CLK_OCRAM_ROOT 215
#define DT_IMX8MP_CLK_OCRAM_S_ROOT 216
#define DT_IMX8MP_CLK_PCIE_ROOT 217
#define DT_IMX8MP_CLK_PERFMON1_ROOT 218
#define DT_IMX8MP_CLK_PERFMON2_ROOT 219
#define DT_IMX8MP_CLK_PWM1_ROOT 220
#define DT_IMX8MP_CLK_PWM2_ROOT 221
#define DT_IMX8MP_CLK_PWM3_ROOT 222
#define DT_IMX8MP_CLK_PWM4_ROOT 223
#define DT_IMX8MP_CLK_QOS_ROOT 224
#define DT_IMX8MP_CLK_QOS_ENET_ROOT 225
#define DT_IMX8MP_CLK_QSPI_ROOT 226
#define DT_IMX8MP_CLK_NAND_ROOT 227
#define DT_IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 228
#define DT_IMX8MP_CLK_RDC_ROOT 229
#define DT_IMX8MP_CLK_ROM_ROOT 230
#define DT_IMX8MP_CLK_I2C5_ROOT 231
#define DT_IMX8MP_CLK_I2C6_ROOT 232
#define DT_IMX8MP_CLK_CAN1_ROOT 233
#define DT_IMX8MP_CLK_CAN2_ROOT 234
#define DT_IMX8MP_CLK_SCTR_ROOT 235
#define DT_IMX8MP_CLK_SDMA1_ROOT 236
#define DT_IMX8MP_CLK_ENET_QOS_ROOT 237
#define DT_IMX8MP_CLK_SEC_DEBUG_ROOT 238
#define DT_IMX8MP_CLK_SEMA1_ROOT 239
#define DT_IMX8MP_CLK_SEMA2_ROOT 240
#define DT_IMX8MP_CLK_IRQ_STEER_ROOT 241
#define DT_IMX8MP_CLK_SIM_ENET_ROOT 242
#define DT_IMX8MP_CLK_SIM_M_ROOT 243
#define DT_IMX8MP_CLK_SIM_MAIN_ROOT 244
#define DT_IMX8MP_CLK_SIM_S_ROOT 245
#define DT_IMX8MP_CLK_SIM_WAKEUP_ROOT 246
#define DT_IMX8MP_CLK_GPU2D_ROOT 247
#define DT_IMX8MP_CLK_GPU3D_ROOT 248
#define DT_IMX8MP_CLK_SNVS_ROOT 249
#define DT_IMX8MP_CLK_TRACE_ROOT 250
#define DT_IMX8MP_CLK_UART1_ROOT 251
#define DT_IMX8MP_CLK_UART2_ROOT 252
#define DT_IMX8MP_CLK_UART3_ROOT 253
#define DT_IMX8MP_CLK_UART4_ROOT 254
#define DT_IMX8MP_CLK_USB_ROOT 255
#define DT_IMX8MP_CLK_USB_PHY_ROOT 256
#define DT_IMX8MP_CLK_USDHC1_ROOT 257
#define DT_IMX8MP_CLK_USDHC2_ROOT           258
#define DT_IMX8MP_CLK_WDOG1_ROOT            259
#define DT_IMX8MP_CLK_WDOG2_ROOT            260
#define DT_IMX8MP_CLK_WDOG3_ROOT            261
#define DT_IMX8MP_CLK_VPU_G1_ROOT           262
#define DT_IMX8MP_CLK_GPU_ROOT          263
#define DT_IMX8MP_CLK_NOC_WRAPPER_ROOT      264
#define DT_IMX8MP_CLK_VPU_VC8KE_ROOT        265
#define DT_IMX8MP_CLK_VPU_G2_ROOT           266
#define DT_IMX8MP_CLK_NPU_ROOT          267
#define DT_IMX8MP_CLK_HSIO_ROOT         268
#define DT_IMX8MP_CLK_MEDIA_APB_ROOT        269
#define DT_IMX8MP_CLK_MEDIA_AXI_ROOT        270
#define DT_IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT       271
#define DT_IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT       272
#define DT_IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT      273
#define DT_IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT      274
#define DT_IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT  275
#define DT_IMX8MP_CLK_MEDIA_ISP_ROOT        276
#define DT_IMX8MP_CLK_USDHC3_ROOT           277
#define DT_IMX8MP_CLK_HDMI_ROOT         278
#define DT_IMX8MP_CLK_XTAL_ROOT         279
#define DT_IMX8MP_CLK_PLL_ROOT          280
#define DT_IMX8MP_CLK_TSENSOR_ROOT          281
#define DT_IMX8MP_CLK_VPU_ROOT          282
#define DT_IMX8MP_CLK_MRPR_ROOT         283
#define DT_IMX8MP_CLK_AUDIO_ROOT            284
#define DT_IMX8MP_CLK_DRAM_ALT_ROOT     285
#define DT_IMX8MP_CLK_DRAM_CORE         286
 
#define CCM_ROOT_REG(base, root_idx)  (base + 0x8000 + (root_idx * 0x80))
#define CCM_TARGET_ROOT(base, root_idx) CCM_ROOT_REG(base, root_idx)
#define CCM_TARGET_ROOT_SET(base, root_idx) (CCM_ROOT_REG(base, root_idx) + 0x04)
#define CCM_TARGET_ROOT_CLR(base, root_idx) (CCM_ROOT_REG(base, root_idx) + 0x08)
#define CCM_TARGET_ROOT_TOG(base, root_idx) (CCM_ROOT_REG(base, root_idx) + 0x0C)
 
#define TARGET_ROOT_ENABLE (1u << 28)
#define TARGET_ROOT_MUX(x)  (((x) & 0x7u) << 24)
#define TARGET_ROOT_PRE(x)  (((x) & 0x7u) << 16)
#define TARGET_ROOT_POST(x) (((x) & 0x3Fu) << 0)
 
 
#define MUX_MEDIA_AXI_SYS_PLL2_500M    7
#define MUX_MEDIA_APB_SYS_PLL1_133M    7
#define MUX_HDMI_REF_266M_SYS_PLL1_266 4
#define MUX_HDMI_24M_OSC_24M           0
#define MUX_HDMI_FDCC_SYS_PLL1_266M    1
#define MUX_DISP2_PIX_VIDEO_PLL1       1
 
 
extern void imx8mp_ccm_init();
 
AU_EXTERN AU_EXPORT void imx8mp_ccm_write(uint32_t clk_root_idx,int offset, uint32_t value);
 
 
extern uint64_t imx8mp_ccm_get_base();
 
#endif