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Macros | Typedefs | Enumerations | Functions
imx8mp_clk.h File Reference
#include <aurora.h>
Include dependency graph for imx8mp_clk.h:
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Go to the source code of this file.

Macros

#define CCM_BASE   0x30380000
 
#define CCM_ROOT_REG(base, root_idx)   (base + 0x8000 + (root_idx * 0x80))
 
#define CCM_TARGET_ROOT(base, root_idx)   CCM_ROOT_REG(base, root_idx)
 
#define CCM_TARGET_ROOT_SET(base, root_idx)   (CCM_ROOT_REG(base, root_idx) + 0x04)
 
#define CCM_TARGET_ROOT_CLR(base, root_idx)   (CCM_ROOT_REG(base, root_idx) + 0x08)
 
#define CCM_TARGET_ROOT_TOG(base, root_idx)   (CCM_ROOT_REG(base, root_idx) + 0x0C)
 
#define TARGET_ROOT_ENABLE   (1u << 28)
 
#define TARGET_ROOT_MUX(x)   (((x) & 0x7u) << 24)
 
#define TARGET_ROOT_PRE(x)   (((x) & 0x7u) << 16)
 
#define TARGET_ROOT_POST(x)   (((x) & 0x3Fu) << 0)
 
#define MUX_MEDIA_AXI_SYS_PLL2_500M   7
 
#define MUX_MEDIA_APB_SYS_PLL1_133M   7
 
#define MUX_HDMI_REF_266M_SYS_PLL1_266   4
 
#define MUX_HDMI_24M_OSC_24M   0
 
#define MUX_HDMI_FDCC_SYS_PLL1_266M   1
 
#define MUX_DISP2_PIX_VIDEO_PLL1   1
 

Typedefs

typedef enum _clock_root_select_ imx8mp_clock_root_select
 
typedef enum _root_id_ imx8mp_clk_root_id
 

Enumerations

enum  _clock_root_select_ {
  ARM_A53_CLK_ROOT = 0 , ARM_M7_CLK_ROOT , ML_CLK_ROOT , GPU3D_CORE_CLK_ROOT ,
  GPU3D_SHADER_CLK_ROOT , GPU2D_CLK_ROOT , AUDIO_AXI_CLK_ROOT , HSIO_AXI_CLK_ROOT ,
  MEDIA_ISP_CLK_ROOT , MAIN_AXI_CLK_ROOT = 16 , ENET_AXI_CLK_ROOT , NAND_USDHC_BUS_CLK_ROOT ,
  VPU_BUS_CLK_ROOT , MEDIA_AXI_CLK_ROOT , MEDIA_APB_CLK_ROOT , HDMI_APB_CLK_ROOT ,
  HDMI_AXI_CLK_ROOT , GPU_AXI_CLK_ROOT , GPU_AHB_CLK_ROOT , NOC_CLK_ROOT ,
  NOC_IO_CLK_ROOT , ML_AXI_CLK_ROOT , ML_AHB_CLK_ROOT , AHB_CLK_ROOT = 32 ,
  IPG_CLK_ROOT , AUDIO_AHB_CLK_ROOT , MEDIA_DISP2_CLK_ROOT = 38 , DRAM_CLK_ROOT_SEL = 48 ,
  ARM_A53_CLK_ROOT_SEL , DRAM_ALT_CLK_ROOT = 64 , DRAM_APB_CLK_ROOT , VPU_G1_CLK_ROOT ,
  VPU_G2_CLK_ROOT , CAN1_CLK_ROOT , CAN2_CLK_ROOT , MEMREPAIR_CLK_ROOT = 70 ,
  PCIE_PHY_CLK_ROOT , PCIE_AUX_CLK_ROOT , I2C5_CLK_ROOT , I2C6_CLK_ROOT ,
  SAI1_CLK_ROOT , HDMI_FDCC_TST_CLK_ROOT = 118 , HDMI_24M_ROOT , HDMI_REF_266M_ROOT
}
 
enum  _root_id_ {
  IMX8MP_CLK_GPC_ROOT = 183 , IMX8MP_CLK_ANAMIX_ROOT , IMX8MP_CLK_CPU_ROOT , IMX8MP_CLK_CSU_ROOT ,
  IMX8MP_CLK_DEBUG_ROOT , IMX8MP_CLK_DRAM1_ROOT , IMX8MP_CLK_ECSPI1_ROOT , IMX8MP_CLK_ECSPI2_ROOT ,
  IMX8MP_CLK_ECSPI3_ROOT , IMX8MP_CLK_ENET1_ROOT , IMX8MP_CLK_GPIO1_ROOT , IMX8MP_CLK_GPIO2_ROOT ,
  IMX8MP_CLK_GPIO3_ROOT , IMX8MP_CLK_GPIO4_ROOT , IMX8MP_CLK_GPIO5_ROOT , IMX8MP_CLK_GPT1_ROOT ,
  IMX8MP_CLK_GPT2_ROOT , IMX8MP_CLK_GPT3_ROOT , IMX8MP_CLK_GPT4_ROOT , IMX8MP_CLK_GPT5_ROOT ,
  IMX8MP_CLK_GPT6_ROOT , IMX8MP_CLK_HS_ROOT , IMX8MP_CLK_I2C1_ROOT , IMX8MP_CLK_I2C2_ROOT ,
  IMX8MP_CLK_I2C3_ROOT , IMX8MP_CLK_I2C4_ROOT , IMX8MP_CLK_IOMUX_ROOT , IMX8MP_CLK_IPMUX1_ROOT ,
  IMX8MP_CLK_IPMUX2_ROOT , IMX8MP_CLK_MU_ROOT , IMX8MP_CLK_OCOTP_ROOT , IMX8MP_CLK_OCRAM_ROOT ,
  IMX8MP_CLK_PCIE_ROOT , IMX8MP_CLK_PERFMON1_ROOT , IMX8MP_CLK_PERFMON2_ROOT , IMX8MP_CLK_PWM1_ROOT ,
  IMX8MP_CLK_PWM2_ROOT , IMX8MP_CLK_PWM3_ROOT , IMX8MP_CLK_PWM4_ROOT , IMX8MP_CLK_QOS_ROOT ,
  IMX8MP_CLK_QOS_ENET_ROOT , IMX8MP_CLK_QSPI_ROOT , IMX8MP_CLK_NAND_ROOT , IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK ,
  IMX8MP_CLK_RDC_ROOT , IMX8MP_CLK_ROM_ROOT , IMX8MP_CLK_I2C5_ROOT , IMX8MP_CLK_I2C6_ROOT ,
  IMX8MP_CLK_CAN1_ROOT , IMX8MP_CLK_CAN2_ROOT , IMX8MP_CLK_SCTR_ROOT , IMX8MP_CLK_SDMA1_ROOT ,
  IMX8MP_CLK_ENET_QOS_ROOT , IMX8MP_CLK_SEC_DEBUG_ROOT , IMX8MP_CLK_SEMA1_ROOT , IMX8MP_CLK_SEMA2_ROOT ,
  IMX8MP_CLK_IRQ_STEER_ROOT , IMX8MP_CLK_SIM_ENET_ROOT , IMX8MP_CLK_SIM_M_ROOT , IMX8MP_CLK_SIM_MAIN_ROOT ,
  IMX8MP_CLK_SIM_S_ROOT , IMX8MP_CLK_SIM_WAKEUP_ROOT , IMX8MP_CLK_GPU2D_ROOT , IMX8MP_CLK_GPU3D_ROOT ,
  IMX8MP_CLK_SNVS_ROOT , IMX8MP_CLK_TRACE_ROOT , IMX8MP_CLK_UART1_ROOT , IMX8MP_CLK_UART2_ROOT ,
  IMX8MP_CLK_UART3_ROOT , IMX8MP_CLK_UART4_ROOT , IMX8MP_CLK_USB_ROOT , IMX8MP_CLK_USB_PHY_ROOT ,
  IMX8MP_CLK_USDHC1_ROOT , IMX8MP_CLK_USDHC2_ROOT , IMX8MP_CLK_WDOG1_ROOT , IMX8MP_CLK_WDOG2_ROOT ,
  IMX8MP_CLK_WDOG3_ROOT , IMX8MP_CLK_VPU_G1_ROOT , IMX8MP_CLK_GPU_ROOT , IMX8MP_CLK_NOC_WRAPPER_ROOT ,
  IMX8MP_CLK_VPU_VC8KE_ROOT , IMX8MP_CLK_VPU_G2_ROOT , IMX8MP_CLK_NPU_ROOT , IMX8MP_CLK_HSIO_ROOT ,
  IMX8MP_CLK_MEDIA_APB_ROOT , IMX8MP_CLK_MEDIA_AXI_ROOT , IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT , IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT ,
  IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT , IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT , IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT , IMX8MP_CLK_MEDIA_ISP_ROOT ,
  IMX8MP_CLK_USDHC3_ROOT , IMX8MP_CLK_HDMI_ROOT , IMX8MP_CLK_XTAL_ROOT , IMX8MP_CLK_PLL_ROOT ,
  IMX8MP_CLK_TSENSOR_ROOT , IMX8MP_CLK_VPU_ROOT , IMX8MP_CLK_MRPR_ROOT , IMX8MP_CLK_AUDIO_ROOT ,
  IMX8MP_CLK_DRAM_ALT_ROOT , IMX8MP_CLK_MEDIA_LDB_ROOT , IMX8MP_CLK_AUDIO_AHB_ROOT , IMX8MP_CLK_AUDIO_AXI_ROOT ,
  IMX8MP_CLK_SAI1_ROOT , IMX8MP_CLK_SAI2_ROOT , IMX8MP_CLK_SAI3_ROOT , IMX8MP_CLK_SAI5_ROOT ,
  IMX8MP_CLK_SAI6_ROOT , IMX8MP_CLK_SAI7_ROOT , IMX8MP_CLK_PDM_ROOT , IMX8MP_CLK_USB_SUSP
}
 

Functions

void imx8mp_ccm_init ()
 imx8mp_void_ccm_init – map the ccm module
 
AU_EXTERN AU_EXPORT void imx8mp_ccm_write (uint32_t clk_root_idx, int offset, uint32_t value)
 imx8mp_ccm_write – write value to clock indexed register
 

Detailed Description

BSD 2-Clause License

Copyright (c) 2022-2026, Manas Kamal Choudhury All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

◆ CCM_BASE

#define CCM_BASE   0x30380000

Clock Control Module regs

◆ CCM_ROOT_REG

#define CCM_ROOT_REG (   base,
  root_idx 
)    (base + 0x8000 + (root_idx * 0x80))

formula to get specific peripheral clock source

◆ CCM_TARGET_ROOT

#define CCM_TARGET_ROOT (   base,
  root_idx 
)    CCM_ROOT_REG(base, root_idx)

◆ CCM_TARGET_ROOT_CLR

#define CCM_TARGET_ROOT_CLR (   base,
  root_idx 
)    (CCM_ROOT_REG(base, root_idx) + 0x08)

◆ CCM_TARGET_ROOT_SET

#define CCM_TARGET_ROOT_SET (   base,
  root_idx 
)    (CCM_ROOT_REG(base, root_idx) + 0x04)

◆ CCM_TARGET_ROOT_TOG

#define CCM_TARGET_ROOT_TOG (   base,
  root_idx 
)    (CCM_ROOT_REG(base, root_idx) + 0x0C)

◆ MUX_DISP2_PIX_VIDEO_PLL1

#define MUX_DISP2_PIX_VIDEO_PLL1   1

◆ MUX_HDMI_24M_OSC_24M

#define MUX_HDMI_24M_OSC_24M   0

◆ MUX_HDMI_FDCC_SYS_PLL1_266M

#define MUX_HDMI_FDCC_SYS_PLL1_266M   1

◆ MUX_HDMI_REF_266M_SYS_PLL1_266

#define MUX_HDMI_REF_266M_SYS_PLL1_266   4

◆ MUX_MEDIA_APB_SYS_PLL1_133M

#define MUX_MEDIA_APB_SYS_PLL1_133M   7

◆ MUX_MEDIA_AXI_SYS_PLL2_500M

#define MUX_MEDIA_AXI_SYS_PLL2_500M   7

◆ TARGET_ROOT_ENABLE

#define TARGET_ROOT_ENABLE   (1u << 28)

◆ TARGET_ROOT_MUX

#define TARGET_ROOT_MUX (   x)    (((x) & 0x7u) << 24)

◆ TARGET_ROOT_POST

#define TARGET_ROOT_POST (   x)    (((x) & 0x3Fu) << 0)

◆ TARGET_ROOT_PRE

#define TARGET_ROOT_PRE (   x)    (((x) & 0x7u) << 16)

Typedef Documentation

◆ imx8mp_clk_root_id

◆ imx8mp_clock_root_select

clock roots

Enumeration Type Documentation

◆ _clock_root_select_

clock roots

Enumerator
ARM_A53_CLK_ROOT 
ARM_M7_CLK_ROOT 
ML_CLK_ROOT 
GPU3D_CORE_CLK_ROOT 
GPU3D_SHADER_CLK_ROOT 
GPU2D_CLK_ROOT 
AUDIO_AXI_CLK_ROOT 
HSIO_AXI_CLK_ROOT 
MEDIA_ISP_CLK_ROOT 
MAIN_AXI_CLK_ROOT 
ENET_AXI_CLK_ROOT 
NAND_USDHC_BUS_CLK_ROOT 
VPU_BUS_CLK_ROOT 
MEDIA_AXI_CLK_ROOT 
MEDIA_APB_CLK_ROOT 
HDMI_APB_CLK_ROOT 
HDMI_AXI_CLK_ROOT 
GPU_AXI_CLK_ROOT 
GPU_AHB_CLK_ROOT 
NOC_CLK_ROOT 
NOC_IO_CLK_ROOT 
ML_AXI_CLK_ROOT 
ML_AHB_CLK_ROOT 
AHB_CLK_ROOT 
IPG_CLK_ROOT 
AUDIO_AHB_CLK_ROOT 
MEDIA_DISP2_CLK_ROOT 
DRAM_CLK_ROOT_SEL 
ARM_A53_CLK_ROOT_SEL 
DRAM_ALT_CLK_ROOT 
DRAM_APB_CLK_ROOT 
VPU_G1_CLK_ROOT 
VPU_G2_CLK_ROOT 
CAN1_CLK_ROOT 
CAN2_CLK_ROOT 
MEMREPAIR_CLK_ROOT 
PCIE_PHY_CLK_ROOT 
PCIE_AUX_CLK_ROOT 
I2C5_CLK_ROOT 
I2C6_CLK_ROOT 
SAI1_CLK_ROOT 
HDMI_FDCC_TST_CLK_ROOT 
HDMI_24M_ROOT 
HDMI_REF_266M_ROOT 

◆ _root_id_

enum _root_id_
Enumerator
IMX8MP_CLK_GPC_ROOT 
IMX8MP_CLK_ANAMIX_ROOT 
IMX8MP_CLK_CPU_ROOT 
IMX8MP_CLK_CSU_ROOT 
IMX8MP_CLK_DEBUG_ROOT 
IMX8MP_CLK_DRAM1_ROOT 
IMX8MP_CLK_ECSPI1_ROOT 
IMX8MP_CLK_ECSPI2_ROOT 
IMX8MP_CLK_ECSPI3_ROOT 
IMX8MP_CLK_ENET1_ROOT 
IMX8MP_CLK_GPIO1_ROOT 
IMX8MP_CLK_GPIO2_ROOT 
IMX8MP_CLK_GPIO3_ROOT 
IMX8MP_CLK_GPIO4_ROOT 
IMX8MP_CLK_GPIO5_ROOT 
IMX8MP_CLK_GPT1_ROOT 
IMX8MP_CLK_GPT2_ROOT 
IMX8MP_CLK_GPT3_ROOT 
IMX8MP_CLK_GPT4_ROOT 
IMX8MP_CLK_GPT5_ROOT 
IMX8MP_CLK_GPT6_ROOT 
IMX8MP_CLK_HS_ROOT 
IMX8MP_CLK_I2C1_ROOT 
IMX8MP_CLK_I2C2_ROOT 
IMX8MP_CLK_I2C3_ROOT 
IMX8MP_CLK_I2C4_ROOT 
IMX8MP_CLK_IOMUX_ROOT 
IMX8MP_CLK_IPMUX1_ROOT 
IMX8MP_CLK_IPMUX2_ROOT 
IMX8MP_CLK_MU_ROOT 
IMX8MP_CLK_OCOTP_ROOT 
IMX8MP_CLK_OCRAM_ROOT 
IMX8MP_CLK_PCIE_ROOT 
IMX8MP_CLK_PERFMON1_ROOT 
IMX8MP_CLK_PERFMON2_ROOT 
IMX8MP_CLK_PWM1_ROOT 
IMX8MP_CLK_PWM2_ROOT 
IMX8MP_CLK_PWM3_ROOT 
IMX8MP_CLK_PWM4_ROOT 
IMX8MP_CLK_QOS_ROOT 
IMX8MP_CLK_QOS_ENET_ROOT 
IMX8MP_CLK_QSPI_ROOT 
IMX8MP_CLK_NAND_ROOT 
IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK 
IMX8MP_CLK_RDC_ROOT 
IMX8MP_CLK_ROM_ROOT 
IMX8MP_CLK_I2C5_ROOT 
IMX8MP_CLK_I2C6_ROOT 
IMX8MP_CLK_CAN1_ROOT 
IMX8MP_CLK_CAN2_ROOT 
IMX8MP_CLK_SCTR_ROOT 
IMX8MP_CLK_SDMA1_ROOT 
IMX8MP_CLK_ENET_QOS_ROOT 
IMX8MP_CLK_SEC_DEBUG_ROOT 
IMX8MP_CLK_SEMA1_ROOT 
IMX8MP_CLK_SEMA2_ROOT 
IMX8MP_CLK_IRQ_STEER_ROOT 
IMX8MP_CLK_SIM_ENET_ROOT 
IMX8MP_CLK_SIM_M_ROOT 
IMX8MP_CLK_SIM_MAIN_ROOT 
IMX8MP_CLK_SIM_S_ROOT 
IMX8MP_CLK_SIM_WAKEUP_ROOT 
IMX8MP_CLK_GPU2D_ROOT 
IMX8MP_CLK_GPU3D_ROOT 
IMX8MP_CLK_SNVS_ROOT 
IMX8MP_CLK_TRACE_ROOT 
IMX8MP_CLK_UART1_ROOT 
IMX8MP_CLK_UART2_ROOT 
IMX8MP_CLK_UART3_ROOT 
IMX8MP_CLK_UART4_ROOT 
IMX8MP_CLK_USB_ROOT 
IMX8MP_CLK_USB_PHY_ROOT 
IMX8MP_CLK_USDHC1_ROOT 
IMX8MP_CLK_USDHC2_ROOT 
IMX8MP_CLK_WDOG1_ROOT 
IMX8MP_CLK_WDOG2_ROOT 
IMX8MP_CLK_WDOG3_ROOT 
IMX8MP_CLK_VPU_G1_ROOT 
IMX8MP_CLK_GPU_ROOT 
IMX8MP_CLK_NOC_WRAPPER_ROOT 
IMX8MP_CLK_VPU_VC8KE_ROOT 
IMX8MP_CLK_VPU_G2_ROOT 
IMX8MP_CLK_NPU_ROOT 
IMX8MP_CLK_HSIO_ROOT 
IMX8MP_CLK_MEDIA_APB_ROOT 
IMX8MP_CLK_MEDIA_AXI_ROOT 
IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT 
IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT 
IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT 
IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT 
IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT 
IMX8MP_CLK_MEDIA_ISP_ROOT 
IMX8MP_CLK_USDHC3_ROOT 
IMX8MP_CLK_HDMI_ROOT 
IMX8MP_CLK_XTAL_ROOT 
IMX8MP_CLK_PLL_ROOT 
IMX8MP_CLK_TSENSOR_ROOT 
IMX8MP_CLK_VPU_ROOT 
IMX8MP_CLK_MRPR_ROOT 
IMX8MP_CLK_AUDIO_ROOT 
IMX8MP_CLK_DRAM_ALT_ROOT 
IMX8MP_CLK_MEDIA_LDB_ROOT 
IMX8MP_CLK_AUDIO_AHB_ROOT 
IMX8MP_CLK_AUDIO_AXI_ROOT 
IMX8MP_CLK_SAI1_ROOT 
IMX8MP_CLK_SAI2_ROOT 
IMX8MP_CLK_SAI3_ROOT 
IMX8MP_CLK_SAI5_ROOT 
IMX8MP_CLK_SAI6_ROOT 
IMX8MP_CLK_SAI7_ROOT 
IMX8MP_CLK_PDM_ROOT 
IMX8MP_CLK_USB_SUSP 

Function Documentation

◆ imx8mp_ccm_init()

void imx8mp_ccm_init ( )
extern

imx8mp_void_ccm_init – map the ccm module

◆ imx8mp_ccm_write()

AU_EXTERN AU_EXPORT void imx8mp_ccm_write ( uint32_t  clk_root_idx,
int  offset,
uint32_t  value 
)

imx8mp_ccm_write – write value to clock indexed register