imx8mp_pll.h

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#ifndef __IMX8MP_PLL_H__
#define __IMX8MP_PLL_H__
 
#include <bordoisila_bits.h>
 
#define __IMX8MP_CCM_BASE__ 0x30360000 //hardcoded from IMX8MP reference PRM, CCM_ANALOG_BASE
#define __IMX8MP_AUDIO_PLL1_GEN_CTRL   __IMX8MP_CCM_BASE__
#define __IMX8MP_AUDIO_PLL1_FDIV_CTL0  (__IMX8MP_CCM_BASE__ + 0x4)
#define __IMX8MP_AUDIO_PLL1_FDIV_CTL1  (__IMX8MP_CCM_BASE__ + 0x8)
#define __IMX8MP_AUDIO_PLL1_SSCG_CTRL  (__IMX8MP_CCM_BASE__ + 0xC)
#define __IMX8MP_AUDIO_PLL1_MNIT_CTRL  (__IMX8MP_CCM_BASE__ + 0x10)
 
 
#define __IMX8MP_AUDIO_PLL2_GEN_CTRL   (__IMX8MP_CCM_BASE__ + 0x14)
#define __IMX8MP_AUDIO_PLL2_FDIV_CTL0  (__IMX8MP_CCM_BASE__ + 0x18)
#define __IMX8MP_AUDIO_PLL2_FDIV_CTL1  (__IMX8MP_CCM_BASE__ + 0x1C)
#define __IMX8MP_AUDIO_PLL2_SSCG_CTRL  (__IMX8MP_CCM_BASE__ + 0x20)
#define __IMX8MP_AUDIO_PLL2_MNIT_CTRL  (__IMX8MP_CCM_BASE__ + 0x24)
 
#define __IMX8MP_VIDEO_PLL1_GEN_CTRL   (__IMX8MP_CCM_BASE__ + 0x28)
#define __IMX8MP_VIDEO_PLL1_FDIV_CTL0  (__IMX8MP_CCM_BASE__ + 0x2C)
#define __IMX8MP_VIDEO_PLL1_FDIV_CTL1  (__IMX8MP_CCM_BASE__ + 0x30)
#define __IMX8MP_VIDEO_PLL1_SSCG_CTRL  (__IMX8MP_CCM_BASE__ + 0x34)
#define __IMX8MP_VIDEO_PLL1_MNIT_CTRL  (__IMX8MP_CCM_BASE__ + 0x38)
 
#define __IMX8MP_DRAM_PLL_GEN_CTRL     (__IMX8MP_CCM_BASE__ + 0x50)
#define __IMX8MP_DRAM_PLL_FDIV_CTL0    (__IMX8MP_CCM_BASE__ + 0x54)
#define __IMX8MP_DRAM_PLL_FDIV_CTL1    (__IMX8MP_CCM_BASE__ + 0x58)
#define __IMX8MP_DRAM_PLL_SSCG_CTRL    (__IMX8MP_CCM_BASE__ + 0x5C)
#define __IMX8MP_DRAM_PLL_MNIT_CTRL    (__IMX8MP_CCM_BASE__ + 0x60)
 
#define __IMX8MP_GPU_PLL_GEN_CTRL      (__IMX8MP_CCM_BASE__ + 0x64)
#define __IMX8MP_GPU_PLL_FDIV_CTL0      (__IMX8MP_CCM_BASE__ + 0x68)
#define __IMX8MP_GPU_PLL_LOCKD_CTRL    (__IMX8MP_CCM_BASE__ + 0x6C)
#define __IMX8MP_GPU_PLL_MNIT_CTRL     (__IMX8MP_CCM_BASE__ + 0x70)
 
#define __IMX8MP_VPU_PLL_GEN_CTRL   (__IMX8MP_CCM_BASE__ + 0x74)
#define __IMX8MP_VPU_PLL_FDIV_CTL0  (__IMX8MP_CCM_BASE__ + 0x78)
#define __IMX8MP_VPU_PLL_LOCKD_CTRL (__IMX8MP_CCM_BASE__ + 0x7C)
#define __IMX8MP_VPU_PLL_MNIT_CTRL  (__IMX8MP_CCM_BASE__ + 0x80)
 
#define __IMX8MP_ARM_PLL_GEN_CTRL    (__IMX8MP_CCM_BASE__ + 0x84)
#define __IMX8MP_ARM_PLL_FDIV_CTL0   (__IMX8MP_CCM_BASE__ + 0x88)
#define __IMX8MP_ARM_PLL_LOCKD_CTRL  (__IMX8MP_CCM_BASE__ + 0x8C)
#define __IMX8MP_ARM_PLL_MNIT_CTRL   (__IMX8MP_CCM_BASE__ + 0x90)
 
#define __IMX8MP_SYS_PLL1_GEN_CTRL   (__IMX8MP_CCM_BASE__ + 0x94)
#define __IMX8MP_SYS_PLL1_FDIV_CTL0  (__IMX8MP_CCM_BASE__ + 0x98)
#define __IMX8MP_SYS_PLL1_LOCKD_CTRL (__IMX8MP_CCM_BASE__ + 0x9C)
#define __IMX8MP_SYS_PLL1_MNIT_CTRL  (__IMX8MP_CCM_BASE__ + 0x100)
 
#define __IMX8MP_SYS_PLL2_GEN_CTRL   (__IMX8MP_CCM_BASE__ + 0x104)
#define __IMX8MP_SYS_PLL2_FDIV_CTL0  (__IMX8MP_CCM_BASE__ + 0x108)
#define __IMX8MP_SYS_PLL2_LOCKD_CTRL (__IMX8MP_CCM_BASE__ + 0x10C)
#define __IMX8MP_SYS_PLL2_MNIT_CTRL  (__IMX8MP_CCM_BASE__ + 0x110)
 
#define __IMX8MP_SYS_PLL3_GEN_CTRL   (__IMX8MP_CCM_BASE__ + 0x114)
#define __IMX8MP_SYS_PLL3_FDIV_CTL0  (__IMX8MP_CCM_BASE__ + 0x118)
#define __IMX8MP_SYS_PLL3_LOCKD_CTRL (__IMX8MP_CCM_BASE__ + 0x11C)
#define __IMX8MP_SYS_PLL3_MNIT_CTRL  (__IMX8MP_CCM_BASE__ + 0x120)
 
#define __IMX8MP_OSC_MISC_CFG         (__IMX8MP_CCM_BASE__ + 0x124)
#define __IMX8MP_ANAMIX_PLL_MNIT_CTL  (__IMX8MP_CCM_BASE__ + 0X128)
#define __IMX8MP_CCM_ANALOG_DIGPROG   0x800
 
 
#define IMX8MP_PLL14XX_MDIV_SHIFT 12
#define IMX8MP_PLL14XX_MDIV_MASK  BORDOISILA_GENMASK(21,12)
#define IMX8MP_PLL14XX_PDIV_SHIFT 4
#define IMX8MP_PLL14XX_PDIV_MASK  BORDOISILA_GENMASK(9,4)
#define IMX8MP_PLL14XX_SDIV_SHIFT  0
#define IMX8MP_PLL14XX_SDIV_MASK  BORDOISILA_GENMASK(2, 0)
#define IMX8MP_PLL14XX_KDIV_SHIFT 0
#define IMX8MP_PLL14XX_KDIV_MASK  BORDOISILA_GENMASK(15, 0)
 
#define LOCK_STATUS    BORDOISILA_BIT(31)
#define LOCK_SEL_MASK  BORDOISILA_BIT(29)
#define CLKE_MASK      BORDOISILA_BIT(11)
#define RST_MASK       BORDOISILA_BIT(9)
#define BYPASS_MASK    BORDOISILA_BIT(4)
 
 
struct imx_pll14xx_rate_table {
    unsigned int rate;
    unsigned int pdiv;
    unsigned int mdiv;
    unsigned int sdiv;
    unsigned int kdiv;
};
 
 
extern void imx8mp_pll_init();
 
extern unsigned long imx8mp_pll_recalc_rate(uint64_t pllbase, unsigned long parent_rate);
 
 
extern uint32_t imx8mp_pll_get_parent_rate(uint64_t pll_base);
 
#endif