#include <bordoisila_bits.h>
Include dependency graph for imx8mp_pll.h:
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Classes | |
| struct | imx_pll14xx_rate_table |
Functions | |
| void | imx8mp_pll_init () |
| unsigned long | imx8mp_pll_recalc_rate (uint64_t pllbase, unsigned long parent_rate) |
| imx8mp_pll_recalc_rate – recalculate pll rate | |
| uint32_t | imx8mp_pll_get_parent_rate (uint64_t pll_base) |
Detailed Description
BSD 2-Clause License
Copyright (c) 2022-2026, Manas Kamal Choudhury All rights reserved.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Macro Definition Documentation
◆ __IMX8MP_ANAMIX_PLL_MNIT_CTL
| #define __IMX8MP_ANAMIX_PLL_MNIT_CTL (__IMX8MP_CCM_BASE__ + 0X128) |
◆ __IMX8MP_ARM_PLL_FDIV_CTL0
| #define __IMX8MP_ARM_PLL_FDIV_CTL0 (__IMX8MP_CCM_BASE__ + 0x88) |
◆ __IMX8MP_ARM_PLL_GEN_CTRL
| #define __IMX8MP_ARM_PLL_GEN_CTRL (__IMX8MP_CCM_BASE__ + 0x84) |
◆ __IMX8MP_ARM_PLL_LOCKD_CTRL
| #define __IMX8MP_ARM_PLL_LOCKD_CTRL (__IMX8MP_CCM_BASE__ + 0x8C) |
◆ __IMX8MP_ARM_PLL_MNIT_CTRL
| #define __IMX8MP_ARM_PLL_MNIT_CTRL (__IMX8MP_CCM_BASE__ + 0x90) |
◆ __IMX8MP_AUDIO_PLL1_FDIV_CTL0
| #define __IMX8MP_AUDIO_PLL1_FDIV_CTL0 (__IMX8MP_CCM_BASE__ + 0x4) |
◆ __IMX8MP_AUDIO_PLL1_FDIV_CTL1
| #define __IMX8MP_AUDIO_PLL1_FDIV_CTL1 (__IMX8MP_CCM_BASE__ + 0x8) |
◆ __IMX8MP_AUDIO_PLL1_GEN_CTRL
| #define __IMX8MP_AUDIO_PLL1_GEN_CTRL __IMX8MP_CCM_BASE__ |
GROUP A table
◆ __IMX8MP_AUDIO_PLL1_MNIT_CTRL
| #define __IMX8MP_AUDIO_PLL1_MNIT_CTRL (__IMX8MP_CCM_BASE__ + 0x10) |
◆ __IMX8MP_AUDIO_PLL1_SSCG_CTRL
| #define __IMX8MP_AUDIO_PLL1_SSCG_CTRL (__IMX8MP_CCM_BASE__ + 0xC) |
◆ __IMX8MP_AUDIO_PLL2_FDIV_CTL0
| #define __IMX8MP_AUDIO_PLL2_FDIV_CTL0 (__IMX8MP_CCM_BASE__ + 0x18) |
◆ __IMX8MP_AUDIO_PLL2_FDIV_CTL1
| #define __IMX8MP_AUDIO_PLL2_FDIV_CTL1 (__IMX8MP_CCM_BASE__ + 0x1C) |
◆ __IMX8MP_AUDIO_PLL2_GEN_CTRL
| #define __IMX8MP_AUDIO_PLL2_GEN_CTRL (__IMX8MP_CCM_BASE__ + 0x14) |
◆ __IMX8MP_AUDIO_PLL2_MNIT_CTRL
| #define __IMX8MP_AUDIO_PLL2_MNIT_CTRL (__IMX8MP_CCM_BASE__ + 0x24) |
◆ __IMX8MP_AUDIO_PLL2_SSCG_CTRL
| #define __IMX8MP_AUDIO_PLL2_SSCG_CTRL (__IMX8MP_CCM_BASE__ + 0x20) |
◆ __IMX8MP_CCM_ANALOG_DIGPROG
| #define __IMX8MP_CCM_ANALOG_DIGPROG 0x800 |
◆ __IMX8MP_CCM_BASE__
| #define __IMX8MP_CCM_BASE__ 0x30360000 |
This file is all about PLL interface, which is used to change or modify PLL clock source from CCM module, by default, values are set according to the suitable environment so directly PLL can be used on target registers
◆ __IMX8MP_DRAM_PLL_FDIV_CTL0
| #define __IMX8MP_DRAM_PLL_FDIV_CTL0 (__IMX8MP_CCM_BASE__ + 0x54) |
◆ __IMX8MP_DRAM_PLL_FDIV_CTL1
| #define __IMX8MP_DRAM_PLL_FDIV_CTL1 (__IMX8MP_CCM_BASE__ + 0x58) |
◆ __IMX8MP_DRAM_PLL_GEN_CTRL
| #define __IMX8MP_DRAM_PLL_GEN_CTRL (__IMX8MP_CCM_BASE__ + 0x50) |
◆ __IMX8MP_DRAM_PLL_MNIT_CTRL
| #define __IMX8MP_DRAM_PLL_MNIT_CTRL (__IMX8MP_CCM_BASE__ + 0x60) |
◆ __IMX8MP_DRAM_PLL_SSCG_CTRL
| #define __IMX8MP_DRAM_PLL_SSCG_CTRL (__IMX8MP_CCM_BASE__ + 0x5C) |
◆ __IMX8MP_GPU_PLL_FDIV_CTL0
| #define __IMX8MP_GPU_PLL_FDIV_CTL0 (__IMX8MP_CCM_BASE__ + 0x68) |
◆ __IMX8MP_GPU_PLL_GEN_CTRL
| #define __IMX8MP_GPU_PLL_GEN_CTRL (__IMX8MP_CCM_BASE__ + 0x64) |
◆ __IMX8MP_GPU_PLL_LOCKD_CTRL
| #define __IMX8MP_GPU_PLL_LOCKD_CTRL (__IMX8MP_CCM_BASE__ + 0x6C) |
◆ __IMX8MP_GPU_PLL_MNIT_CTRL
| #define __IMX8MP_GPU_PLL_MNIT_CTRL (__IMX8MP_CCM_BASE__ + 0x70) |
◆ __IMX8MP_OSC_MISC_CFG
| #define __IMX8MP_OSC_MISC_CFG (__IMX8MP_CCM_BASE__ + 0x124) |
◆ __IMX8MP_SYS_PLL1_FDIV_CTL0
| #define __IMX8MP_SYS_PLL1_FDIV_CTL0 (__IMX8MP_CCM_BASE__ + 0x98) |
◆ __IMX8MP_SYS_PLL1_GEN_CTRL
| #define __IMX8MP_SYS_PLL1_GEN_CTRL (__IMX8MP_CCM_BASE__ + 0x94) |
◆ __IMX8MP_SYS_PLL1_LOCKD_CTRL
| #define __IMX8MP_SYS_PLL1_LOCKD_CTRL (__IMX8MP_CCM_BASE__ + 0x9C) |
◆ __IMX8MP_SYS_PLL1_MNIT_CTRL
| #define __IMX8MP_SYS_PLL1_MNIT_CTRL (__IMX8MP_CCM_BASE__ + 0x100) |
◆ __IMX8MP_SYS_PLL2_FDIV_CTL0
| #define __IMX8MP_SYS_PLL2_FDIV_CTL0 (__IMX8MP_CCM_BASE__ + 0x108) |
◆ __IMX8MP_SYS_PLL2_GEN_CTRL
| #define __IMX8MP_SYS_PLL2_GEN_CTRL (__IMX8MP_CCM_BASE__ + 0x104) |
◆ __IMX8MP_SYS_PLL2_LOCKD_CTRL
| #define __IMX8MP_SYS_PLL2_LOCKD_CTRL (__IMX8MP_CCM_BASE__ + 0x10C) |
◆ __IMX8MP_SYS_PLL2_MNIT_CTRL
| #define __IMX8MP_SYS_PLL2_MNIT_CTRL (__IMX8MP_CCM_BASE__ + 0x110) |
◆ __IMX8MP_SYS_PLL3_FDIV_CTL0
| #define __IMX8MP_SYS_PLL3_FDIV_CTL0 (__IMX8MP_CCM_BASE__ + 0x118) |
◆ __IMX8MP_SYS_PLL3_GEN_CTRL
| #define __IMX8MP_SYS_PLL3_GEN_CTRL (__IMX8MP_CCM_BASE__ + 0x114) |
◆ __IMX8MP_SYS_PLL3_LOCKD_CTRL
| #define __IMX8MP_SYS_PLL3_LOCKD_CTRL (__IMX8MP_CCM_BASE__ + 0x11C) |
◆ __IMX8MP_SYS_PLL3_MNIT_CTRL
| #define __IMX8MP_SYS_PLL3_MNIT_CTRL (__IMX8MP_CCM_BASE__ + 0x120) |
◆ __IMX8MP_VIDEO_PLL1_FDIV_CTL0
| #define __IMX8MP_VIDEO_PLL1_FDIV_CTL0 (__IMX8MP_CCM_BASE__ + 0x2C) |
◆ __IMX8MP_VIDEO_PLL1_FDIV_CTL1
| #define __IMX8MP_VIDEO_PLL1_FDIV_CTL1 (__IMX8MP_CCM_BASE__ + 0x30) |
◆ __IMX8MP_VIDEO_PLL1_GEN_CTRL
| #define __IMX8MP_VIDEO_PLL1_GEN_CTRL (__IMX8MP_CCM_BASE__ + 0x28) |
◆ __IMX8MP_VIDEO_PLL1_MNIT_CTRL
| #define __IMX8MP_VIDEO_PLL1_MNIT_CTRL (__IMX8MP_CCM_BASE__ + 0x38) |
◆ __IMX8MP_VIDEO_PLL1_SSCG_CTRL
| #define __IMX8MP_VIDEO_PLL1_SSCG_CTRL (__IMX8MP_CCM_BASE__ + 0x34) |
◆ __IMX8MP_VPU_PLL_FDIV_CTL0
| #define __IMX8MP_VPU_PLL_FDIV_CTL0 (__IMX8MP_CCM_BASE__ + 0x78) |
◆ __IMX8MP_VPU_PLL_GEN_CTRL
| #define __IMX8MP_VPU_PLL_GEN_CTRL (__IMX8MP_CCM_BASE__ + 0x74) |
◆ __IMX8MP_VPU_PLL_LOCKD_CTRL
| #define __IMX8MP_VPU_PLL_LOCKD_CTRL (__IMX8MP_CCM_BASE__ + 0x7C) |
◆ __IMX8MP_VPU_PLL_MNIT_CTRL
| #define __IMX8MP_VPU_PLL_MNIT_CTRL (__IMX8MP_CCM_BASE__ + 0x80) |
◆ BYPASS_MASK
| #define BYPASS_MASK BORDOISILA_BIT(4) |
◆ CLKE_MASK
| #define CLKE_MASK BORDOISILA_BIT(11) |
◆ IMX8MP_PLL14XX_KDIV_MASK
| #define IMX8MP_PLL14XX_KDIV_MASK BORDOISILA_GENMASK(15, 0) |
◆ IMX8MP_PLL14XX_KDIV_SHIFT
| #define IMX8MP_PLL14XX_KDIV_SHIFT 0 |
◆ IMX8MP_PLL14XX_MDIV_MASK
| #define IMX8MP_PLL14XX_MDIV_MASK BORDOISILA_GENMASK(21,12) |
◆ IMX8MP_PLL14XX_MDIV_SHIFT
| #define IMX8MP_PLL14XX_MDIV_SHIFT 12 |
imx8mp uses PLL14xx modern analog hardware ip block
◆ IMX8MP_PLL14XX_PDIV_MASK
| #define IMX8MP_PLL14XX_PDIV_MASK BORDOISILA_GENMASK(9,4) |
◆ IMX8MP_PLL14XX_PDIV_SHIFT
| #define IMX8MP_PLL14XX_PDIV_SHIFT 4 |
◆ IMX8MP_PLL14XX_SDIV_MASK
| #define IMX8MP_PLL14XX_SDIV_MASK BORDOISILA_GENMASK(2, 0) |
◆ IMX8MP_PLL14XX_SDIV_SHIFT
| #define IMX8MP_PLL14XX_SDIV_SHIFT 0 |
◆ LOCK_SEL_MASK
| #define LOCK_SEL_MASK BORDOISILA_BIT(29) |
◆ LOCK_STATUS
| #define LOCK_STATUS BORDOISILA_BIT(31) |
◆ RST_MASK
| #define RST_MASK BORDOISILA_BIT(9) |
Function Documentation
◆ imx8mp_pll_get_parent_rate()
◆ imx8mp_pll_init()
|
extern |
◆ imx8mp_pll_recalc_rate()
|
extern |
imx8mp_pll_recalc_rate – recalculate pll rate
- Parameters
-
pllbase – pll base source or entry parent_rate – clock rate, if the target root is high powered device, it uses osc_24m sel otherwise osc_32k is used for low powered device
