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imx8mp_uart.h
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1
32#ifndef __IMX8MP_UART_H__
33#define __IMX8MP_UART_H__
34
35
36#include <stdint.h>
42#define IMX8MP_UART1_BASE_ADDRESS 0x30860000
43#define IMX8MP_UART3_BASE_ADDRESS 0x30880000
44#define IMX8MP_UART2_BASE_ADDRESS 0x30890000
45
46
47#define IMX8MP_UART_URXD(base) base /* UART Receiver Register (URDX) -- 32 bit width*/
48#define IMX8MP_UART_UTXD(base) (base + 0x40)
49#define IMX8MP_UART_UCR1(base) (base + 0x80)
50#define IMX8MP_UART_UCR2(base) (base + 0x84)
51#define IMX8MP_UART_UCR3(base) (base + 0x88)
52#define IMX8MP_UART_UCR4(base) (base + 0x8C)
53#define IMX8MP_UART_UFCR(base) (base + 0x90)
54#define IMX8MP_UART_USR1(base) (base + 0x94)
55#define IMX8MP_UART_USR2(base) (base + 0x98)
56#define IMX8MP_UART_UESC(base) (base + 0x9C)
57#define IMX8MP_UART_UTIM(base) (base + 0xA0)
58#define IMX8MP_UART_UBIR(base) (base + 0xA4)
59#define IMX8MP_UART_UBMR(base) (base + 0xA8)
60#define IMX8MP_UART_UBRC(base) (base + 0xAC)
61#define IMX8MP_UART_ONEMS(base) (base + 0xB0)
62#define IMX8MP_UART_UTS(base) (base + 0xB4)
63#define IMX8MP_UART_UMCR(base) (base + 0xB8)
65 /* ── UCR1 bits ────────────────────────────────────────────────────────── */
66#define UCR1_UARTEN (1u << 0) /* UART enable */
67#define UCR1_DOZE (1u << 1) /* Doze mode enable */
68#define UCR1_ATDMAEN (1u << 2) /* Aging DMA timer enable */
69#define UCR1_TXDMAEN (1u << 3) /* Transmitter DMA enable */
70#define UCR1_SNDBRK (1u << 4) /* Send BREAK */
71#define UCR1_RTSDEN (1u << 5) /* RTS delta interrupt enable */
72#define UCR1_TXMPTYEN (1u << 6) /* Tx FIFO empty interrupt enable */
73#define UCR1_IREN (1u << 7) /* IrDA enable */
74#define UCR1_RXDMAEN (1u << 8) /* Receiver DMA enable */
75#define UCR1_RRDYEN (1u << 9) /* Receiver ready interrupt enable */
76#define UCR1_ICD_MASK (3u << 10) /* Idle condition detect mask */
77#define UCR1_IDEN (1u << 12) /* Idle condition detected IRQ enable */
78#define UCR1_TRDYEN (1u << 13) /* Transmitter ready interrupt enable */
79#define UCR1_ADBR (1u << 14) /* Automatic detection of baud rate */
80#define UCR1_ADEN (1u << 15) /* Auto baud rate detection IRQ en */
81
82/* ── UCR2 bits ────────────────────────────────────────────────────────── */
83#define UCR2_SRST (1u << 0) /* SW reset (active low, write 1 to clear) */
84#define UCR2_RXEN (1u << 1) /* Receiver enable */
85#define UCR2_TXEN (1u << 2) /* Transmitter enable */
86#define UCR2_ATEN (1u << 3) /* Aging timer enable */
87#define UCR2_RTSEN (1u << 4) /* RTS interrupt enable */
88#define UCR2_WS (1u << 5) /* Word size: 0=7-bit, 1=8-bit */
89#define UCR2_STPB (1u << 6) /* Stop bits: 0=1 stop, 1=2 stop */
90#define UCR2_PROE (1u << 7) /* Parity odd enable */
91#define UCR2_PREN (1u << 8) /* Parity enable */
92#define UCR2_RTEC_MASK (3u << 9) /* Request-to-send edge control mask */
93#define UCR2_ESCEN (1u << 11) /* Escape sequence interrupt enable */
94#define UCR2_CTS (1u << 12) /* CTS status */
95#define UCR2_CTSC (1u << 13) /* CTS pin controlled by receiver */
96#define UCR2_IRTS (1u << 14) /* Ignore RTS pin */
97#define UCR2_ESCI (1u << 15) /* Escape sequence interrupt enable */
98
99/* ── UCR3 bits ────────────────────────────────────────────────────────── */
100#define UCR3_RXDMUXSEL (1u << 2) /* Mux RXD: must be set on i.MX8M */
101
102/* ── UCR4 bits ────────────────────────────────────────────────────────── */
103#define UCR4_DREN (1u << 0) /* Receive data ready interrupt enable */
104#define UCR4_OREN (1u << 1) /* Receiver overrun interrupt enable */
105#define UCR4_BKEN (1u << 2) /* BREAK condition interrupt enable */
106#define UCR4_TCEN (1u << 3) /* Transmit complete interrupt enable */
107#define UCR4_INVR (1u << 9) /* Inverted infrared reception */
108
109/* ── UFCR bits ────────────────────────────────────────────────────────── */
110#define UFCR_RXTL_SHIFT 0 /* RX trigger level [5:0] */
111#define UFCR_RXTL_MASK (0x3Fu)
112#define UFCR_DCEDTE (1u << 6) /* DCE/DTE mode select */
113#define UFCR_RFDIV_SHIFT 7 /* Reference frequency divider [9:7] */
114#define UFCR_RFDIV_MASK (7u << 7)
115#define UFCR_TXTL_SHIFT 10 /* TX trigger level [15:10] */
116#define UFCR_TXTL_MASK (0x3Fu << 10)
117
118/* UFCR_RFDIV encoding: 000=6, 001=5, 010=4, 011=3, 100=2, 101=1, 110=7 */
119#define UFCR_RFDIV(n) (((n) & 7u) << UFCR_RFDIV_SHIFT)
120
121/* ── USR1 bits ────────────────────────────────────────────────────────── */
122#define USR1_AWAKE (1u << 4) /* Awake interrupt flag */
123#define USR1_AIRINT (1u << 5) /* Async IR interrupt flag */
124#define USR1_RXDS (1u << 6) /* Receiver idle condition */
125#define USR1_DTRD (1u << 7) /* DTR delta */
126#define USR1_AGTIM (1u << 8) /* Aging timer interrupt flag */
127#define USR1_RRDY (1u << 9) /* Receiver ready */
128#define USR1_FRAMERR (1u << 10) /* Frame error in RX FIFO */
129#define USR1_ESCF (1u << 11) /* Escape sequence flag */
130#define USR1_RTSD (1u << 12) /* RTS delta */
131#define USR1_TRDY (1u << 13) /* Transmitter ready */
132#define USR1_RTSS (1u << 14) /* RTS pin status */
133#define USR1_PARITYERR (1u << 15) /* Parity error */
134
135/* ── USR2 bits ────────────────────────────────────────────────────────── */
136#define USR2_RDR (1u << 0) /* Receive data ready */
137#define USR2_ORE (1u << 1) /* Overrun error */
138#define USR2_BRCD (1u << 2) /* BREAK condition detected */
139#define USR2_TXDC (1u << 3) /* Transmitter complete (FIFO + SR empty) */
140#define USR2_RTSF (1u << 4) /* RTS edge triggered interrupt flag */
141#define USR2_DCDIN (1u << 5) /* Data carrier detect */
142#define USR2_DCDDELT (1u << 6) /* Data carrier detect delta */
143#define USR2_WAKE (1u << 7) /* Wake */
144#define USR2_IRINT (1u << 8) /* Serial infrared interrupt flag */
145#define USR2_RIIN (1u << 9) /* Ring indicator input */
146#define USR2_RIDELT (1u << 10) /* Ring indicator delta */
147#define USR2_ACST (1u << 11) /* Auto-baud counter stopped */
148#define USR2_IDLE (1u << 12) /* Idle condition */
149#define USR2_DTRF (1u << 13) /* DTR edge triggered interrupt flag */
150#define USR2_TXFE (1u << 14) /* Transmit FIFO empty */
151#define USR2_ADET (1u << 15) /* Automatic baud-rate detect complete */
152
153/* ── UTS bits ─────────────────────────────────────────────────────────── */
154#define UTS_SOFTRST (1u << 0) /* Software reset */
155#define UTS_RXFULL (1u << 3) /* RX FIFO full */
156#define UTS_TXFULL (1u << 4) /* TX FIFO full */
157#define UTS_RXEMPTY (1u << 5) /* RX FIFO empty */
158#define UTS_TXEMPTY (1u << 6) /* TX FIFO empty */
159#define UTS_RXDBG (1u << 9) /* RX FIFO debug mode */
160#define UTS_LOOPIR (1u << 10) /* Loop IR test */
161#define UTS_DBGEN (1u << 11) /* Debug enable */
162#define UTS_LOOP (1u << 12) /* Loop TX->RX (loopback test) */
163#define UTS_FRCPERR (1u << 13) /* Force parity error */
164
165/* ── URXD bits ────────────────────────────────────────────────────────── */
166#define URXD_RX_DATA 0x00FFu /* Received character [7:0] */
167#define URXD_PRERR (1u << 10) /* Parity error */
168#define URXD_BRK (1u << 11) /* BREAK detected */
169#define URXD_FRMERR (1u << 12) /* Frame error */
170#define URXD_OVRRUN (1u << 13) /* Overrun error */
171#define URXD_ERR (1u << 14) /* Any error bit set */
172#define URXD_CHARRDY (1u << 15) /* Character ready in FIFO */
173
174
175#define IMX_PARITY_NONE 0
176#define IMX_PARITY_EVEN 1
177#define IMX_PARITY_ODD 2
178
179
184extern void au_imx8mp_uart_putc(char c);
189extern void au_imx8mp_uart_puts(const char* s);
190
191
196extern int au_imx8mp_uart_getc();
197
198extern void au_imx8np_uart_initialize(uint64_t base);
199
200
201#endif
uint64_t
COMPILER_DEPENDENT_UINT64 uint64_t
Definition acefiex.h:165
au_imx8mp_uart_putc
void au_imx8mp_uart_putc(char c)
imx8mp_uart_putc – put a single character on the UART
au_imx8mp_uart_getc
int au_imx8mp_uart_getc()
imx8mp_uart_getc – receive a single character from the UART
au_imx8mp_uart_puts
void au_imx8mp_uart_puts(const char *s)
imx8mp_uart_puts – put a collection of character on the UART
au_imx8np_uart_initialize
void au_imx8np_uart_initialize(uint64_t base)
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