imx8mp_uart.h File Reference

#include <stdint.h>

Include dependency graph for imx8mp_uart.h:

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros
#define	IMX8MP_UART1_BASE_ADDRESS   0x30860000
#define	IMX8MP_UART3_BASE_ADDRESS   0x30880000
#define	IMX8MP_UART2_BASE_ADDRESS   0x30890000
#define	IMX8MP_UART_URXD(base)   base /* UART Receiver Register (URDX) -- 32 bit width*/
#define	IMX8MP_UART_UTXD(base)   (base + 0x40) /** UART Transmitter Register (UTXD) -- 32 bit width */
#define	IMX8MP_UART_UCR1(base)   (base + 0x80) /** UART1 Control register */
#define	IMX8MP_UART_UCR2(base)   (base + 0x84)
#define	IMX8MP_UART_UCR3(base)   (base + 0x88)
#define	IMX8MP_UART_UCR4(base)   (base + 0x8C)
#define	IMX8MP_UART_UFCR(base)   (base + 0x90) /** UART1 FIFO Control Register **/
#define	IMX8MP_UART_USR1(base)   (base + 0x94) /** UART1 Status Regster 1 **/
#define	IMX8MP_UART_USR2(base)   (base + 0x98) /** UART1 Status Register 2 **/
#define	IMX8MP_UART_UESC(base)   (base + 0x9C) /** UART1 Escape Character Register **/
#define	IMX8MP_UART_UTIM(base)   (base + 0xA0) /** UART1 Escape Timer Register **/
#define	IMX8MP_UART_UBIR(base)   (base + 0xA4) /** UART1 BRM Incremental Register **/
#define	IMX8MP_UART_UBMR(base)   (base + 0xA8) /** UART1 BRM Modulator Register **/
#define	IMX8MP_UART_UBRC(base)   (base + 0xAC) /** UART1 Baude Rate Count Register **/
#define	IMX8MP_UART_ONEMS(base)   (base + 0xB0) /** UART1 One Millisecond Register **/
#define	IMX8MP_UART_UTS(base)   (base + 0xB4) /** UART1 Test Register **/
#define	IMX8MP_UART_UMCR(base)   (base + 0xB8) /** UART1 RS-485 Mode Control Register **/
#define	UCR1_UARTEN   (1u << 0) /* UART enable */
#define	UCR1_DOZE   (1u << 1) /* Doze mode enable */
#define	UCR1_ATDMAEN   (1u << 2) /* Aging DMA timer enable */
#define	UCR1_TXDMAEN   (1u << 3) /* Transmitter DMA enable */
#define	UCR1_SNDBRK   (1u << 4) /* Send BREAK */
#define	UCR1_RTSDEN   (1u << 5) /* RTS delta interrupt enable */
#define	UCR1_TXMPTYEN   (1u << 6) /* Tx FIFO empty interrupt enable */
#define	UCR1_IREN   (1u << 7) /* IrDA enable */
#define	UCR1_RXDMAEN   (1u << 8) /* Receiver DMA enable */
#define	UCR1_RRDYEN   (1u << 9) /* Receiver ready interrupt enable */
#define	UCR1_ICD_MASK   (3u << 10) /* Idle condition detect mask */
#define	UCR1_IDEN   (1u << 12) /* Idle condition detected IRQ enable */
#define	UCR1_TRDYEN   (1u << 13) /* Transmitter ready interrupt enable */
#define	UCR1_ADBR   (1u << 14) /* Automatic detection of baud rate */
#define	UCR1_ADEN   (1u << 15) /* Auto baud rate detection IRQ en */
#define	UCR2_SRST   (1u << 0) /* SW reset (active low, write 1 to clear) */
#define	UCR2_RXEN   (1u << 1) /* Receiver enable */
#define	UCR2_TXEN   (1u << 2) /* Transmitter enable */
#define	UCR2_ATEN   (1u << 3) /* Aging timer enable */
#define	UCR2_RTSEN   (1u << 4) /* RTS interrupt enable */
#define	UCR2_WS   (1u << 5) /* Word size: 0=7-bit, 1=8-bit */
#define	UCR2_STPB   (1u << 6) /* Stop bits: 0=1 stop, 1=2 stop */
#define	UCR2_PROE   (1u << 7) /* Parity odd enable */
#define	UCR2_PREN   (1u << 8) /* Parity enable */
#define	UCR2_RTEC_MASK   (3u << 9) /* Request-to-send edge control mask */
#define	UCR2_ESCEN   (1u << 11) /* Escape sequence interrupt enable */
#define	UCR2_CTS   (1u << 12) /* CTS status */
#define	UCR2_CTSC   (1u << 13) /* CTS pin controlled by receiver */
#define	UCR2_IRTS   (1u << 14) /* Ignore RTS pin */
#define	UCR2_ESCI   (1u << 15) /* Escape sequence interrupt enable */
#define	UCR3_RXDMUXSEL   (1u << 2) /* Mux RXD: must be set on i.MX8M */
#define	UCR4_DREN   (1u << 0) /* Receive data ready interrupt enable */
#define	UCR4_OREN   (1u << 1) /* Receiver overrun interrupt enable */
#define	UCR4_BKEN   (1u << 2) /* BREAK condition interrupt enable */
#define	UCR4_TCEN   (1u << 3) /* Transmit complete interrupt enable */
#define	UCR4_INVR   (1u << 9) /* Inverted infrared reception */
#define	UFCR_RXTL_SHIFT   0 /* RX trigger level [5:0] */
#define	UFCR_RXTL_MASK   (0x3Fu)
#define	UFCR_DCEDTE   (1u << 6) /* DCE/DTE mode select */
#define	UFCR_RFDIV_SHIFT   7 /* Reference frequency divider [9:7] */
#define	UFCR_RFDIV_MASK   (7u << 7)
#define	UFCR_TXTL_SHIFT   10 /* TX trigger level [15:10] */
#define	UFCR_TXTL_MASK   (0x3Fu << 10)
#define	UFCR_RFDIV(n)   (((n) & 7u) << UFCR_RFDIV_SHIFT)
#define	USR1_AWAKE   (1u << 4) /* Awake interrupt flag */
#define	USR1_AIRINT   (1u << 5) /* Async IR interrupt flag */
#define	USR1_RXDS   (1u << 6) /* Receiver idle condition */
#define	USR1_DTRD   (1u << 7) /* DTR delta */
#define	USR1_AGTIM   (1u << 8) /* Aging timer interrupt flag */
#define	USR1_RRDY   (1u << 9) /* Receiver ready */
#define	USR1_FRAMERR   (1u << 10) /* Frame error in RX FIFO */
#define	USR1_ESCF   (1u << 11) /* Escape sequence flag */
#define	USR1_RTSD   (1u << 12) /* RTS delta */
#define	USR1_TRDY   (1u << 13) /* Transmitter ready */
#define	USR1_RTSS   (1u << 14) /* RTS pin status */
#define	USR1_PARITYERR   (1u << 15) /* Parity error */
#define	USR2_RDR   (1u << 0) /* Receive data ready */
#define	USR2_ORE   (1u << 1) /* Overrun error */
#define	USR2_BRCD   (1u << 2) /* BREAK condition detected */
#define	USR2_TXDC   (1u << 3) /* Transmitter complete (FIFO + SR empty) */
#define	USR2_RTSF   (1u << 4) /* RTS edge triggered interrupt flag */
#define	USR2_DCDIN   (1u << 5) /* Data carrier detect */
#define	USR2_DCDDELT   (1u << 6) /* Data carrier detect delta */
#define	USR2_WAKE   (1u << 7) /* Wake */
#define	USR2_IRINT   (1u << 8) /* Serial infrared interrupt flag */
#define	USR2_RIIN   (1u << 9) /* Ring indicator input */
#define	USR2_RIDELT   (1u << 10) /* Ring indicator delta */
#define	USR2_ACST   (1u << 11) /* Auto-baud counter stopped */
#define	USR2_IDLE   (1u << 12) /* Idle condition */
#define	USR2_DTRF   (1u << 13) /* DTR edge triggered interrupt flag */
#define	USR2_TXFE   (1u << 14) /* Transmit FIFO empty */
#define	USR2_ADET   (1u << 15) /* Automatic baud-rate detect complete */
#define	UTS_SOFTRST   (1u << 0) /* Software reset */
#define	UTS_RXFULL   (1u << 3) /* RX FIFO full */
#define	UTS_TXFULL   (1u << 4) /* TX FIFO full */
#define	UTS_RXEMPTY   (1u << 5) /* RX FIFO empty */
#define	UTS_TXEMPTY   (1u << 6) /* TX FIFO empty */
#define	UTS_RXDBG   (1u << 9) /* RX FIFO debug mode */
#define	UTS_LOOPIR   (1u << 10) /* Loop IR test */
#define	UTS_DBGEN   (1u << 11) /* Debug enable */
#define	UTS_LOOP   (1u << 12) /* Loop TX->RX (loopback test) */
#define	UTS_FRCPERR   (1u << 13) /* Force parity error */
#define	URXD_RX_DATA   0x00FFu /* Received character [7:0] */
#define	URXD_PRERR   (1u << 10) /* Parity error */
#define	URXD_BRK   (1u << 11) /* BREAK detected */
#define	URXD_FRMERR   (1u << 12) /* Frame error */
#define	URXD_OVRRUN   (1u << 13) /* Overrun error */
#define	URXD_ERR   (1u << 14) /* Any error bit set */
#define	URXD_CHARRDY   (1u << 15) /* Character ready in FIFO */
#define	IMX_PARITY_NONE   0
#define	IMX_PARITY_EVEN   1
#define	IMX_PARITY_ODD   2

Functions
void	au_imx8mp_uart_putc (char c)
	imx8mp_uart_putc – put a single character on the UART
void	au_imx8mp_uart_puts (const char *s)
	imx8mp_uart_puts – put a collection of character on the UART
int	au_imx8mp_uart_getc ()
	imx8mp_uart_getc – receive a single character from the UART
void	au_imx8np_uart_initialize (uint64_t base)

Detailed Description

BSD 2-Clause License

Copyright (c) 2022-2025, Manas Kamal Choudhury All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Macro Definition Documentation

IMX8MP_UART1_BASE_ADDRESS

#define IMX8MP_UART1_BASE_ADDRESS   0x30860000

UART Register Map for NXP.IMX8MP SoC family, can be found in iMX8MPRM – Processor Reference Manual

IMX8MP_UART2_BASE_ADDRESS

#define IMX8MP_UART2_BASE_ADDRESS   0x30890000

IMX8MP_UART3_BASE_ADDRESS

#define IMX8MP_UART3_BASE_ADDRESS   0x30880000

IMX8MP_UART_ONEMS

#define IMX8MP_UART_ONEMS

(

base

)

(base + 0xB0) /** UART1 One Millisecond Register **/

IMX8MP_UART_UBIR

#define IMX8MP_UART_UBIR

(

base

)

(base + 0xA4) /** UART1 BRM Incremental Register **/

IMX8MP_UART_UBMR

#define IMX8MP_UART_UBMR

(

base

)

(base + 0xA8) /** UART1 BRM Modulator Register **/

IMX8MP_UART_UBRC

#define IMX8MP_UART_UBRC

(

base

)

(base + 0xAC) /** UART1 Baude Rate Count Register **/

IMX8MP_UART_UCR1

#define IMX8MP_UART_UCR1

(

base

)

(base + 0x80) /** UART1 Control register */

IMX8MP_UART_UCR2

#define IMX8MP_UART_UCR2

(

base

)

(base + 0x84)

IMX8MP_UART_UCR3

#define IMX8MP_UART_UCR3

(

base

)

(base + 0x88)

IMX8MP_UART_UCR4

#define IMX8MP_UART_UCR4

(

base

)

(base + 0x8C)

IMX8MP_UART_UESC

#define IMX8MP_UART_UESC

(

base

)

(base + 0x9C) /** UART1 Escape Character Register **/

IMX8MP_UART_UFCR

#define IMX8MP_UART_UFCR

(

base

)

(base + 0x90) /** UART1 FIFO Control Register **/

IMX8MP_UART_UMCR

#define IMX8MP_UART_UMCR

(

base

)

(base + 0xB8) /** UART1 RS-485 Mode Control Register **/

IMX8MP_UART_URXD

#define IMX8MP_UART_URXD

(

base

)

base /* UART Receiver Register (URDX) -- 32 bit width*/

IMX8MP_UART_USR1

#define IMX8MP_UART_USR1

(

base

)

(base + 0x94) /** UART1 Status Regster 1 **/

IMX8MP_UART_USR2

#define IMX8MP_UART_USR2

(

base

)

(base + 0x98) /** UART1 Status Register 2 **/

IMX8MP_UART_UTIM

#define IMX8MP_UART_UTIM

(

base

)

(base + 0xA0) /** UART1 Escape Timer Register **/

IMX8MP_UART_UTS

#define IMX8MP_UART_UTS

(

base

)

(base + 0xB4) /** UART1 Test Register **/

IMX8MP_UART_UTXD

#define IMX8MP_UART_UTXD

(

base

)

(base + 0x40) /** UART Transmitter Register (UTXD) -- 32 bit width */

IMX_PARITY_EVEN

#define IMX_PARITY_EVEN   1

IMX_PARITY_NONE

#define IMX_PARITY_NONE   0

IMX_PARITY_ODD

#define IMX_PARITY_ODD   2

UCR1_ADBR

#define UCR1_ADBR   (1u << 14) /* Automatic detection of baud rate */

UCR1_ADEN

#define UCR1_ADEN   (1u << 15) /* Auto baud rate detection IRQ en */

UCR1_ATDMAEN

#define UCR1_ATDMAEN   (1u << 2) /* Aging DMA timer enable */

UCR1_DOZE

#define UCR1_DOZE   (1u << 1) /* Doze mode enable */

UCR1_ICD_MASK

#define UCR1_ICD_MASK   (3u << 10) /* Idle condition detect mask */

UCR1_IDEN

#define UCR1_IDEN   (1u << 12) /* Idle condition detected IRQ enable */

UCR1_IREN

#define UCR1_IREN   (1u << 7) /* IrDA enable */

UCR1_RRDYEN

#define UCR1_RRDYEN   (1u << 9) /* Receiver ready interrupt enable */

UCR1_RTSDEN

#define UCR1_RTSDEN   (1u << 5) /* RTS delta interrupt enable */

UCR1_RXDMAEN

#define UCR1_RXDMAEN   (1u << 8) /* Receiver DMA enable */

UCR1_SNDBRK

#define UCR1_SNDBRK   (1u << 4) /* Send BREAK */

UCR1_TRDYEN

#define UCR1_TRDYEN   (1u << 13) /* Transmitter ready interrupt enable */

UCR1_TXDMAEN

#define UCR1_TXDMAEN   (1u << 3) /* Transmitter DMA enable */

UCR1_TXMPTYEN

#define UCR1_TXMPTYEN   (1u << 6) /* Tx FIFO empty interrupt enable */

UCR1_UARTEN

#define UCR1_UARTEN   (1u << 0) /* UART enable */

UCR2_ATEN

#define UCR2_ATEN   (1u << 3) /* Aging timer enable */

UCR2_CTS

#define UCR2_CTS   (1u << 12) /* CTS status */

UCR2_CTSC

#define UCR2_CTSC   (1u << 13) /* CTS pin controlled by receiver */

UCR2_ESCEN

#define UCR2_ESCEN   (1u << 11) /* Escape sequence interrupt enable */

UCR2_ESCI

#define UCR2_ESCI   (1u << 15) /* Escape sequence interrupt enable */

UCR2_IRTS

#define UCR2_IRTS   (1u << 14) /* Ignore RTS pin */

UCR2_PREN

#define UCR2_PREN   (1u << 8) /* Parity enable */

UCR2_PROE

#define UCR2_PROE   (1u << 7) /* Parity odd enable */

UCR2_RTEC_MASK

#define UCR2_RTEC_MASK   (3u << 9) /* Request-to-send edge control mask */

UCR2_RTSEN

#define UCR2_RTSEN   (1u << 4) /* RTS interrupt enable */

UCR2_RXEN

#define UCR2_RXEN   (1u << 1) /* Receiver enable */

UCR2_SRST

#define UCR2_SRST   (1u << 0) /* SW reset (active low, write 1 to clear) */

UCR2_STPB

#define UCR2_STPB   (1u << 6) /* Stop bits: 0=1 stop, 1=2 stop */

UCR2_TXEN

#define UCR2_TXEN   (1u << 2) /* Transmitter enable */

UCR2_WS

#define UCR2_WS   (1u << 5) /* Word size: 0=7-bit, 1=8-bit */

UCR3_RXDMUXSEL

#define UCR3_RXDMUXSEL   (1u << 2) /* Mux RXD: must be set on i.MX8M */

UCR4_BKEN

#define UCR4_BKEN   (1u << 2) /* BREAK condition interrupt enable */

UCR4_DREN

#define UCR4_DREN   (1u << 0) /* Receive data ready interrupt enable */

UCR4_INVR

#define UCR4_INVR   (1u << 9) /* Inverted infrared reception */

UCR4_OREN

#define UCR4_OREN   (1u << 1) /* Receiver overrun interrupt enable */

UCR4_TCEN

#define UCR4_TCEN   (1u << 3) /* Transmit complete interrupt enable */

UFCR_DCEDTE

#define UFCR_DCEDTE   (1u << 6) /* DCE/DTE mode select */

UFCR_RFDIV

#define UFCR_RFDIV

(

n

)

(((n) & 7u) << UFCR_RFDIV_SHIFT)

UFCR_RFDIV_MASK

#define UFCR_RFDIV_MASK   (7u << 7)

UFCR_RFDIV_SHIFT

#define UFCR_RFDIV_SHIFT   7 /* Reference frequency divider [9:7] */

UFCR_RXTL_MASK

#define UFCR_RXTL_MASK   (0x3Fu)

UFCR_RXTL_SHIFT

#define UFCR_RXTL_SHIFT   0 /* RX trigger level [5:0] */

UFCR_TXTL_MASK

#define UFCR_TXTL_MASK   (0x3Fu << 10)

UFCR_TXTL_SHIFT

#define UFCR_TXTL_SHIFT   10 /* TX trigger level [15:10] */

URXD_BRK

#define URXD_BRK   (1u << 11) /* BREAK detected */

URXD_CHARRDY

#define URXD_CHARRDY   (1u << 15) /* Character ready in FIFO */

URXD_ERR

#define URXD_ERR   (1u << 14) /* Any error bit set */

URXD_FRMERR

#define URXD_FRMERR   (1u << 12) /* Frame error */

URXD_OVRRUN

#define URXD_OVRRUN   (1u << 13) /* Overrun error */

URXD_PRERR

#define URXD_PRERR   (1u << 10) /* Parity error */

URXD_RX_DATA

#define URXD_RX_DATA   0x00FFu /* Received character [7:0] */

USR1_AGTIM

#define USR1_AGTIM   (1u << 8) /* Aging timer interrupt flag */

USR1_AIRINT

#define USR1_AIRINT   (1u << 5) /* Async IR interrupt flag */

USR1_AWAKE

#define USR1_AWAKE   (1u << 4) /* Awake interrupt flag */

USR1_DTRD

#define USR1_DTRD   (1u << 7) /* DTR delta */

USR1_ESCF

#define USR1_ESCF   (1u << 11) /* Escape sequence flag */

USR1_FRAMERR

#define USR1_FRAMERR   (1u << 10) /* Frame error in RX FIFO */

USR1_PARITYERR

#define USR1_PARITYERR   (1u << 15) /* Parity error */

USR1_RRDY

#define USR1_RRDY   (1u << 9) /* Receiver ready */

USR1_RTSD

#define USR1_RTSD   (1u << 12) /* RTS delta */

USR1_RTSS

#define USR1_RTSS   (1u << 14) /* RTS pin status */

USR1_RXDS

#define USR1_RXDS   (1u << 6) /* Receiver idle condition */

USR1_TRDY

#define USR1_TRDY   (1u << 13) /* Transmitter ready */

USR2_ACST

#define USR2_ACST   (1u << 11) /* Auto-baud counter stopped */

USR2_ADET

#define USR2_ADET   (1u << 15) /* Automatic baud-rate detect complete */

USR2_BRCD

#define USR2_BRCD   (1u << 2) /* BREAK condition detected */

USR2_DCDDELT

#define USR2_DCDDELT   (1u << 6) /* Data carrier detect delta */

USR2_DCDIN

#define USR2_DCDIN   (1u << 5) /* Data carrier detect */

USR2_DTRF

#define USR2_DTRF   (1u << 13) /* DTR edge triggered interrupt flag */

USR2_IDLE

#define USR2_IDLE   (1u << 12) /* Idle condition */

USR2_IRINT

#define USR2_IRINT   (1u << 8) /* Serial infrared interrupt flag */

USR2_ORE

#define USR2_ORE   (1u << 1) /* Overrun error */

USR2_RDR

#define USR2_RDR   (1u << 0) /* Receive data ready */

USR2_RIDELT

#define USR2_RIDELT   (1u << 10) /* Ring indicator delta */

USR2_RIIN

#define USR2_RIIN   (1u << 9) /* Ring indicator input */

USR2_RTSF

#define USR2_RTSF   (1u << 4) /* RTS edge triggered interrupt flag */

USR2_TXDC

#define USR2_TXDC   (1u << 3) /* Transmitter complete (FIFO + SR empty) */

USR2_TXFE

#define USR2_TXFE   (1u << 14) /* Transmit FIFO empty */

USR2_WAKE

#define USR2_WAKE   (1u << 7) /* Wake */

UTS_DBGEN

#define UTS_DBGEN   (1u << 11) /* Debug enable */

UTS_FRCPERR

#define UTS_FRCPERR   (1u << 13) /* Force parity error */

UTS_LOOP

#define UTS_LOOP   (1u << 12) /* Loop TX->RX (loopback test) */

UTS_LOOPIR

#define UTS_LOOPIR   (1u << 10) /* Loop IR test */

UTS_RXDBG

#define UTS_RXDBG   (1u << 9) /* RX FIFO debug mode */

UTS_RXEMPTY

#define UTS_RXEMPTY   (1u << 5) /* RX FIFO empty */

UTS_RXFULL

#define UTS_RXFULL   (1u << 3) /* RX FIFO full */

UTS_SOFTRST

#define UTS_SOFTRST   (1u << 0) /* Software reset */

UTS_TXEMPTY

#define UTS_TXEMPTY   (1u << 6) /* TX FIFO empty */

UTS_TXFULL

#define UTS_TXFULL   (1u << 4) /* TX FIFO full */

Function Documentation

au_imx8mp_uart_getc()

int au_imx8mp_uart_getc ( )

extern

imx8mp_uart_getc – receive a single character from the UART

au_imx8mp_uart_putc()

void au_imx8mp_uart_putc ( char  c )

extern

imx8mp_uart_putc – put a single character on the UART

Parameters

c	– character to put

au_imx8mp_uart_puts()

void au_imx8mp_uart_puts ( const char *  s )

extern

imx8mp_uart_puts – put a collection of character on the UART

Parameters

s	– String to send

au_imx8np_uart_initialize()

void au_imx8np_uart_initialize ( uint64_t  base )

extern