EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES Struct Reference

#include <Acpi62.h>

Public Attributes
UINT32	TotalCacheLevels:4
UINT32	CacheLevel:4
UINT32	CacheAssociativity:4
UINT32	WritePolicy:4
UINT32	CacheLineSize:16

Detailed Description

Memory Side Cache Information Structure cache attributes

Member Data Documentation

CacheAssociativity

UINT32 EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES::CacheAssociativity

CacheLevel

UINT32 EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES::CacheLevel

CacheLineSize

UINT32 EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES::CacheLineSize

TotalCacheLevels

UINT32 EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES::TotalCacheLevels

WritePolicy

UINT32 EFI_ACPI_6_2_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES::WritePolicy

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The documentation for this struct was generated from the following file:

• XenevaOS/Boot/include/IndustryStandard/Acpi62.h