#include <Pal.h>
◆ FailedCacheLevel
| UINT64 PAL_CACHE_CHECK_INFO::FailedCacheLevel |
Bit5:4 Level of cache where the error occurred. A value of 0 indicates the first level of cache.
◆ FailedInDataCache
| UINT64 PAL_CACHE_CHECK_INFO::FailedInDataCache |
Bit10, Failure located in the data cache.
◆ FailedInDataPart
| UINT64 PAL_CACHE_CHECK_INFO::FailedInDataPart |
Bit8, Failure located in the data part of the cache line.
◆ FailedInInsCache
| UINT64 PAL_CACHE_CHECK_INFO::FailedInInsCache |
Bit11, Failure located in the instruction cache.
◆ FailedInTagPart
| UINT64 PAL_CACHE_CHECK_INFO::FailedInTagPart |
Bit9, Failure located in the tag part of the cache line.
◆ FailedWay
| UINT64 PAL_CACHE_CHECK_INFO::FailedWay |
Bit20:16, Failure located in the way of the cache indicated by this value.
◆ IndexOfCacheLineError
| UINT64 PAL_CACHE_CHECK_INFO::IndexOfCacheLineError |
Bit51:32, Index of the cache line where the error occurred.
◆ InstructionSet
| UINT64 PAL_CACHE_CHECK_INFO::InstructionSet |
Bit54, Instruction set. If this value is set to zero, the instruction that generated the machine check was an Intel Itanium instruction. If this bit is set to one, the instruction that generated the machine check was IA-32 instruction.
◆ InstructionSetIsValid
| UINT64 PAL_CACHE_CHECK_INFO::InstructionSetIsValid |
Bit55, The is field in the cache_check parameter is valid.
◆ McCorrected
| UINT64 PAL_CACHE_CHECK_INFO::McCorrected |
Bit59, Machine check corrected: This bit is set to one to indicate that the machine check has been corrected.
◆ Mesi
| UINT64 PAL_CACHE_CHECK_INFO::Mesi |
Bit14:12, 0 - cache line is invalid. 1 - cache line is held shared. 2 - cache line is held exclusive. 3 - cache line is modified. All other values are reserved.
◆ MesiIsValid
| UINT64 PAL_CACHE_CHECK_INFO::MesiIsValid |
Bit15, The mesi field in the cache_check parameter is valid.
◆ MultipleBitsError
| UINT64 PAL_CACHE_CHECK_INFO::MultipleBitsError |
Bit23, A multiple-bit error was detected, and data was poisoned for the corresponding cache line during castout.
◆ Operation
| UINT64 PAL_CACHE_CHECK_INFO::Operation |
Bit3:0, Type of cache operation that caused the machine check: 0 - unknown or internal error 1 - load 2 - store 3 - instruction fetch or instruction prefetch 4 - data prefetch (both hardware and software) 5 - snoop (coherency check) 6 - cast out (explicit or implicit write-back of a cache line) 7 - move in (cache line fill)
◆ PreciseInsPointer
| UINT64 PAL_CACHE_CHECK_INFO::PreciseInsPointer |
Bit63, Precise instruction pointer. This bit is set to one to indicate that a valid precise instruction pointer has been logged.
◆ PrivilegeLevel
| UINT64 PAL_CACHE_CHECK_INFO::PrivilegeLevel |
Bit57:56, Privilege level. The privilege level of the instruction bundle responsible for generating the machine check.
◆ PrivilegeLevelIsValide
| UINT64 PAL_CACHE_CHECK_INFO::PrivilegeLevelIsValide |
Bit58, The pl field of the cache_check parameter is valid.
◆ RequesterIdentifier
| UINT64 PAL_CACHE_CHECK_INFO::RequesterIdentifier |
Bit61, Requester identifier: This bit is set to one to indicate that a valid requester identifier has been logged.
◆ Reserved1
| UINT64 PAL_CACHE_CHECK_INFO::Reserved1 |
◆ Reserved2
| UINT64 PAL_CACHE_CHECK_INFO::Reserved2 |
◆ Reserved3
| UINT64 PAL_CACHE_CHECK_INFO::Reserved3 |
◆ Reserved4
| UINT64 PAL_CACHE_CHECK_INFO::Reserved4 |
◆ ResponserIdentifier
| UINT64 PAL_CACHE_CHECK_INFO::ResponserIdentifier |
Bit62, Responder identifier: This bit is set to one to indicate that a valid responder identifier has been logged.
◆ TargetAddressIsValid
| UINT64 PAL_CACHE_CHECK_INFO::TargetAddressIsValid |
Bit60, Target address is valid: This bit is set to one to indicate that a valid target address has been logged.
◆ WayIndexIsValid
| UINT64 PAL_CACHE_CHECK_INFO::WayIndexIsValid |
Bit21, The way and index field in the cache_check parameter is valid.
The documentation for this struct was generated from the following file:
- XenevaOS/Boot/include/IndustryStandard/Pal.h
