#include <Pal.h>
◆ CoreId
| UINT64 PAL_MC_ERROR_INFO_LEVEL_INDEX::CoreId |
Bit3:0, Processor core ID (default is 0 for processors with a single core)
◆ InfoOfDataCache
| UINT64 PAL_MC_ERROR_INFO_LEVEL_INDEX::InfoOfDataCache |
Bit15:12, Error information is available for 1st, 2nd, 3rd, and 4th level data/unified caches.
◆ InfoOfDataTlb
| UINT64 PAL_MC_ERROR_INFO_LEVEL_INDEX::InfoOfDataTlb |
Bit23:20, Error information is available for 1st, 2nd, 3rd, and 4th level data/unified TLB
◆ InfoOfInsCache
| UINT64 PAL_MC_ERROR_INFO_LEVEL_INDEX::InfoOfInsCache |
Bit11:8, Error information is available for 1st, 2nd, 3rd, and 4th level instruction caches.
◆ InfoOfInsTlb
| UINT64 PAL_MC_ERROR_INFO_LEVEL_INDEX::InfoOfInsTlb |
Bit19:16 Error information is available for 1st, 2nd, 3rd, and 4th level instruction TLB.
◆ InfoOfMicroArch
| UINT64 PAL_MC_ERROR_INFO_LEVEL_INDEX::InfoOfMicroArch |
Bit47:32, Error information is available on micro-architectural structures.
◆ InfoOfProcessorBus
| UINT64 PAL_MC_ERROR_INFO_LEVEL_INDEX::InfoOfProcessorBus |
Bit27:24 Error information is available for the 1st, 2nd, 3rd, and 4th level processor bus hierarchy.
◆ InfoOfRegisterFile
| UINT64 PAL_MC_ERROR_INFO_LEVEL_INDEX::InfoOfRegisterFile |
Bit31:28 Error information is available on register file structures.
◆ Reserved
| UINT64 PAL_MC_ERROR_INFO_LEVEL_INDEX::Reserved |
◆ ThreadId
| UINT64 PAL_MC_ERROR_INFO_LEVEL_INDEX::ThreadId |
Bit7:4, Logical thread ID (default is 0 for processors that execute a single thread)
The documentation for this struct was generated from the following file:
- XenevaOS/Boot/include/IndustryStandard/Pal.h
