#include <Pal.h>

Public Attributes
UINT64	FailedSlot:8

UINT64	FailedSlotIsValid:1

UINT64	Reserved1:1

UINT64	TlbLevel:2

UINT64	Reserved2:4

UINT64	FailedInDataTr:1

UINT64	FailedInInsTr:1

UINT64	FailedInDataTc:1

UINT64	FailedInInsTc:1

UINT64	FailedOperation:4

UINT64	Reserved3:30

UINT64	InstructionSet:1

UINT64	InstructionSetIsValid:1

UINT64	PrivelegeLevel:2

UINT64	PrivelegeLevelIsValid:1

UINT64	McCorrected:1

UINT64	TargetAddressIsValid:1

UINT64	RequesterIdentifier:1

UINT64	ResponserIdentifier:1

UINT64	PreciseInsPointer:1

Member Data Documentation

◆ FailedInDataTc

UINT64 PAL_TLB_CHECK_INFO::FailedInDataTc

Bit18, Error occurred in data translation cache.

◆ FailedInDataTr

UINT64 PAL_TLB_CHECK_INFO::FailedInDataTr

Bit16, Error occurred in the data translation registers.

◆ FailedInInsTc

UINT64 PAL_TLB_CHECK_INFO::FailedInInsTc

Bit19, Error occurred in the instruction translation cache.

◆ FailedInInsTr

UINT64 PAL_TLB_CHECK_INFO::FailedInInsTr

Bit17, Error occurred in the instruction translation registers

◆ FailedOperation

UINT64 PAL_TLB_CHECK_INFO::FailedOperation

Bit23:20, Type of cache operation that caused the machine check: 0 - unknown 1 - TLB access due to load instruction 2 - TLB access due to store instruction 3 - TLB access due to instruction fetch or instruction prefetch 4 - TLB access due to data prefetch (both hardware and software) 5 - TLB shoot down access 6 - TLB probe instruction (probe, tpa) 7 - move in (VHPT fill) 8 - purge (insert operation that purges entries or a TLB purge instruction) All other values are reserved.

◆ FailedSlot

UINT64 PAL_TLB_CHECK_INFO::FailedSlot

Bit7:0, Slot number of the translation register where the failure occurred.

◆ FailedSlotIsValid

UINT64 PAL_TLB_CHECK_INFO::FailedSlotIsValid

Bit8, The tr_slot field in the TLB_check parameter is valid.

◆ InstructionSet

UINT64 PAL_TLB_CHECK_INFO::InstructionSet

Bit54, Instruction set. If this value is set to zero, the instruction that generated the machine check was an Intel Itanium instruction. If this bit is set to one, the instruction that generated the machine check was IA-32 instruction.

◆ InstructionSetIsValid

UINT64 PAL_TLB_CHECK_INFO::InstructionSetIsValid

Bit55, The is field in the TLB_check parameter is valid.

◆ McCorrected

UINT64 PAL_TLB_CHECK_INFO::McCorrected

Bit59, Machine check corrected: This bit is set to one to indicate that the machine check has been corrected.

◆ PreciseInsPointer

UINT64 PAL_TLB_CHECK_INFO::PreciseInsPointer

Bit63 Precise instruction pointer. This bit is set to one to indicate that a valid precise instruction pointer has been logged.

◆ PrivelegeLevel

UINT64 PAL_TLB_CHECK_INFO::PrivelegeLevel

Bit57:56, Privilege level. The privilege level of the instruction bundle responsible for generating the machine check.

◆ PrivelegeLevelIsValid

UINT64 PAL_TLB_CHECK_INFO::PrivelegeLevelIsValid

Bit58, The pl field of the TLB_check parameter is valid.

◆ RequesterIdentifier

UINT64 PAL_TLB_CHECK_INFO::RequesterIdentifier

Bit61 Requester identifier: This bit is set to one to indicate that a valid requester identifier has been logged.

◆ Reserved1

UINT64 PAL_TLB_CHECK_INFO::Reserved1

◆ Reserved2

UINT64 PAL_TLB_CHECK_INFO::Reserved2

◆ Reserved3

UINT64 PAL_TLB_CHECK_INFO::Reserved3

◆ ResponserIdentifier

UINT64 PAL_TLB_CHECK_INFO::ResponserIdentifier

Bit62, Responder identifier: This bit is set to one to indicate that a valid responder identifier has been logged.

◆ TargetAddressIsValid

UINT64 PAL_TLB_CHECK_INFO::TargetAddressIsValid

Bit60, Target address is valid: This bit is set to one to indicate that a valid target address has been logged.

◆ TlbLevel

UINT64 PAL_TLB_CHECK_INFO::TlbLevel

Bit11:10, The level of the TLB where the error occurred. A value of 0 indicates the first level of TLB

The documentation for this struct was generated from the following file:

XenevaOS/Boot/include/IndustryStandard/Pal.h

Public Attributes