#include <Pci22.h>

Detailed Description

PCI-PCI Bridge header region in PCI Configuration Space Section 3.2, PCI-PCI Bridge Architecture, Version 1.2

Member Data Documentation

◆ Bar

UINT32 PCI_BRIDGE_CONTROL_REGISTER::Bar[2]

◆ BridgeControl

UINT16 PCI_BRIDGE_CONTROL_REGISTER::BridgeControl

◆ CapabilityPtr

UINT8 PCI_BRIDGE_CONTROL_REGISTER::CapabilityPtr

◆ ExpansionRomBAR

UINT32 PCI_BRIDGE_CONTROL_REGISTER::ExpansionRomBAR

◆ InterruptLine

UINT8 PCI_BRIDGE_CONTROL_REGISTER::InterruptLine

◆ InterruptPin

UINT8 PCI_BRIDGE_CONTROL_REGISTER::InterruptPin

◆ IoBase

UINT8 PCI_BRIDGE_CONTROL_REGISTER::IoBase

◆ IoBaseUpper16

UINT16 PCI_BRIDGE_CONTROL_REGISTER::IoBaseUpper16

◆ IoLimit

UINT8 PCI_BRIDGE_CONTROL_REGISTER::IoLimit

◆ IoLimitUpper16

UINT16 PCI_BRIDGE_CONTROL_REGISTER::IoLimitUpper16

◆ MemoryBase

UINT16 PCI_BRIDGE_CONTROL_REGISTER::MemoryBase

◆ MemoryLimit

UINT16 PCI_BRIDGE_CONTROL_REGISTER::MemoryLimit

◆ PrefetchableBaseUpper32

UINT32 PCI_BRIDGE_CONTROL_REGISTER::PrefetchableBaseUpper32

◆ PrefetchableLimitUpper32

UINT32 PCI_BRIDGE_CONTROL_REGISTER::PrefetchableLimitUpper32

◆ PrefetchableMemoryBase

UINT16 PCI_BRIDGE_CONTROL_REGISTER::PrefetchableMemoryBase

◆ PrefetchableMemoryLimit

UINT16 PCI_BRIDGE_CONTROL_REGISTER::PrefetchableMemoryLimit

◆ PrimaryBus

UINT8 PCI_BRIDGE_CONTROL_REGISTER::PrimaryBus

◆ Reserved

UINT8 PCI_BRIDGE_CONTROL_REGISTER::Reserved[3]

◆ SecondaryBus

UINT8 PCI_BRIDGE_CONTROL_REGISTER::SecondaryBus

◆ SecondaryLatencyTimer

UINT8 PCI_BRIDGE_CONTROL_REGISTER::SecondaryLatencyTimer

◆ SecondaryStatus

UINT16 PCI_BRIDGE_CONTROL_REGISTER::SecondaryStatus

◆ SubordinateBus

UINT8 PCI_BRIDGE_CONTROL_REGISTER::SubordinateBus

The documentation for this struct was generated from the following file:

XenevaOS/Boot/include/IndustryStandard/Pci22.h

Public Attributes
UINT32	Bar [2]

UINT8	PrimaryBus

UINT8	SecondaryBus

UINT8	SubordinateBus

UINT8	SecondaryLatencyTimer

UINT8	IoBase

UINT8	IoLimit

UINT16	SecondaryStatus

UINT16	MemoryBase

UINT16	MemoryLimit

UINT16	PrefetchableMemoryBase

UINT16	PrefetchableMemoryLimit

UINT32	PrefetchableBaseUpper32

UINT32	PrefetchableLimitUpper32

UINT16	IoBaseUpper16

UINT16	IoLimitUpper16

UINT8	CapabilityPtr

UINT8	Reserved [3]

UINT32	ExpansionRomBAR

UINT8	InterruptLine

UINT8	InterruptPin

UINT16	BridgeControl

Public Attributes