#include <TpmPtp.h>
◆ Access
| UINT8 PTP_FIFO_REGISTERS::Access |
Used to gain ownership for this particular port.
◆ BurstCount
| UINT16 PTP_FIFO_REGISTERS::BurstCount |
Number of consecutive writes that can be done to the TPM.
◆ DataFifo
| UINT32 PTP_FIFO_REGISTERS::DataFifo |
Read or write FIFO, depending on transaction.
◆ Did
| UINT16 PTP_FIFO_REGISTERS::Did |
◆ IntEnable
| UINT32 PTP_FIFO_REGISTERS::IntEnable |
◆ InterfaceCapability
| UINT32 PTP_FIFO_REGISTERS::InterfaceCapability |
Shows which interrupts are supported by that particular TPM.
◆ InterfaceId
| UINT32 PTP_FIFO_REGISTERS::InterfaceId |
Used to identify the Interface types supported by the TPM.
◆ IntSts
| UINT32 PTP_FIFO_REGISTERS::IntSts |
◆ IntVector
| UINT8 PTP_FIFO_REGISTERS::IntVector |
SIRQ vector to be used by the TPM.
◆ Reserved
| UINT8 PTP_FIFO_REGISTERS::Reserved[0xfb] |
◆ Reserved1
| UINT8 PTP_FIFO_REGISTERS::Reserved1[7] |
◆ Reserved2
| UINT8 PTP_FIFO_REGISTERS::Reserved2[3] |
◆ Reserved3
| UINT8 PTP_FIFO_REGISTERS::Reserved3[8] |
◆ Reserved4
| UINT8 PTP_FIFO_REGISTERS::Reserved4[8] |
◆ Reserved5
| UINT8 PTP_FIFO_REGISTERS::Reserved5[0x4c] |
◆ Reserved6
| UINT8 PTP_FIFO_REGISTERS::Reserved6[0xe7c] |
◆ Rid
| UINT8 PTP_FIFO_REGISTERS::Rid |
◆ Status
| UINT8 PTP_FIFO_REGISTERS::Status |
Status Register. Provides status of the TPM.
◆ StatusEx
| UINT8 PTP_FIFO_REGISTERS::StatusEx |
Additional Status Register.
◆ Vid
| UINT16 PTP_FIFO_REGISTERS::Vid |
◆ XDataFifo
| UINT32 PTP_FIFO_REGISTERS::XDataFifo |
Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write)
The documentation for this struct was generated from the following file:
- XenevaOS/Boot/include/IndustryStandard/TpmPtp.h