_EFI_SPI_HC_PROTOCOL Struct Reference

#include <SpiHc.h>

Collaboration diagram for _EFI_SPI_HC_PROTOCOL:

Public Attributes
UINT32	Attributes
UINT32	FrameSizeSupportMask
UINT32	MaximumTransferBytes
EFI_SPI_HC_PROTOCOL_CHIP_SELECT	ChipSelect
EFI_SPI_HC_PROTOCOL_CLOCK	Clock
EFI_SPI_HC_PROTOCOL_TRANSACTION	Transaction

Detailed Description

Support a SPI data transaction between the SPI controller and a SPI chip.

Member Data Documentation

Attributes

UINT32 _EFI_SPI_HC_PROTOCOL::Attributes

Host control attributes, may have zero or more of the following set:

• HC_SUPPORTS_WRITE_ONLY_OPERATIONS
• HC_SUPPORTS_READ_ONLY_OPERATIONS
• HC_SUPPORTS_WRITE_THEN_READ_OPERATIONS
• HC_TX_FRAME_IN_MOST_SIGNIFICANT_BITS
  • The SPI host controller requires the transmit frame to be in most significant bits instead of least significant bits.The host driver will adjust the frames if necessary.
• HC_RX_FRAME_IN_MOST_SIGNIFICANT_BITS
  • The SPI host controller places the receive frame to be in most significant bits instead of least significant bits.The host driver will adjust the frames to be in the least significant bits if necessary.
• HC_SUPPORTS_2_BIT_DATA_BUS_W1DTH
  • The SPI controller supports a 2 - bit data bus
• HC_SUPPORTS_4_B1T_DATA_BUS_WIDTH
  • The SPI controller supports a 4 - bit data bus
• HC_TRANSFER_SIZE_INCLUDES_OPCODE
  • Transfer size includes the opcode byte
• HC_TRANSFER_SIZE_INCLUDES_ADDRESS
  • Transfer size includes the 3 address bytes The SPI host controller must support full - duplex (receive while sending) operation.The SPI host controller must support a 1 - bit bus width.

ChipSelect

EFI_SPI_HC_PROTOCOL_CHIP_SELECT _EFI_SPI_HC_PROTOCOL::ChipSelect

Assert or deassert the SPI chip select.

Clock

EFI_SPI_HC_PROTOCOL_CLOCK _EFI_SPI_HC_PROTOCOL::Clock

Set up the clock generator to produce the correct clock frequency, phase and polarity for a SPI chip.

FrameSizeSupportMask

UINT32 _EFI_SPI_HC_PROTOCOL::FrameSizeSupportMask

Mask of frame sizes which the SPI host controller supports. Frame size of N-bits is supported when bit N-1 is set. The host controller must support a frame size of 8-bits.

MaximumTransferBytes

UINT32 _EFI_SPI_HC_PROTOCOL::MaximumTransferBytes

Maximum transfer size in bytes: 1 - Oxffffffff

Transaction

EFI_SPI_HC_PROTOCOL_TRANSACTION _EFI_SPI_HC_PROTOCOL::Transaction

Perform the SPI transaction on the SPI peripheral using the SPI host controller.

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The documentation for this struct was generated from the following file:

• XenevaOS/Boot/include/Protocol/SpiHc.h