#include <amdgpu_drm.h>

Public Attributes
__u32	device_id

__u32	chip_rev

__u32	external_rev

__u32	pci_rev

__u32	family

__u32	num_shader_engines

__u32	num_shader_arrays_per_engine

__u32	gpu_counter_freq

__u64	max_engine_clock

__u64	max_memory_clock

__u32	cu_active_number

__u32	cu_ao_mask

__u32	cu_bitmap [4][4]

__u32	enabled_rb_pipes_mask

__u32	num_rb_pipes

__u32	num_hw_gfx_contexts

__u32	pcie_gen

__u64	ids_flags

__u64	virtual_address_offset

__u64	virtual_address_max

__u32	virtual_address_alignment

__u32	pte_fragment_size

__u32	gart_page_size

__u32	ce_ram_size

__u32	vram_type

__u32	vram_bit_width

__u32	vce_harvest_config

__u32	gc_double_offchip_lds_buf

__u64	prim_buf_gpu_addr

__u64	pos_buf_gpu_addr

__u64	cntl_sb_buf_gpu_addr

__u64	param_buf_gpu_addr

__u32	prim_buf_size

__u32	pos_buf_size

__u32	cntl_sb_buf_size

__u32	param_buf_size

__u32	wave_front_size

__u32	num_shader_visible_vgprs

__u32	num_cu_per_sh

__u32	num_tcc_blocks

__u32	gs_vgt_table_depth

__u32	gs_prim_buffer_depth

__u32	max_gs_waves_per_vgt

__u32	pcie_num_lanes

__u32	cu_ao_bitmap [4][4]

__u64	high_va_offset

__u64	high_va_max

__u32	pa_sc_tile_steering_override

__u64	tcc_disabled_mask

__u64	min_engine_clock

__u64	min_memory_clock

__u32	tcp_cache_size

__u32	num_sqc_per_wgp

__u32	sqc_data_cache_size

__u32	sqc_inst_cache_size

__u32	gl1c_cache_size

__u32	gl2c_cache_size

__u64	mall_size

__u32	enabled_rb_pipes_mask_hi

__u32	shadow_size

__u32	shadow_alignment

__u32	csa_size

__u32	csa_alignment

__u32	userq_ip_mask

__u32	pad

Member Data Documentation

◆ ce_ram_size

__u32 drm_amdgpu_info_device::ce_ram_size

constant engine ram size

◆ chip_rev

__u32 drm_amdgpu_info_device::chip_rev

Internal chip revision: A0, A1, etc.)

◆ cntl_sb_buf_gpu_addr

__u64 drm_amdgpu_info_device::cntl_sb_buf_gpu_addr

◆ cntl_sb_buf_size

__u32 drm_amdgpu_info_device::cntl_sb_buf_size

◆ csa_alignment

__u32 drm_amdgpu_info_device::csa_alignment

◆ csa_size

__u32 drm_amdgpu_info_device::csa_size

◆ cu_active_number

__u32 drm_amdgpu_info_device::cu_active_number

◆ cu_ao_bitmap

__u32 drm_amdgpu_info_device::cu_ao_bitmap[4][4]

◆ cu_ao_mask

__u32 drm_amdgpu_info_device::cu_ao_mask

◆ cu_bitmap

__u32 drm_amdgpu_info_device::cu_bitmap[4][4]

◆ device_id

__u32 drm_amdgpu_info_device::device_id

PCI Device ID

◆ enabled_rb_pipes_mask

__u32 drm_amdgpu_info_device::enabled_rb_pipes_mask

Render backend pipe mask. One render backend is CB+DB.

◆ enabled_rb_pipes_mask_hi

__u32 drm_amdgpu_info_device::enabled_rb_pipes_mask_hi

◆ external_rev

__u32 drm_amdgpu_info_device::external_rev

◆ family

__u32 drm_amdgpu_info_device::family

◆ gart_page_size

__u32 drm_amdgpu_info_device::gart_page_size

◆ gc_double_offchip_lds_buf

__u32 drm_amdgpu_info_device::gc_double_offchip_lds_buf

◆ gl1c_cache_size

__u32 drm_amdgpu_info_device::gl1c_cache_size

◆ gl2c_cache_size

__u32 drm_amdgpu_info_device::gl2c_cache_size

◆ gpu_counter_freq

__u32 drm_amdgpu_info_device::gpu_counter_freq

◆ gs_prim_buffer_depth

__u32 drm_amdgpu_info_device::gs_prim_buffer_depth

◆ gs_vgt_table_depth

__u32 drm_amdgpu_info_device::gs_vgt_table_depth

◆ high_va_max

__u64 drm_amdgpu_info_device::high_va_max

The maximum high virtual address

◆ high_va_offset

__u64 drm_amdgpu_info_device::high_va_offset

Starting high virtual address for UMDs.

◆ ids_flags

__u64 drm_amdgpu_info_device::ids_flags

◆ mall_size

__u64 drm_amdgpu_info_device::mall_size

◆ max_engine_clock

__u64 drm_amdgpu_info_device::max_engine_clock

◆ max_gs_waves_per_vgt

__u32 drm_amdgpu_info_device::max_gs_waves_per_vgt

◆ max_memory_clock

__u64 drm_amdgpu_info_device::max_memory_clock

◆ min_engine_clock

__u64 drm_amdgpu_info_device::min_engine_clock

◆ min_memory_clock

__u64 drm_amdgpu_info_device::min_memory_clock

◆ num_cu_per_sh

__u32 drm_amdgpu_info_device::num_cu_per_sh

◆ num_hw_gfx_contexts

__u32 drm_amdgpu_info_device::num_hw_gfx_contexts

◆ num_rb_pipes

__u32 drm_amdgpu_info_device::num_rb_pipes

◆ num_shader_arrays_per_engine

__u32 drm_amdgpu_info_device::num_shader_arrays_per_engine

◆ num_shader_engines

__u32 drm_amdgpu_info_device::num_shader_engines

◆ num_shader_visible_vgprs

__u32 drm_amdgpu_info_device::num_shader_visible_vgprs

◆ num_sqc_per_wgp

__u32 drm_amdgpu_info_device::num_sqc_per_wgp

◆ num_tcc_blocks

__u32 drm_amdgpu_info_device::num_tcc_blocks

◆ pa_sc_tile_steering_override

__u32 drm_amdgpu_info_device::pa_sc_tile_steering_override

◆ pad

__u32 drm_amdgpu_info_device::pad

◆ param_buf_gpu_addr

__u64 drm_amdgpu_info_device::param_buf_gpu_addr

◆ param_buf_size

__u32 drm_amdgpu_info_device::param_buf_size

◆ pci_rev

__u32 drm_amdgpu_info_device::pci_rev

Revision id in PCI Config space

◆ pcie_gen

__u32 drm_amdgpu_info_device::pcie_gen

◆ pcie_num_lanes

__u32 drm_amdgpu_info_device::pcie_num_lanes

◆ pos_buf_gpu_addr

__u64 drm_amdgpu_info_device::pos_buf_gpu_addr

◆ pos_buf_size

__u32 drm_amdgpu_info_device::pos_buf_size

◆ prim_buf_gpu_addr

__u64 drm_amdgpu_info_device::prim_buf_gpu_addr

◆ prim_buf_size

__u32 drm_amdgpu_info_device::prim_buf_size

◆ pte_fragment_size

__u32 drm_amdgpu_info_device::pte_fragment_size

Page table entry - fragment size

◆ shadow_alignment

__u32 drm_amdgpu_info_device::shadow_alignment

◆ shadow_size

__u32 drm_amdgpu_info_device::shadow_size

◆ sqc_data_cache_size

__u32 drm_amdgpu_info_device::sqc_data_cache_size

◆ sqc_inst_cache_size

__u32 drm_amdgpu_info_device::sqc_inst_cache_size

◆ tcc_disabled_mask

__u64 drm_amdgpu_info_device::tcc_disabled_mask

◆ tcp_cache_size

__u32 drm_amdgpu_info_device::tcp_cache_size

◆ userq_ip_mask

__u32 drm_amdgpu_info_device::userq_ip_mask

◆ vce_harvest_config

__u32 drm_amdgpu_info_device::vce_harvest_config

◆ virtual_address_alignment

__u32 drm_amdgpu_info_device::virtual_address_alignment

Required alignment of virtual addresses.

◆ virtual_address_max

__u64 drm_amdgpu_info_device::virtual_address_max

The maximum virtual address

◆ virtual_address_offset

__u64 drm_amdgpu_info_device::virtual_address_offset

Starting virtual address for UMDs.

◆ vram_bit_width

__u32 drm_amdgpu_info_device::vram_bit_width

video memory bit width

◆ vram_type

__u32 drm_amdgpu_info_device::vram_type

video memory type info

◆ wave_front_size

__u32 drm_amdgpu_info_device::wave_front_size

The documentation for this struct was generated from the following file:

XenevaOS/BaseHdr/uapi/drm/amdgpu_drm.h

Public Attributes