#include <amdgpu_drm.h>

Public Attributes
__u32	op

__u32	queue_id

__u32	ip_type

__u32	doorbell_handle

__u32	doorbell_offset

__u32	flags

__u64	queue_va

__u64	queue_size

__u64	rptr_va

__u64	wptr_va

__u64	mqd

__u64	mqd_size

Member Data Documentation

◆ doorbell_handle

__u32 drm_amdgpu_userq_in::doorbell_handle

@doorbell_handle: the handle of doorbell GEM object associated with this userqueue client.

◆ doorbell_offset

__u32 drm_amdgpu_userq_in::doorbell_offset

@doorbell_offset: 32-bit offset of the doorbell in the doorbell bo. Kernel will generate absolute doorbell offset using doorbell_handle and doorbell_offset in the doorbell bo.

◆ flags

__u32 drm_amdgpu_userq_in::flags

@flags: flags used for queue parameters

◆ ip_type

__u32 drm_amdgpu_userq_in::ip_type

the target GPU engine to execute workload (AMDGPU_HW_IP_*)

◆ mqd

__u64 drm_amdgpu_userq_in::mqd

@mqd: MQD (memory queue descriptor) is a set of parameters which allow the GPU to uniquely define and identify a usermode queue.

MQD data can be of different size for different GPU IP/engine and their respective versions/revisions, so this points to a __u64 * which holds IP specific MQD of this usermode queue.

◆ mqd_size

__u64 drm_amdgpu_userq_in::mqd_size

@size: size of MQD data in bytes, it must match the MQD structure size of the respective engine/revision defined in UAPI for ex, for gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11).

◆ op

__u32 drm_amdgpu_userq_in::op

AMDGPU_USERQ_OP_*

◆ queue_id

__u32 drm_amdgpu_userq_in::queue_id

Queue id passed for operation USERQ_OP_FREE

◆ queue_size

__u64 drm_amdgpu_userq_in::queue_size

@queue_size: Size of the queue in bytes, this needs to be 256-byte aligned.

◆ queue_va

__u64 drm_amdgpu_userq_in::queue_va

@queue_va: Virtual address of the GPU memory which holds the queue object. The queue holds the workload packets.

◆ rptr_va

__u64 drm_amdgpu_userq_in::rptr_va

@rptr_va : Virtual address of the GPU memory which holds the ring RPTR. This object must be at least 8 byte in size and aligned to 8-byte offset.

◆ wptr_va

__u64 drm_amdgpu_userq_in::wptr_va

@wptr_va : Virtual address of the GPU memory which holds the ring WPTR. This object must be at least 8 byte in size and aligned to 8-byte offset.

Queue, RPTR and WPTR can come from the same object, as long as the size and alignment related requirements are met.

The documentation for this struct was generated from the following file:

XenevaOS/BaseHdr/uapi/drm/amdgpu_drm.h

Public Attributes