drm_asahi_queue_create Struct Reference

#include <asahi_drm.h>

Public Attributes
__u32	flags
__u32	vm_id
__u32	priority
__u32	queue_id
__u64	usc_exec_base

Detailed Description

struct drm_asahi_queue_create - Arguments passed to DRM_IOCTL_ASAHI_QUEUE_CREATE

Member Data Documentation

flags

__u32 drm_asahi_queue_create::flags

@flags: MBZ

priority

__u32 drm_asahi_queue_create::priority

@priority: One of drm_asahi_priority

queue_id

__u32 drm_asahi_queue_create::queue_id

@queue_id: The returned queue ID

usc_exec_base

__u64 drm_asahi_queue_create::usc_exec_base

@usc_exec_base: GPU base address for all USC binaries (shaders) on this queue. USC addresses are 32-bit relative to this 64-bit base.

This sets the following registers on all queue commands:

USC_EXEC_BASE_TA (vertex) USC_EXEC_BASE_ISP (fragment) USC_EXEC_BASE_CP (compute)

While the hardware lets us configure these independently per command, we do not have a use case for this. Instead, we expect userspace to fix a 4GiB VA carveout for USC memory and pass its base address here.

vm_id

__u32 drm_asahi_queue_create::vm_id

@vm_id: The ID of the VM this queue is bound to

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The documentation for this struct was generated from the following file:

• XenevaOS/BaseHdr/uapi/drm/asahi_drm.h