XenevaOS
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Public Attributes | List of all members
hl_info_hw_ip_info Struct Reference

#include <habanalabs_accel.h>

Public Attributes

__u64 sram_base_address
 
__u64 dram_base_address
 
__u64 dram_size
 
__u32 sram_size
 
__u32 num_of_events
 
__u32 device_id
 
__u32 module_id
 
__u32 decoder_enabled_mask
 
__u16 first_available_interrupt_id
 
__u16 server_type
 
__u32 cpld_version
 
__u32 psoc_pci_pll_nr
 
__u32 psoc_pci_pll_nf
 
__u32 psoc_pci_pll_od
 
__u32 psoc_pci_pll_div_factor
 
__u8 tpc_enabled_mask
 
__u8 dram_enabled
 
__u8 security_enabled
 
__u8 mme_master_slave_mode
 
__u8 cpucp_version [HL_INFO_VERSION_MAX_LEN]
 
__u8 card_name [HL_INFO_CARD_NAME_MAX_LEN]
 
__u64 tpc_enabled_mask_ext
 
__u64 dram_page_size
 
__u32 edma_enabled_mask
 
__u16 number_of_user_interrupts
 
__u8 reserved1
 
__u8 reserved2
 
__u64 reserved3
 
__u64 device_mem_alloc_default_page_size
 
__u64 reserved4
 
__u64 reserved5
 
__u32 reserved6
 
__u8 reserved7
 
__u8 revision_id
 
__u16 tpc_interrupt_id
 
__u32 rotator_enabled_mask
 
__u32 reserved9
 
__u64 engine_core_interrupt_reg_addr
 
__u64 reserved_dram_size
 

Detailed Description

struct hl_info_hw_ip_info - hardware information on various IPs in the ASIC @sram_base_address: The first SRAM physical base address that is free to be used by the user. @dram_base_address: The first DRAM virtual or physical base address that is free to be used by the user. @dram_size: The DRAM size that is available to the user. @sram_size: The SRAM size that is available to the user. @num_of_events: The number of events that can be received from the f/w. This is needed so the user can what is the size of the h/w events array he needs to pass to the kernel when he wants to fetch the event counters. @device_id: PCI device ID of the ASIC. @module_id: Module ID of the ASIC for mezzanine cards in servers (From OCP spec). @decoder_enabled_mask: Bit-mask that represents which decoders are enabled. @first_available_interrupt_id: The first available interrupt ID for the user to be used when it works with user interrupts. Relevant for Gaudi2 and later. @server_type: Server type that the Gaudi ASIC is currently installed in. The value is according to enum hl_server_type @cpld_version: CPLD version on the board. @psoc_pci_pll_nr: PCI PLL NR value. Needed by the profiler in some ASICs. @psoc_pci_pll_nf: PCI PLL NF value. Needed by the profiler in some ASICs. @psoc_pci_pll_od: PCI PLL OD value. Needed by the profiler in some ASICs. @psoc_pci_pll_div_factor: PCI PLL DIV factor value. Needed by the profiler in some ASICs. @tpc_enabled_mask: Bit-mask that represents which TPCs are enabled. Relevant for Goya/Gaudi only. @dram_enabled: Whether the DRAM is enabled. @security_enabled: Whether security is enabled on device. @mme_master_slave_mode: Indicate whether the MME is working in master/slave configuration. Relevant for Gaudi2 and later. @cpucp_version: The CPUCP f/w version. @card_name: The card name as passed by the f/w. @tpc_enabled_mask_ext: Bit-mask that represents which TPCs are enabled. Relevant for Gaudi2 and later. @dram_page_size: The DRAM physical page size. @edma_enabled_mask: Bit-mask that represents which EDMAs are enabled. Relevant for Gaudi2 and later. @number_of_user_interrupts: The number of interrupts that are available to the userspace application to use. Relevant for Gaudi2 and later. @device_mem_alloc_default_page_size: default page size used in device memory allocation. @revision_id: PCI revision ID of the ASIC. @tpc_interrupt_id: interrupt id for TPC to use in order to raise events towards the host. @rotator_enabled_mask: Bit-mask that represents which rotators are enabled. Relevant for Gaudi3 and later. @engine_core_interrupt_reg_addr: interrupt register address for engine core to use in order to raise events toward FW. @reserved_dram_size: DRAM size reserved for driver and firmware.

Member Data Documentation

◆ card_name

__u8 hl_info_hw_ip_info::card_name[HL_INFO_CARD_NAME_MAX_LEN]

◆ cpld_version

__u32 hl_info_hw_ip_info::cpld_version

◆ cpucp_version

__u8 hl_info_hw_ip_info::cpucp_version[HL_INFO_VERSION_MAX_LEN]

◆ decoder_enabled_mask

__u32 hl_info_hw_ip_info::decoder_enabled_mask

◆ device_id

__u32 hl_info_hw_ip_info::device_id

◆ device_mem_alloc_default_page_size

__u64 hl_info_hw_ip_info::device_mem_alloc_default_page_size

◆ dram_base_address

__u64 hl_info_hw_ip_info::dram_base_address

◆ dram_enabled

__u8 hl_info_hw_ip_info::dram_enabled

◆ dram_page_size

__u64 hl_info_hw_ip_info::dram_page_size

◆ dram_size

__u64 hl_info_hw_ip_info::dram_size

◆ edma_enabled_mask

__u32 hl_info_hw_ip_info::edma_enabled_mask

◆ engine_core_interrupt_reg_addr

__u64 hl_info_hw_ip_info::engine_core_interrupt_reg_addr

◆ first_available_interrupt_id

__u16 hl_info_hw_ip_info::first_available_interrupt_id

◆ mme_master_slave_mode

__u8 hl_info_hw_ip_info::mme_master_slave_mode

◆ module_id

__u32 hl_info_hw_ip_info::module_id

◆ num_of_events

__u32 hl_info_hw_ip_info::num_of_events

◆ number_of_user_interrupts

__u16 hl_info_hw_ip_info::number_of_user_interrupts

◆ psoc_pci_pll_div_factor

__u32 hl_info_hw_ip_info::psoc_pci_pll_div_factor

◆ psoc_pci_pll_nf

__u32 hl_info_hw_ip_info::psoc_pci_pll_nf

◆ psoc_pci_pll_nr

__u32 hl_info_hw_ip_info::psoc_pci_pll_nr

◆ psoc_pci_pll_od

__u32 hl_info_hw_ip_info::psoc_pci_pll_od

◆ reserved1

__u8 hl_info_hw_ip_info::reserved1

◆ reserved2

__u8 hl_info_hw_ip_info::reserved2

◆ reserved3

__u64 hl_info_hw_ip_info::reserved3

◆ reserved4

__u64 hl_info_hw_ip_info::reserved4

◆ reserved5

__u64 hl_info_hw_ip_info::reserved5

◆ reserved6

__u32 hl_info_hw_ip_info::reserved6

◆ reserved7

__u8 hl_info_hw_ip_info::reserved7

◆ reserved9

__u32 hl_info_hw_ip_info::reserved9

◆ reserved_dram_size

__u64 hl_info_hw_ip_info::reserved_dram_size

◆ revision_id

__u8 hl_info_hw_ip_info::revision_id

◆ rotator_enabled_mask

__u32 hl_info_hw_ip_info::rotator_enabled_mask

◆ security_enabled

__u8 hl_info_hw_ip_info::security_enabled

◆ server_type

__u16 hl_info_hw_ip_info::server_type

◆ sram_base_address

__u64 hl_info_hw_ip_info::sram_base_address

◆ sram_size

__u32 hl_info_hw_ip_info::sram_size

◆ tpc_enabled_mask

__u8 hl_info_hw_ip_info::tpc_enabled_mask

◆ tpc_enabled_mask_ext

__u64 hl_info_hw_ip_info::tpc_enabled_mask_ext

◆ tpc_interrupt_id

__u16 hl_info_hw_ip_info::tpc_interrupt_id

The documentation for this struct was generated from the following file: