PCI_REG_PCIE_LINK_CAPABILITY Union Reference

#include <PciExpress21.h>

Public Attributes
struct {
UINT32   MaxLinkSpeed: 4
UINT32   MaxLinkWidth: 6
UINT32   Aspm: 2
UINT32   L0sExitLatency: 3
UINT32   L1ExitLatency: 3
UINT32   ClockPowerManagement: 1
UINT32   SurpriseDownError: 1
UINT32   DataLinkLayerLinkActive: 1
UINT32   LinkBandwidthNotification: 1
UINT32   AspmOptionalityCompliance: 1
UINT32   Reserved: 1
UINT32   PortNumber: 8
}	Bits
UINT32	Uint32

Member Data Documentation

Aspm

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::Aspm

AspmOptionalityCompliance

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::AspmOptionalityCompliance

[struct]

struct { ... } PCI_REG_PCIE_LINK_CAPABILITY::Bits

ClockPowerManagement

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::ClockPowerManagement

DataLinkLayerLinkActive

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::DataLinkLayerLinkActive

L0sExitLatency

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::L0sExitLatency

L1ExitLatency

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::L1ExitLatency

LinkBandwidthNotification

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::LinkBandwidthNotification

MaxLinkSpeed

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::MaxLinkSpeed

MaxLinkWidth

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::MaxLinkWidth

PortNumber

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::PortNumber

Reserved

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::Reserved

SurpriseDownError

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::SurpriseDownError

Uint32

UINT32 PCI_REG_PCIE_LINK_CAPABILITY::Uint32

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The documentation for this union was generated from the following file:

• XenevaOS/Boot/include/IndustryStandard/PciExpress21.h