SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH Union Reference

#include <SdramSpdDdr3.h>

Public Attributes
struct {
UINT8   AddressCommandPrelaunch: 1
	Bits 0:0. More...
UINT8   Rank1Rank5Swap: 1
	Bits 1:1. More...
UINT8   Reserved0: 1
	Bits 2:2. More...
UINT8   Reserved1: 1
	Bits 3:3. More...
UINT8   AddressCommandOutputs: 2
	Bits 5:4. More...
UINT8   QxCS_nOutputs: 2
	Bits 7:6. More...
}	Bits
UINT8	Data

Member Data Documentation

AddressCommandOutputs

UINT8 SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH::AddressCommandOutputs

Bits 5:4.

AddressCommandPrelaunch

UINT8 SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH::AddressCommandPrelaunch

Bits 0:0.

[struct]

struct { ... } SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH::Bits

Data

UINT8 SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH::Data

QxCS_nOutputs

UINT8 SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH::QxCS_nOutputs

Bits 7:6.

Rank1Rank5Swap

UINT8 SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH::Rank1Rank5Swap

Bits 1:1.

Reserved0

UINT8 SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH::Reserved0

Bits 2:2.

Reserved1

UINT8 SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH::Reserved1

Bits 3:3.

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The documentation for this union was generated from the following file:

• XenevaOS/Boot/include/IndustryStandard/SdramSpdDdr3.h