#include "drm.h"

Include dependency graph for vc4_drm.h:

Classes
struct	drm_vc4_submit_rcl_surface

struct	drm_vc4_submit_cl

struct	drm_vc4_wait_seqno

struct	drm_vc4_wait_bo

struct	drm_vc4_create_bo

struct	drm_vc4_mmap_bo

struct	drm_vc4_create_shader_bo

struct	drm_vc4_get_hang_state_bo

struct	drm_vc4_get_hang_state

struct	drm_vc4_get_param

struct	drm_vc4_get_tiling

struct	drm_vc4_set_tiling

struct	drm_vc4_label_bo

struct	drm_vc4_gem_madvise

struct	drm_vc4_perfmon_create

struct	drm_vc4_perfmon_destroy

struct	drm_vc4_perfmon_get_values

Macros
#define	DRM_VC4_SUBMIT_CL 0x00

#define	DRM_VC4_WAIT_SEQNO 0x01

#define	DRM_VC4_WAIT_BO 0x02

#define	DRM_VC4_CREATE_BO 0x03

#define	DRM_VC4_MMAP_BO 0x04

#define	DRM_VC4_CREATE_SHADER_BO 0x05

#define	DRM_VC4_GET_HANG_STATE 0x06

#define	DRM_VC4_GET_PARAM 0x07

#define	DRM_VC4_SET_TILING 0x08

#define	DRM_VC4_GET_TILING 0x09

#define	DRM_VC4_LABEL_BO 0x0a

#define	DRM_VC4_GEM_MADVISE 0x0b

#define	DRM_VC4_PERFMON_CREATE 0x0c

#define	DRM_VC4_PERFMON_DESTROY 0x0d

#define	DRM_VC4_PERFMON_GET_VALUES 0x0e

#define	DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)

#define	DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)

#define	DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)

#define	DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)

#define	DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)

#define	DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)

#define	DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)

#define	DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)

#define	DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)

#define	DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)

#define	DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)

#define	DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise)

#define	DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create)

#define	DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy)

#define	DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values)

#define	VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)

#define	VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)

#define	VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1)

#define	VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2)

#define	VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3)

#define	DRM_VC4_PARAM_V3D_IDENT0 0

#define	DRM_VC4_PARAM_V3D_IDENT1 1

#define	DRM_VC4_PARAM_V3D_IDENT2 2

#define	DRM_VC4_PARAM_SUPPORTS_BRANCHES 3

#define	DRM_VC4_PARAM_SUPPORTS_ETC1 4

#define	DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5

#define	DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6

#define	DRM_VC4_PARAM_SUPPORTS_MADVISE 7

#define	DRM_VC4_PARAM_SUPPORTS_PERFMON 8

#define	VC4_MADV_WILLNEED 0

#define	VC4_MADV_DONTNEED 1

#define	__VC4_MADV_PURGED 2

#define	__VC4_MADV_NOTSUPP 3

#define	DRM_VC4_MAX_PERF_COUNTERS 16

Enumerations
enum	{ VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER , VC4_PERFCNT_FEP_VALID_PRIMS_RENDER , VC4_PERFCNT_FEP_CLIPPED_QUADS , VC4_PERFCNT_FEP_VALID_QUADS , VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL , VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL , VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL , VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE , VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE , VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF , VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT , VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING , VC4_PERFCNT_PSE_PRIMS_REVERSED , VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES , VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING , VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING , VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST , VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS , VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD , VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS , VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT , VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS , VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT , VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS , VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED , VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS , VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED , VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED , VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT , VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS , VC4_PERFCNT_NUM_EVENTS }

Macro Definition Documentation

◆ __VC4_MADV_NOTSUPP

#define __VC4_MADV_NOTSUPP 3

◆ __VC4_MADV_PURGED

#define __VC4_MADV_PURGED 2

◆ DRM_IOCTL_VC4_CREATE_BO

#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)

◆ DRM_IOCTL_VC4_CREATE_SHADER_BO

#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)

◆ DRM_IOCTL_VC4_GEM_MADVISE

#define DRM_IOCTL_VC4_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GEM_MADVISE, struct drm_vc4_gem_madvise)

◆ DRM_IOCTL_VC4_GET_HANG_STATE

#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)

◆ DRM_IOCTL_VC4_GET_PARAM

#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)

◆ DRM_IOCTL_VC4_GET_TILING

#define DRM_IOCTL_VC4_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_TILING, struct drm_vc4_get_tiling)

◆ DRM_IOCTL_VC4_LABEL_BO

#define DRM_IOCTL_VC4_LABEL_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_LABEL_BO, struct drm_vc4_label_bo)

◆ DRM_IOCTL_VC4_MMAP_BO

#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)

◆ DRM_IOCTL_VC4_PERFMON_CREATE

#define DRM_IOCTL_VC4_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_CREATE, struct drm_vc4_perfmon_create)

◆ DRM_IOCTL_VC4_PERFMON_DESTROY

#define DRM_IOCTL_VC4_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_DESTROY, struct drm_vc4_perfmon_destroy)

◆ DRM_IOCTL_VC4_PERFMON_GET_VALUES

#define DRM_IOCTL_VC4_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_PERFMON_GET_VALUES, struct drm_vc4_perfmon_get_values)

◆ DRM_IOCTL_VC4_SET_TILING

#define DRM_IOCTL_VC4_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SET_TILING, struct drm_vc4_set_tiling)

◆ DRM_IOCTL_VC4_SUBMIT_CL

#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)

◆ DRM_IOCTL_VC4_WAIT_BO

#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)

◆ DRM_IOCTL_VC4_WAIT_SEQNO

#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)

◆ DRM_VC4_CREATE_BO

#define DRM_VC4_CREATE_BO 0x03

◆ DRM_VC4_CREATE_SHADER_BO

#define DRM_VC4_CREATE_SHADER_BO 0x05

◆ DRM_VC4_GEM_MADVISE

#define DRM_VC4_GEM_MADVISE 0x0b

◆ DRM_VC4_GET_HANG_STATE

#define DRM_VC4_GET_HANG_STATE 0x06

◆ DRM_VC4_GET_PARAM

#define DRM_VC4_GET_PARAM 0x07

◆ DRM_VC4_GET_TILING

#define DRM_VC4_GET_TILING 0x09

◆ DRM_VC4_LABEL_BO

#define DRM_VC4_LABEL_BO 0x0a

◆ DRM_VC4_MAX_PERF_COUNTERS

#define DRM_VC4_MAX_PERF_COUNTERS 16

◆ DRM_VC4_MMAP_BO

#define DRM_VC4_MMAP_BO 0x04

◆ DRM_VC4_PARAM_SUPPORTS_BRANCHES

#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3

◆ DRM_VC4_PARAM_SUPPORTS_ETC1

#define DRM_VC4_PARAM_SUPPORTS_ETC1 4

◆ DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER

#define DRM_VC4_PARAM_SUPPORTS_FIXED_RCL_ORDER 6

◆ DRM_VC4_PARAM_SUPPORTS_MADVISE

#define DRM_VC4_PARAM_SUPPORTS_MADVISE 7

◆ DRM_VC4_PARAM_SUPPORTS_PERFMON

#define DRM_VC4_PARAM_SUPPORTS_PERFMON 8

◆ DRM_VC4_PARAM_SUPPORTS_THREADED_FS

#define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5

◆ DRM_VC4_PARAM_V3D_IDENT0

#define DRM_VC4_PARAM_V3D_IDENT0 0

◆ DRM_VC4_PARAM_V3D_IDENT1

#define DRM_VC4_PARAM_V3D_IDENT1 1

◆ DRM_VC4_PARAM_V3D_IDENT2

#define DRM_VC4_PARAM_V3D_IDENT2 2

◆ DRM_VC4_PERFMON_CREATE

#define DRM_VC4_PERFMON_CREATE 0x0c

◆ DRM_VC4_PERFMON_DESTROY

#define DRM_VC4_PERFMON_DESTROY 0x0d

◆ DRM_VC4_PERFMON_GET_VALUES

#define DRM_VC4_PERFMON_GET_VALUES 0x0e

◆ DRM_VC4_SET_TILING

#define DRM_VC4_SET_TILING 0x08

◆ DRM_VC4_SUBMIT_CL

#define DRM_VC4_SUBMIT_CL 0x00

◆ DRM_VC4_WAIT_BO

#define DRM_VC4_WAIT_BO 0x02

◆ DRM_VC4_WAIT_SEQNO

#define DRM_VC4_WAIT_SEQNO 0x01

◆ VC4_MADV_DONTNEED

#define VC4_MADV_DONTNEED 1

◆ VC4_MADV_WILLNEED

#define VC4_MADV_WILLNEED 0

◆ VC4_SUBMIT_CL_FIXED_RCL_ORDER

#define VC4_SUBMIT_CL_FIXED_RCL_ORDER (1 << 1)

◆ VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X

#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X (1 << 2)

◆ VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y

#define VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y (1 << 3)

◆ VC4_SUBMIT_CL_USE_CLEAR_COLOR

#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)

◆ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES

#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)

Enumeration Type Documentation

◆ anonymous enum

anonymous enum

Enumerator
VC4_PERFCNT_FEP_VALID_PRIMS_NO_RENDER
VC4_PERFCNT_FEP_VALID_PRIMS_RENDER
VC4_PERFCNT_FEP_CLIPPED_QUADS
VC4_PERFCNT_FEP_VALID_QUADS
VC4_PERFCNT_TLB_QUADS_NOT_PASSING_STENCIL
VC4_PERFCNT_TLB_QUADS_NOT_PASSING_Z_AND_STENCIL
VC4_PERFCNT_TLB_QUADS_PASSING_Z_AND_STENCIL
VC4_PERFCNT_TLB_QUADS_ZERO_COVERAGE
VC4_PERFCNT_TLB_QUADS_NON_ZERO_COVERAGE
VC4_PERFCNT_TLB_QUADS_WRITTEN_TO_COLOR_BUF
VC4_PERFCNT_PLB_PRIMS_OUTSIDE_VIEWPORT
VC4_PERFCNT_PLB_PRIMS_NEED_CLIPPING
VC4_PERFCNT_PSE_PRIMS_REVERSED
VC4_PERFCNT_QPU_TOTAL_IDLE_CYCLES
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_VERTEX_COORD_SHADING
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_FRAGMENT_SHADING
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_EXEC_VALID_INST
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_TMUS
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_SCOREBOARD
VC4_PERFCNT_QPU_TOTAL_CLK_CYCLES_WAITING_VARYINGS
VC4_PERFCNT_QPU_TOTAL_INST_CACHE_HIT
VC4_PERFCNT_QPU_TOTAL_INST_CACHE_MISS
VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_HIT
VC4_PERFCNT_QPU_TOTAL_UNIFORM_CACHE_MISS
VC4_PERFCNT_TMU_TOTAL_TEXT_QUADS_PROCESSED
VC4_PERFCNT_TMU_TOTAL_TEXT_CACHE_MISS
VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VDW_STALLED
VC4_PERFCNT_VPM_TOTAL_CLK_CYCLES_VCD_STALLED
VC4_PERFCNT_L2C_TOTAL_L2_CACHE_HIT
VC4_PERFCNT_L2C_TOTAL_L2_CACHE_MISS
VC4_PERFCNT_NUM_EVENTS

Classes

Macros

Enumerations