#include <stdint.h>
#include <list.h>
#include <Sync/spinlock.h>
#include <Hal/x86_64_sched.h>

Include dependency graph for xhci.h:

This graph shows which files directly or indirectly include this file:

Classes
struct	_xhci_cap_regs_

struct	_xhci_op_regs_

struct	_xhci_intr_reg_

struct	_xhci_runtime_regs_

struct	_xhci_doorbell_

struct	_xhci_trb_

struct	_xhci_ex_cap_

struct	_xhci_port_reg_

struct	_endp_

struct	_xhci_slot_

struct	_xhci_event_trb_

struct	_xhci_link_trb_

struct	_xhci_setup_trb_t_

struct	_xhci_data_trb_

struct	_xhci_status_trb_

struct	_xhci_ex_cap_protocol_

struct	__xhci_legacy_cap__

struct	_xhci_noop_trb_

struct	_xhci_erst_

struct	_xhci_input_ctx_

struct	_xhci_dev_

struct	_usb_hotplug_

struct	USB_REQUEST_PACKET

Macros
#define	XHCI_VENDOR_INTEL 0x8086

#define	XHCI_VENDOR_AMD 0x1022

#define	XHCI_VENDOR_ASMEDIA 0x1B21

#define	XHCI_VENDOR_LINUX_FOUNDATION 0x1D6A

#define	XHCI_VENDOR_NEC 0x1033

#define	XHCI_VENDOR_NVIDIA 0x10DE

#define	XHCI_VENDOR_FRESCO 0x1E31

#define	XHCI_VENDOR_VIA 0x1106

#define	XHCI_USB_CMD_INTE (1<<2)

#define	XHCI_USB_CMD_HSEE (1<<3)

#define	XHCI_USB_STS_HCH (1<<0)

#define	XHCI_USB_STS_HSE (1<<2)

#define	XHCI_USB_STS_EINT (1<<3)

#define	XHCI_USB_STS_PCD (1<<4)

#define	XHCI_USB_STS_SSS (1<<8)

#define	XHCI_USB_STS_RSS (1<<9)

#define	XHCI_USB_STS_SRE (1<<10)

#define	XHCI_USB_STS_CNR (1<<11)

#define	XHCI_USB_STS_HCE (1<<12)

#define	XHCI_USB_CFG_MXSLOT_ENABLE 0xFF

#define	XHCI_USB_CFG_U3_EN (1<<8)

#define	XHCI_USB_CFG_CINFO_EN (1 << 9)

#define	XHCI_USB_CCR_RCS (1<<0)

#define	XHCI_USB_CCR_CS (1<<1)

#define	XHCI_USB_CCR_CA (1<<2)

#define	XHCI_USB_CCR_CRR (1<<3)

#define	XHCI_USB_CCR_PTR_LO 0xFFFFFFC0

#define	XCHI_USB_CCR_PTR 0xFFFFFFFFFFFFFFC0

#define	XHCI_PORTSC_CCS (1<<0)

#define	XHCI_PORTSC_PED (1<<1)

#define	XHCI_PORTSC_OCA (1<<3)

#define	XHCI_PORTSC_PR (1<<4)

#define	XHCI_PORTSC_PP (1<<9)

#define	XHCI_PORTSC_CSC (1<<17)

#define	XHCI_PORTSC_PEC (1<<18)

#define	XHCI_PORTSC_PRC (1<<21)

#define	XHCI_PORTSC_WPR (1<<31)

#define	XHCI_INT_ERDP_BUSY (1<<3)

#define	XHCI_TRB_SIZE 16

#define	XHCI_EVENT_RING_SEG_TBL_ENTRY_SIZE 16

#define	XHCI_TRB_ENT 0x200000000

#define	XHCI_TRB_ISP 0x400000000

#define	XHCI_TRB_IOC 0x2000000000

#define	XHCI_TRB_IDT 0x4000000000

#define	XHCI_TRB_TRT(x) ((uint64_t)x << 48)

#define	XHCI_TRB_DIR_IN ((uint64_t)1 << 48)

#define	XHCI_DOORBELL_ENDPOINT_0 1

#define	XHCI_DOORBELL_ENDPOINT_1 2

#define	USB_SPEED_RESERVED 0

#define	USB_FULL_SPEED 1

#define	USB_LOW_SPEED 2

#define	USB_HIGH_SPEED 3

#define	USB_SUPER_SPEED 4

#define	USB_SUPER_SPEED_PLUS 5

#define	TRB_TRANSFER_NORMAL 1

#define	TRB_TRANSFER_SETUP_STAGE 2

#define	TRB_TRANSFER_DATA_STAGE 3

#define	TRB_TRANSFER_STATUS_STAGE 4

#define	TRB_TRANSFER_ISOCH 5

#define	TRB_TRANSFER_LINK 6

#define	TRB_TRANSFER_EVENT_DATA 7

#define	TRB_TRANSFER_NO_OP 8

#define	TRB_CMD_ENABLE_SLOT 9

#define	TRB_CMD_DISABLE_SLOT 10

#define	TRB_CMD_ADDRESS_DEV 11

#define	TRB_CMD_CONFIG_ENDPOINT 12

#define	TRB_CMD_EVALUATE_CTX 13

#define	TRB_CMD_RESET_ENDPOINT 14

#define	TRB_CMD_STOP_ENDPOINT 15

#define	TRB_CMD_SET_TR_DEQ_POINTER 16

#define	TRB_CMD_RESET_DEV 17

#define	TRB_CMD_FORCE_EVENT 18

#define	TRB_CMD_NEGOTIATE_BANDWIDTH 19

#define	TRB_CMD_SET_LATENCY_TOLERANCE_VALUE 20

#define	TRB_CMD_GET_PORT_BANDWIDTH 21

#define	TRB_CMD_FORCE_HEADER 22

#define	TRB_CMD_NO_OP 23

#define	TRB_CMD_GET_EXT_PROPERTY 24

#define	TRB_CMD_SET_EXT_PROPERTY 25

#define	TRB_EVENT_TRANSFER 32

#define	TRB_EVENT_CMD_COMPLETION 33

#define	TRB_EVENT_PORT_STATUS_CHANGE 34

#define	TRB_EVENT_BANDWIDTH_REQUEST 35

#define	TRB_EVENT_DOORBELL 36

#define	TRB_EVENT_HOST_CONTROLLER 37

#define	TRB_EVENT_DEVICE_NOTIFICATION 38

#define	TRB_EVENT_MFINDEX 39

#define	CTL_TRANSFER_TRT_NO_DATA 0

#define	CTL_TRANSFER_TRT_RESV 1

#define	CTL_TRANSFER_TRT_OUT_DATA 2

#define	CTL_TRANSFER_TRT_IN_DATA 3

#define	USB_SLOT_CTX_DWORD0(entries, hub, multi_tt, speed, route_string) (((entries & 0x1F) << 27) \| ((hub & 1) << 26) \| ((multi_tt & 1) << 25) \| ((speed & 0xF) << 20) \| (route_string & ((1 << 20) - 1)))

#define	USB_SLOT_CTX_DWORD1(num_ports, root_hub_port, max_exit_latency) (((num_ports & 0xFF) << 24) \| ((root_hub_port & 0xFF) << 16) \| (max_exit_latency & 0xFFFF))

#define	USB_ENDPOINT_CTX_DWORD0(max_esit_high, interval, lsa, max_p_streams, mult, ep_state) (((max_esit_high & 0xFF) << 24) \| ((interval & 0xFF) << 16) \| ((lsa & 1) << 15) \| ((max_p_streams & 0x1F) << 10) \| ((mult & 0x3) << 8) \| (ep_state & 0x7))

#define	USB_ENDPOINT_CTX_DWORD1(max_packet_size, max_burst_size, hid, ep_type, cerr) (((max_packet_size & 0xFFFF) << 16) \| ((max_burst_size & 0xFF) << 8) \| ((hid & 1) << 7) \| ((ep_type & 0x7) << 3) \| ((cerr & 0x3) << 1))

#define	USB_ENDPOINT_CTX_DWORD2(trdp, dcs) ((trdp & 0xFFFFFFFF) \| (dcs & 1))

#define	USB_ENDPOINT_CTX_DWORD3(trdp) ((trdp >> 32) & 0xFFFFFFFF)

#define	USB_ENDPOINT_CTX_DWORD4(max_esit_lo, average_trb_len) (((max_esit_lo & 0xFFFF) << 16) \| (average_trb_len & 0xFFFF))

Typedefs
typedef void(*	endpoint_callback) (void dev, void slot, void *Endp)

typedef struct _xhci_cap_regs_	xhci_cap_regs_t

typedef struct _xhci_op_regs_	xhci_op_regs_t

typedef struct _xhci_intr_reg_	xhci_interrupter_reg_t

typedef struct _xhci_runtime_regs_	xhci_runtime_regs_t

typedef struct _xhci_doorbell_	xhci_doorbell_regs_t

typedef struct _xhci_trb_	xhci_trb_t

typedef struct _xhci_ex_cap_	xhci_ext_cap_t

typedef struct _xhci_port_reg_	xhci_port_regs_t

typedef struct _endp_	XHCIEndpoint

typedef struct _xhci_slot_	XHCISlot

typedef struct _xhci_event_trb_	xhci_event_trb_t

typedef struct _xhci_link_trb_	xhci_link_trb_t

typedef struct _xhci_setup_trb_t_	xhci_setup_trb_t

typedef struct _xhci_data_trb_	xhci_data_trb_t

typedef struct _xhci_status_trb_	xhci_status_trb_t

typedef struct _xhci_ex_cap_protocol_	xhci_ex_cap_protocol_t

typedef struct __xhci_legacy_cap__	xhci_legacy_cap_t

typedef struct _xhci_noop_trb_	xhci_noop_cmd_trb_t

typedef struct _xhci_erst_	xhci_erst_t

typedef struct _xhci_input_ctx_	XHCIInputContext

typedef struct _xhci_dev_	XHCIDevice

typedef struct _usb_hotplug_	USBHotPlug

Functions
XHCIEndpoint *	XHCISlotGetEP_DCI (XHCISlot *slot, uint8_t endp_num)

XHCISlot *	XHCIGetSlotByID (XHCIDevice *dev, uint8_t slot_id)

XHCIDevice *	XHCIGetHost ()

void	XHCIAddSlot (XHCIDevice dev, XHCISlot slot)

void	XHCISlotRemove (XHCIDevice *dev, uint8_t slot_id)

void	XHCIRingDoorbellHost (XHCIDevice *dev)

int	XHCIPollEvent (XHCIDevice *usb_device, int trb_type)

void	XHCIRingDoorbellSlot (XHCIDevice *dev, uint8_t slot, uint32_t endpoint)

void	XHCISendCmdToHost (XHCIDevice *dev, uint32_t param1, uint32_t param2, uint32_t status, uint32_t ctrl)

void	XHCISendCmdOtherEP (XHCISlot *slot, uint8_t endp_num, uint32_t param1, uint32_t param2, uint32_t status, uint32_t ctrl)

void	XHCISendCmdDefaultEP (XHCISlot *slot, uint32_t param1, uint32_t param2, uint32_t status, uint32_t ctrl)

void	XHCIEvaluateContextCmd (XHCIDevice *dev, uint64_t input_ctx_ptr, uint8_t slot_id)

void	XHCIConfigureEndpoint (XHCIDevice *dev, uint64_t input_ctx_ptr, uint8_t slot_id)

void	XHCISendAddressDevice (XHCIDevice dev, XHCISlot slot, uint8_t bsr, uint64_t input_ctx_ptr, uint8_t slot_id)

void	XHCICreateSetupTRB (XHCISlot *slot, uint8_t rType, uint8_t bRequest, uint16_t value, uint16_t wIndex, uint16_t wLength, uint8_t trt)

void	XHCICreateDataTRB (XHCISlot *slot, uint64_t buffer, uint16_t size, bool in_direction)

void	XHCICreateStatusTRB (XHCISlot *slot, bool in_direction)

void	XHCIEnableSlot (XHCIDevice *dev, uint8_t slot_type)

void	XHCIDisableSlot (XHCIDevice *dev, uint8_t slot_num)

void	XHCISendNoopCmd (XHCIDevice *dev)

void	XHCISendControlCmd (XHCIDevice dev, XHCISlot slot, uint8_t slot_id, const USB_REQUEST_PACKET *request, uint64_t buffer_addr, const size_t len, uint8_t trt=CTL_TRANSFER_TRT_IN_DATA)

void	XHCISendNormalTRB (XHCIDevice dev, XHCISlot slot, uint64_t data_buffer, uint16_t data_len, XHCIEndpoint *ep)

void	XHCIBulkTransfer (XHCIDevice dev, XHCISlot slot, uint64_t buffer, uint16_t data_len, XHCIEndpoint *ep_)

size_t	XHCIGetMaxPacketSize (uint8_t speed)

Macro Definition Documentation

◆ CTL_TRANSFER_TRT_IN_DATA

#define CTL_TRANSFER_TRT_IN_DATA 3

◆ CTL_TRANSFER_TRT_NO_DATA

#define CTL_TRANSFER_TRT_NO_DATA 0

◆ CTL_TRANSFER_TRT_OUT_DATA

#define CTL_TRANSFER_TRT_OUT_DATA 2

◆ CTL_TRANSFER_TRT_RESV

#define CTL_TRANSFER_TRT_RESV 1

◆ TRB_CMD_ADDRESS_DEV

#define TRB_CMD_ADDRESS_DEV 11

◆ TRB_CMD_CONFIG_ENDPOINT

#define TRB_CMD_CONFIG_ENDPOINT 12

◆ TRB_CMD_DISABLE_SLOT

#define TRB_CMD_DISABLE_SLOT 10

◆ TRB_CMD_ENABLE_SLOT

#define TRB_CMD_ENABLE_SLOT 9

◆ TRB_CMD_EVALUATE_CTX

#define TRB_CMD_EVALUATE_CTX 13

◆ TRB_CMD_FORCE_EVENT

#define TRB_CMD_FORCE_EVENT 18

◆ TRB_CMD_FORCE_HEADER

#define TRB_CMD_FORCE_HEADER 22

◆ TRB_CMD_GET_EXT_PROPERTY

#define TRB_CMD_GET_EXT_PROPERTY 24

◆ TRB_CMD_GET_PORT_BANDWIDTH

#define TRB_CMD_GET_PORT_BANDWIDTH 21

◆ TRB_CMD_NEGOTIATE_BANDWIDTH

#define TRB_CMD_NEGOTIATE_BANDWIDTH 19

◆ TRB_CMD_NO_OP

#define TRB_CMD_NO_OP 23

◆ TRB_CMD_RESET_DEV

#define TRB_CMD_RESET_DEV 17

◆ TRB_CMD_RESET_ENDPOINT

#define TRB_CMD_RESET_ENDPOINT 14

◆ TRB_CMD_SET_EXT_PROPERTY

#define TRB_CMD_SET_EXT_PROPERTY 25

◆ TRB_CMD_SET_LATENCY_TOLERANCE_VALUE

#define TRB_CMD_SET_LATENCY_TOLERANCE_VALUE 20

◆ TRB_CMD_SET_TR_DEQ_POINTER

#define TRB_CMD_SET_TR_DEQ_POINTER 16

◆ TRB_CMD_STOP_ENDPOINT

#define TRB_CMD_STOP_ENDPOINT 15

◆ TRB_EVENT_BANDWIDTH_REQUEST

#define TRB_EVENT_BANDWIDTH_REQUEST 35

◆ TRB_EVENT_CMD_COMPLETION

#define TRB_EVENT_CMD_COMPLETION 33

◆ TRB_EVENT_DEVICE_NOTIFICATION

#define TRB_EVENT_DEVICE_NOTIFICATION 38

◆ TRB_EVENT_DOORBELL

#define TRB_EVENT_DOORBELL 36

◆ TRB_EVENT_HOST_CONTROLLER

#define TRB_EVENT_HOST_CONTROLLER 37

◆ TRB_EVENT_MFINDEX

#define TRB_EVENT_MFINDEX 39

◆ TRB_EVENT_PORT_STATUS_CHANGE

#define TRB_EVENT_PORT_STATUS_CHANGE 34

◆ TRB_EVENT_TRANSFER

#define TRB_EVENT_TRANSFER 32

◆ TRB_TRANSFER_DATA_STAGE

#define TRB_TRANSFER_DATA_STAGE 3

◆ TRB_TRANSFER_EVENT_DATA

#define TRB_TRANSFER_EVENT_DATA 7

◆ TRB_TRANSFER_ISOCH

#define TRB_TRANSFER_ISOCH 5

◆ TRB_TRANSFER_LINK

#define TRB_TRANSFER_LINK 6

◆ TRB_TRANSFER_NO_OP

#define TRB_TRANSFER_NO_OP 8

◆ TRB_TRANSFER_NORMAL

#define TRB_TRANSFER_NORMAL 1

◆ TRB_TRANSFER_SETUP_STAGE

#define TRB_TRANSFER_SETUP_STAGE 2

◆ TRB_TRANSFER_STATUS_STAGE

#define TRB_TRANSFER_STATUS_STAGE 4

◆ USB_ENDPOINT_CTX_DWORD0

#define USB_ENDPOINT_CTX_DWORD0	(	max_esit_high,
		interval,
		lsa,
		max_p_streams,
		mult,
		ep_state
	)	(((max_esit_high & 0xFF) << 24) \| ((interval & 0xFF) << 16) \| ((lsa & 1) << 15) \| ((max_p_streams & 0x1F) << 10) \| ((mult & 0x3) << 8) \| (ep_state & 0x7))

◆ USB_ENDPOINT_CTX_DWORD1

#define USB_ENDPOINT_CTX_DWORD1	(	max_packet_size,
		max_burst_size,
		hid,
		ep_type,
		cerr
	)	(((max_packet_size & 0xFFFF) << 16) \| ((max_burst_size & 0xFF) << 8) \| ((hid & 1) << 7) \| ((ep_type & 0x7) << 3) \| ((cerr & 0x3) << 1))

◆ USB_ENDPOINT_CTX_DWORD2

#define USB_ENDPOINT_CTX_DWORD2	(	trdp,
		dcs
	)	((trdp & 0xFFFFFFFF) \| (dcs & 1))

◆ USB_ENDPOINT_CTX_DWORD3

#define USB_ENDPOINT_CTX_DWORD3 ( trdp ) ((trdp >> 32) & 0xFFFFFFFF)

◆ USB_ENDPOINT_CTX_DWORD4

#define USB_ENDPOINT_CTX_DWORD4	(	max_esit_lo,
		average_trb_len
	)	(((max_esit_lo & 0xFFFF) << 16) \| (average_trb_len & 0xFFFF))

◆ USB_FULL_SPEED

#define USB_FULL_SPEED 1

◆ USB_HIGH_SPEED

#define USB_HIGH_SPEED 3

◆ USB_LOW_SPEED

#define USB_LOW_SPEED 2

◆ USB_SLOT_CTX_DWORD0

#define USB_SLOT_CTX_DWORD0	(	entries,
		hub,
		multi_tt,
		speed,
		route_string
	)	(((entries & 0x1F) << 27) \| ((hub & 1) << 26) \| ((multi_tt & 1) << 25) \| ((speed & 0xF) << 20) \| (route_string & ((1 << 20) - 1)))

◆ USB_SLOT_CTX_DWORD1

#define USB_SLOT_CTX_DWORD1	(	num_ports,
		root_hub_port,
		max_exit_latency
	)	(((num_ports & 0xFF) << 24) \| ((root_hub_port & 0xFF) << 16) \| (max_exit_latency & 0xFFFF))

◆ USB_SPEED_RESERVED

#define USB_SPEED_RESERVED 0

◆ USB_SUPER_SPEED

#define USB_SUPER_SPEED 4

◆ USB_SUPER_SPEED_PLUS

#define USB_SUPER_SPEED_PLUS 5

◆ XCHI_USB_CCR_PTR

#define XCHI_USB_CCR_PTR 0xFFFFFFFFFFFFFFC0

◆ XHCI_DOORBELL_ENDPOINT_0

#define XHCI_DOORBELL_ENDPOINT_0 1

◆ XHCI_DOORBELL_ENDPOINT_1

#define XHCI_DOORBELL_ENDPOINT_1 2

◆ XHCI_EVENT_RING_SEG_TBL_ENTRY_SIZE

#define XHCI_EVENT_RING_SEG_TBL_ENTRY_SIZE 16

◆ XHCI_INT_ERDP_BUSY

#define XHCI_INT_ERDP_BUSY (1<<3)

◆ XHCI_PORTSC_CCS

#define XHCI_PORTSC_CCS (1<<0)

◆ XHCI_PORTSC_CSC

#define XHCI_PORTSC_CSC (1<<17)

◆ XHCI_PORTSC_OCA

#define XHCI_PORTSC_OCA (1<<3)

◆ XHCI_PORTSC_PEC

#define XHCI_PORTSC_PEC (1<<18)

◆ XHCI_PORTSC_PED

#define XHCI_PORTSC_PED (1<<1)

◆ XHCI_PORTSC_PP

#define XHCI_PORTSC_PP (1<<9)

◆ XHCI_PORTSC_PR

#define XHCI_PORTSC_PR (1<<4)

◆ XHCI_PORTSC_PRC

#define XHCI_PORTSC_PRC (1<<21)

◆ XHCI_PORTSC_WPR

#define XHCI_PORTSC_WPR (1<<31)

◆ XHCI_TRB_DIR_IN

#define XHCI_TRB_DIR_IN ((uint64_t)1 << 48)

◆ XHCI_TRB_ENT

#define XHCI_TRB_ENT 0x200000000

◆ XHCI_TRB_IDT

#define XHCI_TRB_IDT 0x4000000000

◆ XHCI_TRB_IOC

#define XHCI_TRB_IOC 0x2000000000

◆ XHCI_TRB_ISP

#define XHCI_TRB_ISP 0x400000000

◆ XHCI_TRB_SIZE

#define XHCI_TRB_SIZE 16

◆ XHCI_TRB_TRT

#define XHCI_TRB_TRT ( x ) ((uint64_t)x << 48)

◆ XHCI_USB_CCR_CA

#define XHCI_USB_CCR_CA (1<<2)

◆ XHCI_USB_CCR_CRR

#define XHCI_USB_CCR_CRR (1<<3)

◆ XHCI_USB_CCR_CS

#define XHCI_USB_CCR_CS (1<<1)

◆ XHCI_USB_CCR_PTR_LO

#define XHCI_USB_CCR_PTR_LO 0xFFFFFFC0

◆ XHCI_USB_CCR_RCS

#define XHCI_USB_CCR_RCS (1<<0)

◆ XHCI_USB_CFG_CINFO_EN

#define XHCI_USB_CFG_CINFO_EN (1 << 9)

◆ XHCI_USB_CFG_MXSLOT_ENABLE

#define XHCI_USB_CFG_MXSLOT_ENABLE 0xFF

◆ XHCI_USB_CFG_U3_EN

#define XHCI_USB_CFG_U3_EN (1<<8)

◆ XHCI_USB_CMD_HSEE

#define XHCI_USB_CMD_HSEE (1<<3)

◆ XHCI_USB_CMD_INTE

#define XHCI_USB_CMD_INTE (1<<2)

◆ XHCI_USB_STS_CNR

#define XHCI_USB_STS_CNR (1<<11)

◆ XHCI_USB_STS_EINT

#define XHCI_USB_STS_EINT (1<<3)

◆ XHCI_USB_STS_HCE

#define XHCI_USB_STS_HCE (1<<12)

◆ XHCI_USB_STS_HCH

#define XHCI_USB_STS_HCH (1<<0)

◆ XHCI_USB_STS_HSE

#define XHCI_USB_STS_HSE (1<<2)

◆ XHCI_USB_STS_PCD

#define XHCI_USB_STS_PCD (1<<4)

◆ XHCI_USB_STS_RSS

#define XHCI_USB_STS_RSS (1<<9)

◆ XHCI_USB_STS_SRE

#define XHCI_USB_STS_SRE (1<<10)

◆ XHCI_USB_STS_SSS

#define XHCI_USB_STS_SSS (1<<8)

◆ XHCI_VENDOR_AMD

#define XHCI_VENDOR_AMD 0x1022

◆ XHCI_VENDOR_ASMEDIA

#define XHCI_VENDOR_ASMEDIA 0x1B21

◆ XHCI_VENDOR_FRESCO

#define XHCI_VENDOR_FRESCO 0x1E31

◆ XHCI_VENDOR_INTEL

#define XHCI_VENDOR_INTEL 0x8086

BSD 2-Clause License

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

◆ XHCI_VENDOR_LINUX_FOUNDATION

#define XHCI_VENDOR_LINUX_FOUNDATION 0x1D6A

◆ XHCI_VENDOR_NEC

#define XHCI_VENDOR_NEC 0x1033

◆ XHCI_VENDOR_NVIDIA

#define XHCI_VENDOR_NVIDIA 0x10DE

◆ XHCI_VENDOR_VIA

#define XHCI_VENDOR_VIA 0x1106

Typedef Documentation

◆ endpoint_callback

typedef void(* endpoint_callback) (void *dev, void *slot, void *Endp)

◆ USBHotPlug

typedef struct _usb_hotplug_ USBHotPlug

◆ xhci_cap_regs_t

typedef struct _xhci_cap_regs_ xhci_cap_regs_t

◆ xhci_data_trb_t

typedef struct _xhci_data_trb_ xhci_data_trb_t

◆ xhci_doorbell_regs_t

typedef struct _xhci_doorbell_ xhci_doorbell_regs_t

◆ xhci_erst_t

typedef struct _xhci_erst_ xhci_erst_t

◆ xhci_event_trb_t

typedef struct _xhci_event_trb_ xhci_event_trb_t

◆ xhci_ex_cap_protocol_t

typedef struct _xhci_ex_cap_protocol_ xhci_ex_cap_protocol_t

◆ xhci_ext_cap_t

typedef struct _xhci_ex_cap_ xhci_ext_cap_t

◆ xhci_interrupter_reg_t

typedef struct _xhci_intr_reg_ xhci_interrupter_reg_t

◆ xhci_legacy_cap_t

typedef struct __xhci_legacy_cap__ xhci_legacy_cap_t

◆ xhci_link_trb_t

typedef struct _xhci_link_trb_ xhci_link_trb_t

◆ xhci_noop_cmd_trb_t

typedef struct _xhci_noop_trb_ xhci_noop_cmd_trb_t

◆ xhci_op_regs_t

typedef struct _xhci_op_regs_ xhci_op_regs_t

◆ xhci_port_regs_t

typedef struct _xhci_port_reg_ xhci_port_regs_t

◆ xhci_runtime_regs_t

typedef struct _xhci_runtime_regs_ xhci_runtime_regs_t

◆ xhci_setup_trb_t

typedef struct _xhci_setup_trb_t_ xhci_setup_trb_t

◆ xhci_status_trb_t

typedef struct _xhci_status_trb_ xhci_status_trb_t

◆ xhci_trb_t

typedef struct _xhci_trb_ xhci_trb_t

◆ XHCIDevice

typedef struct _xhci_dev_ XHCIDevice

◆ XHCIEndpoint

typedef struct _endp_ XHCIEndpoint

◆ XHCIInputContext

typedef struct _xhci_input_ctx_ XHCIInputContext

◆ XHCISlot

typedef struct _xhci_slot_ XHCISlot

Function Documentation

◆ XHCIAddSlot()

void XHCIAddSlot	(	XHCIDevice *	dev,
		XHCISlot *	slot
	)

extern

◆ XHCIBulkTransfer()

void XHCIBulkTransfer	(	XHCIDevice *	dev,
		XHCISlot *	slot,
		uint64_t	buffer,
		uint16_t	data_len,
		XHCIEndpoint *	ep_
	)

extern

◆ XHCIConfigureEndpoint()

void XHCIConfigureEndpoint	(	XHCIDevice *	dev,
		uint64_t	input_ctx_ptr,
		uint8_t	slot_id
	)

extern

◆ XHCICreateDataTRB()

void XHCICreateDataTRB	(	XHCISlot *	slot,
		uint64_t	buffer,
		uint16_t	size,
		bool	in_direction
	)

extern

◆ XHCICreateSetupTRB()

void XHCICreateSetupTRB	(	XHCISlot *	slot,
		uint8_t	rType,
		uint8_t	bRequest,
		uint16_t	value,
		uint16_t	wIndex,
		uint16_t	wLength,
		uint8_t	trt
	)

extern

◆ XHCICreateStatusTRB()

void XHCICreateStatusTRB	(	XHCISlot *	slot,
		bool	in_direction
	)

extern

◆ XHCIDisableSlot()

void XHCIDisableSlot	(	XHCIDevice *	dev,
		uint8_t	slot_num
	)

extern

◆ XHCIEnableSlot()

void XHCIEnableSlot	(	XHCIDevice *	dev,
		uint8_t	slot_type
	)

extern

◆ XHCIEvaluateContextCmd()

void XHCIEvaluateContextCmd	(	XHCIDevice *	dev,
		uint64_t	input_ctx_ptr,
		uint8_t	slot_id
	)

extern

BSD 2-Clause License

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

◆ XHCIGetHost()

XHCIDevice * XHCIGetHost ( )

extern

◆ XHCIGetMaxPacketSize()

size_t XHCIGetMaxPacketSize ( uint8_t speed )

extern

◆ XHCIGetSlotByID()

XHCISlot * XHCIGetSlotByID	(	XHCIDevice *	dev,
		uint8_t	slot_id
	)

extern

◆ XHCIPollEvent()

int XHCIPollEvent	(	XHCIDevice *	usb_device,
		int	trb_type
	)

extern

here we need a delay, while using VirtualBox *‍/

◆ XHCIRingDoorbellHost()

void XHCIRingDoorbellHost ( XHCIDevice * dev )

extern

◆ XHCIRingDoorbellSlot()

void XHCIRingDoorbellSlot	(	XHCIDevice *	dev,
		uint8_t	slot,
		uint32_t	endpoint
	)

extern

◆ XHCISendAddressDevice()

void XHCISendAddressDevice	(	XHCIDevice *	dev,
		XHCISlot *	slot,
		uint8_t	bsr,
		uint64_t	input_ctx_ptr,
		uint8_t	slot_id
	)

extern

◆ XHCISendCmdDefaultEP()

void XHCISendCmdDefaultEP	(	XHCISlot *	slot,
		uint32_t	param1,
		uint32_t	param2,
		uint32_t	status,
		uint32_t	ctrl
	)

extern

◆ XHCISendCmdOtherEP()

void XHCISendCmdOtherEP	(	XHCISlot *	slot,
		uint8_t	endp_num,
		uint32_t	param1,
		uint32_t	param2,
		uint32_t	status,
		uint32_t	ctrl
	)

extern

◆ XHCISendCmdToHost()

void XHCISendCmdToHost	(	XHCIDevice *	dev,
		uint32_t	param1,
		uint32_t	param2,
		uint32_t	status,
		uint32_t	ctrl
	)

extern

◆ XHCISendControlCmd()

void XHCISendControlCmd	(	XHCIDevice *	dev,
		XHCISlot *	slot,
		uint8_t	slot_id,
		const USB_REQUEST_PACKET *	request,
		uint64_t	buffer_addr,
		const size_t	len,
		uint8_t	trt = `CTL_TRANSFER_TRT_IN_DATA`
	)

extern

◆ XHCISendNoopCmd()

void XHCISendNoopCmd ( XHCIDevice * dev )

extern

◆ XHCISendNormalTRB()

void XHCISendNormalTRB	(	XHCIDevice *	dev,
		XHCISlot *	slot,
		uint64_t	data_buffer,
		uint16_t	data_len,
		XHCIEndpoint *	ep
	)

extern

◆ XHCISlotGetEP_DCI()

XHCIEndpoint * XHCISlotGetEP_DCI	(	XHCISlot *	slot,
		uint8_t	endp_num
	)

extern

BSD 2-Clause License

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

◆ XHCISlotRemove()

void XHCISlotRemove	(	XHCIDevice *	dev,
		uint8_t	slot_id
	)

extern

Classes

Macros

Typedefs

Functions

Macro Definition Documentation

◆ CTL_TRANSFER_TRT_IN_DATA

◆ CTL_TRANSFER_TRT_NO_DATA

◆ CTL_TRANSFER_TRT_OUT_DATA

◆ CTL_TRANSFER_TRT_RESV

◆ TRB_CMD_ADDRESS_DEV

◆ TRB_CMD_CONFIG_ENDPOINT

◆ TRB_CMD_DISABLE_SLOT

◆ TRB_CMD_ENABLE_SLOT

◆ TRB_CMD_EVALUATE_CTX

◆ TRB_CMD_FORCE_EVENT

◆ TRB_CMD_FORCE_HEADER

◆ TRB_CMD_GET_EXT_PROPERTY

◆ TRB_CMD_GET_PORT_BANDWIDTH

◆ TRB_CMD_NEGOTIATE_BANDWIDTH

◆ TRB_CMD_NO_OP

◆ TRB_CMD_RESET_DEV

◆ TRB_CMD_RESET_ENDPOINT

◆ TRB_CMD_SET_EXT_PROPERTY

◆ TRB_CMD_SET_LATENCY_TOLERANCE_VALUE

◆ TRB_CMD_SET_TR_DEQ_POINTER

◆ TRB_CMD_STOP_ENDPOINT

◆ TRB_EVENT_BANDWIDTH_REQUEST

◆ TRB_EVENT_CMD_COMPLETION

◆ TRB_EVENT_DEVICE_NOTIFICATION

◆ TRB_EVENT_DOORBELL

◆ TRB_EVENT_HOST_CONTROLLER

◆ TRB_EVENT_MFINDEX

◆ TRB_EVENT_PORT_STATUS_CHANGE

◆ TRB_EVENT_TRANSFER

◆ TRB_TRANSFER_DATA_STAGE

◆ TRB_TRANSFER_EVENT_DATA

◆ TRB_TRANSFER_ISOCH

◆ TRB_TRANSFER_LINK

◆ TRB_TRANSFER_NO_OP

◆ TRB_TRANSFER_NORMAL

◆ TRB_TRANSFER_SETUP_STAGE

◆ TRB_TRANSFER_STATUS_STAGE

◆ USB_ENDPOINT_CTX_DWORD0

◆ USB_ENDPOINT_CTX_DWORD1

◆ USB_ENDPOINT_CTX_DWORD2

◆ USB_ENDPOINT_CTX_DWORD3

◆ USB_ENDPOINT_CTX_DWORD4

◆ USB_FULL_SPEED

◆ USB_HIGH_SPEED

◆ USB_LOW_SPEED

◆ USB_SLOT_CTX_DWORD0

◆ USB_SLOT_CTX_DWORD1

◆ USB_SPEED_RESERVED

◆ USB_SUPER_SPEED

◆ USB_SUPER_SPEED_PLUS

◆ XCHI_USB_CCR_PTR

◆ XHCI_DOORBELL_ENDPOINT_0

◆ XHCI_DOORBELL_ENDPOINT_1

◆ XHCI_EVENT_RING_SEG_TBL_ENTRY_SIZE

◆ XHCI_INT_ERDP_BUSY

◆ XHCI_PORTSC_CCS

◆ XHCI_PORTSC_CSC

◆ XHCI_PORTSC_OCA

◆ XHCI_PORTSC_PEC

◆ XHCI_PORTSC_PED

◆ XHCI_PORTSC_PP

◆ XHCI_PORTSC_PR

◆ XHCI_PORTSC_PRC

◆ XHCI_PORTSC_WPR

◆ XHCI_TRB_DIR_IN

◆ XHCI_TRB_ENT

◆ XHCI_TRB_IDT

◆ XHCI_TRB_IOC

◆ XHCI_TRB_ISP

◆ XHCI_TRB_SIZE

◆ XHCI_TRB_TRT

◆ XHCI_USB_CCR_CA

◆ XHCI_USB_CCR_CRR

◆ XHCI_USB_CCR_CS

◆ XHCI_USB_CCR_PTR_LO