amdxdna_accel.h File Reference

#include <linux/stddef.h>
#include "drm.h"

Include dependency graph for amdxdna_accel.h:

Go to the source code of this file.

Classes
struct	amdxdna_qos_info
struct	amdxdna_drm_create_hwctx
struct	amdxdna_drm_destroy_hwctx
struct	amdxdna_cu_config
struct	amdxdna_hwctx_param_config_cu
struct	amdxdna_drm_config_hwctx
struct	amdxdna_drm_va_entry
struct	amdxdna_drm_va_tbl
struct	amdxdna_drm_create_bo
struct	amdxdna_drm_get_bo_info
struct	amdxdna_drm_sync_bo
struct	amdxdna_drm_exec_cmd
struct	amdxdna_drm_wait_cmd
struct	amdxdna_drm_query_aie_status
struct	amdxdna_drm_query_aie_version
struct	amdxdna_drm_query_aie_tile_metadata
struct	amdxdna_drm_query_aie_metadata
struct	amdxdna_drm_query_clock
struct	amdxdna_drm_query_clock_metadata
struct	amdxdna_drm_query_sensor
struct	amdxdna_drm_query_hwctx
struct	amdxdna_drm_get_power_mode
struct	amdxdna_drm_query_firmware_version
struct	amdxdna_drm_get_resource_info
struct	amdxdna_drm_attribute_state
struct	amdxdna_drm_query_telemetry_header
struct	amdxdna_drm_get_info
struct	amdxdna_drm_hwctx_entry
struct	amdxdna_async_error
struct	amdxdna_drm_bo_usage
struct	amdxdna_drm_get_array
struct	amdxdna_drm_set_state
struct	amdxdna_drm_set_power_mode

Macros
#define	AMDXDNA_INVALID_CMD_HANDLE   (~0UL)
#define	AMDXDNA_INVALID_ADDR   (~0UL)
#define	AMDXDNA_INVALID_CTX_HANDLE   0
#define	AMDXDNA_INVALID_BO_HANDLE   0
#define	AMDXDNA_INVALID_FENCE_HANDLE   0
#define	AMDXDNA_INVALID_DOORBELL_OFFSET   (~0U)
#define	AMDXDNA_QOS_REALTIME_PRIORITY   0x100
#define	AMDXDNA_QOS_HIGH_PRIORITY   0x180
#define	AMDXDNA_QOS_NORMAL_PRIORITY   0x200
#define	AMDXDNA_QOS_LOW_PRIORITY   0x280
#define	SYNC_DIRECT_TO_DEVICE   0U
#define	SYNC_DIRECT_FROM_DEVICE   1U

Enumerations
enum	amdxdna_device_type { AMDXDNA_DEV_TYPE_UNKNOWN = -1 , AMDXDNA_DEV_TYPE_KMQ = 0 , AMDXDNA_DEV_TYPE_UMQ = 1 , AMDXDNA_DEV_TYPE_PF = 2 }
enum	amdxdna_drm_ioctl_id {   DRM_AMDXDNA_CREATE_HWCTX , DRM_AMDXDNA_DESTROY_HWCTX , DRM_AMDXDNA_CONFIG_HWCTX , DRM_AMDXDNA_CREATE_BO ,   DRM_AMDXDNA_GET_BO_INFO , DRM_AMDXDNA_SYNC_BO , DRM_AMDXDNA_EXEC_CMD , DRM_AMDXDNA_GET_INFO ,   DRM_AMDXDNA_SET_STATE , DRM_AMDXDNA_WAIT_CMD , DRM_AMDXDNA_GET_ARRAY }
enum	amdxdna_drm_config_hwctx_param { DRM_AMDXDNA_HWCTX_CONFIG_CU , DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF , DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF }
enum	amdxdna_bo_type {   AMDXDNA_BO_INVALID = 0 , AMDXDNA_BO_SHMEM = 1 , AMDXDNA_BO_SHARE = 1 , AMDXDNA_BO_DEV_HEAP = 2 ,   AMDXDNA_BO_DEV = 3 , AMDXDNA_BO_CMD = 4 }
enum	amdxdna_cmd_type { AMDXDNA_CMD_SUBMIT_EXEC_BUF = 0 , AMDXDNA_CMD_SUBMIT_DEPENDENCY , AMDXDNA_CMD_SUBMIT_SIGNAL }

: The clock name.
struct amdxdna_drm_query_clock - Metadata for a clock @freq_mhz: The clock frequency. @pad: Structure padding.
#define	AMDXDNA_HWCTX_STATE_IDLE   0
#define	AMDXDNA_HWCTX_STATE_ACTIVE   1
#define	DRM_AMDXDNA_HW_CONTEXT_ALL   0
#define	DRM_AMDXDNA_HW_LAST_ASYNC_ERR   2
#define	DRM_AMDXDNA_BO_USAGE   6
#define	DRM_IOCTL_AMDXDNA_CREATE_HWCTX
#define	DRM_IOCTL_AMDXDNA_DESTROY_HWCTX
#define	DRM_IOCTL_AMDXDNA_CONFIG_HWCTX
#define	DRM_IOCTL_AMDXDNA_CREATE_BO
#define	DRM_IOCTL_AMDXDNA_GET_BO_INFO
#define	DRM_IOCTL_AMDXDNA_SYNC_BO
#define	DRM_IOCTL_AMDXDNA_EXEC_CMD
#define	DRM_IOCTL_AMDXDNA_GET_INFO
#define	DRM_IOCTL_AMDXDNA_SET_STATE
#define	DRM_IOCTL_AMDXDNA_GET_ARRAY
#define	DRM_IOCTL_AMDXDNA_WAIT_CMD
enum	amdxdna_sensor_type { AMDXDNA_SENSOR_TYPE_POWER , AMDXDNA_SENSOR_TYPE_COLUMN_UTILIZATION }
enum	amdxdna_power_mode_type {   POWER_MODE_DEFAULT , POWER_MODE_LOW , POWER_MODE_MEDIUM , POWER_MODE_HIGH ,   POWER_MODE_TURBO }
enum	amdxdna_drm_get_param {   DRM_AMDXDNA_QUERY_AIE_STATUS , DRM_AMDXDNA_QUERY_AIE_METADATA , DRM_AMDXDNA_QUERY_AIE_VERSION , DRM_AMDXDNA_QUERY_CLOCK_METADATA ,   DRM_AMDXDNA_QUERY_SENSORS , DRM_AMDXDNA_QUERY_HW_CONTEXTS , DRM_AMDXDNA_QUERY_FIRMWARE_VERSION = 8 , DRM_AMDXDNA_GET_POWER_MODE ,   DRM_AMDXDNA_QUERY_TELEMETRY , DRM_AMDXDNA_GET_FORCE_PREEMPT_STATE , DRM_AMDXDNA_QUERY_RESOURCE_INFO , DRM_AMDXDNA_GET_FRAME_BOUNDARY_PREEMPT_STATE }
enum	amdxdna_drm_set_param {   DRM_AMDXDNA_SET_POWER_MODE , DRM_AMDXDNA_WRITE_AIE_MEM , DRM_AMDXDNA_WRITE_AIE_REG , DRM_AMDXDNA_SET_FORCE_PREEMPT ,   DRM_AMDXDNA_SET_FRAME_BOUNDARY_PREEMPT }

Macro Definition Documentation

AMDXDNA_HWCTX_STATE_ACTIVE

#define AMDXDNA_HWCTX_STATE_ACTIVE   1

AMDXDNA_HWCTX_STATE_IDLE

#define AMDXDNA_HWCTX_STATE_IDLE   0

AMDXDNA_INVALID_ADDR

#define AMDXDNA_INVALID_ADDR   (~0UL)

AMDXDNA_INVALID_BO_HANDLE

#define AMDXDNA_INVALID_BO_HANDLE   0

AMDXDNA_INVALID_CMD_HANDLE

#define AMDXDNA_INVALID_CMD_HANDLE   (~0UL)

AMDXDNA_INVALID_CTX_HANDLE

#define AMDXDNA_INVALID_CTX_HANDLE   0

AMDXDNA_INVALID_DOORBELL_OFFSET

#define AMDXDNA_INVALID_DOORBELL_OFFSET   (~0U)

AMDXDNA_INVALID_FENCE_HANDLE

#define AMDXDNA_INVALID_FENCE_HANDLE   0

AMDXDNA_QOS_HIGH_PRIORITY

#define AMDXDNA_QOS_HIGH_PRIORITY   0x180

AMDXDNA_QOS_LOW_PRIORITY

#define AMDXDNA_QOS_LOW_PRIORITY   0x280

AMDXDNA_QOS_NORMAL_PRIORITY

#define AMDXDNA_QOS_NORMAL_PRIORITY   0x200

AMDXDNA_QOS_REALTIME_PRIORITY

#define AMDXDNA_QOS_REALTIME_PRIORITY   0x100

DRM_AMDXDNA_BO_USAGE

#define DRM_AMDXDNA_BO_USAGE   6

DRM_AMDXDNA_HW_CONTEXT_ALL

#define DRM_AMDXDNA_HW_CONTEXT_ALL   0

DRM_AMDXDNA_HW_LAST_ASYNC_ERR

#define DRM_AMDXDNA_HW_LAST_ASYNC_ERR   2

DRM_IOCTL_AMDXDNA_CONFIG_HWCTX

#define DRM_IOCTL_AMDXDNA_CONFIG_HWCTX

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CONFIG_HWCTX, \
         struct amdxdna_drm_config_hwctx)

DRM_IOCTL_AMDXDNA_CREATE_BO

#define DRM_IOCTL_AMDXDNA_CREATE_BO

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_BO, \
         struct amdxdna_drm_create_bo)

DRM_IOCTL_AMDXDNA_CREATE_HWCTX

#define DRM_IOCTL_AMDXDNA_CREATE_HWCTX

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, \
         struct amdxdna_drm_create_hwctx)

DRM_IOCTL_AMDXDNA_DESTROY_HWCTX

#define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, \
         struct amdxdna_drm_destroy_hwctx)

DRM_IOCTL_AMDXDNA_EXEC_CMD

#define DRM_IOCTL_AMDXDNA_EXEC_CMD

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_EXEC_CMD, \
         struct amdxdna_drm_exec_cmd)

DRM_IOCTL_AMDXDNA_GET_ARRAY

#define DRM_IOCTL_AMDXDNA_GET_ARRAY

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_ARRAY, \
         struct amdxdna_drm_get_array)

DRM_IOCTL_AMDXDNA_GET_BO_INFO

#define DRM_IOCTL_AMDXDNA_GET_BO_INFO

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_BO_INFO, \
         struct amdxdna_drm_get_bo_info)

DRM_IOCTL_AMDXDNA_GET_INFO

#define DRM_IOCTL_AMDXDNA_GET_INFO

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_INFO, \
         struct amdxdna_drm_get_info)

DRM_IOCTL_AMDXDNA_SET_STATE

#define DRM_IOCTL_AMDXDNA_SET_STATE

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SET_STATE, \
         struct amdxdna_drm_set_state)

DRM_IOCTL_AMDXDNA_SYNC_BO

#define DRM_IOCTL_AMDXDNA_SYNC_BO

Value:

    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SYNC_BO, \
         struct amdxdna_drm_sync_bo)

DRM_IOCTL_AMDXDNA_WAIT_CMD

#define DRM_IOCTL_AMDXDNA_WAIT_CMD

Value:

    DRM_IOW(DRM_COMMAND_BASE + DRM_AMDXDNA_WAIT_CMD, \
        struct amdxdna_drm_wait_cmd)

SYNC_DIRECT_FROM_DEVICE

#define SYNC_DIRECT_FROM_DEVICE   1U

SYNC_DIRECT_TO_DEVICE

#define SYNC_DIRECT_TO_DEVICE   0U

Enumeration Type Documentation

amdxdna_bo_type

enum amdxdna_bo_type

Enumerator
AMDXDNA_BO_INVALID
AMDXDNA_BO_SHMEM
AMDXDNA_BO_SHARE
AMDXDNA_BO_DEV_HEAP
AMDXDNA_BO_DEV
AMDXDNA_BO_CMD

amdxdna_cmd_type

enum amdxdna_cmd_type

Enumerator
AMDXDNA_CMD_SUBMIT_EXEC_BUF
AMDXDNA_CMD_SUBMIT_DEPENDENCY
AMDXDNA_CMD_SUBMIT_SIGNAL

amdxdna_device_type

enum amdxdna_device_type

Enumerator
AMDXDNA_DEV_TYPE_UNKNOWN
AMDXDNA_DEV_TYPE_KMQ
AMDXDNA_DEV_TYPE_UMQ
AMDXDNA_DEV_TYPE_PF

amdxdna_drm_config_hwctx_param

enum amdxdna_drm_config_hwctx_param

Enumerator
DRM_AMDXDNA_HWCTX_CONFIG_CU
DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF
DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF

amdxdna_drm_get_param

enum amdxdna_drm_get_param

Enumerator
DRM_AMDXDNA_QUERY_AIE_STATUS
DRM_AMDXDNA_QUERY_AIE_METADATA
DRM_AMDXDNA_QUERY_AIE_VERSION
DRM_AMDXDNA_QUERY_CLOCK_METADATA
DRM_AMDXDNA_QUERY_SENSORS
DRM_AMDXDNA_QUERY_HW_CONTEXTS
DRM_AMDXDNA_QUERY_FIRMWARE_VERSION
DRM_AMDXDNA_GET_POWER_MODE
DRM_AMDXDNA_QUERY_TELEMETRY
DRM_AMDXDNA_GET_FORCE_PREEMPT_STATE
DRM_AMDXDNA_QUERY_RESOURCE_INFO
DRM_AMDXDNA_GET_FRAME_BOUNDARY_PREEMPT_STATE

amdxdna_drm_ioctl_id

enum amdxdna_drm_ioctl_id

Enumerator
DRM_AMDXDNA_CREATE_HWCTX
DRM_AMDXDNA_DESTROY_HWCTX
DRM_AMDXDNA_CONFIG_HWCTX
DRM_AMDXDNA_CREATE_BO
DRM_AMDXDNA_GET_BO_INFO
DRM_AMDXDNA_SYNC_BO
DRM_AMDXDNA_EXEC_CMD
DRM_AMDXDNA_GET_INFO
DRM_AMDXDNA_SET_STATE
DRM_AMDXDNA_WAIT_CMD
DRM_AMDXDNA_GET_ARRAY

amdxdna_drm_set_param

enum amdxdna_drm_set_param

Enumerator
DRM_AMDXDNA_SET_POWER_MODE
DRM_AMDXDNA_WRITE_AIE_MEM
DRM_AMDXDNA_WRITE_AIE_REG
DRM_AMDXDNA_SET_FORCE_PREEMPT
DRM_AMDXDNA_SET_FRAME_BOUNDARY_PREEMPT

amdxdna_power_mode_type

enum amdxdna_power_mode_type

Enumerator
POWER_MODE_DEFAULT
POWER_MODE_LOW
POWER_MODE_MEDIUM
POWER_MODE_HIGH
POWER_MODE_TURBO

amdxdna_sensor_type

enum amdxdna_sensor_type

Enumerator
AMDXDNA_SENSOR_TYPE_POWER
AMDXDNA_SENSOR_TYPE_COLUMN_UTILIZATION