amdxdna_accel.h

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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
/*
 * Copyright (C) 2022-2024, Advanced Micro Devices, Inc.
 */
 
#ifndef _UAPI_AMDXDNA_ACCEL_H_
#define _UAPI_AMDXDNA_ACCEL_H_
 
#include <linux/stddef.h>
#include "drm.h"
 
#if defined(__cplusplus)
extern "C" {
#endif
 
#define AMDXDNA_INVALID_CMD_HANDLE  (~0UL)
#define AMDXDNA_INVALID_ADDR        (~0UL)
#define AMDXDNA_INVALID_CTX_HANDLE  0
#define AMDXDNA_INVALID_BO_HANDLE   0
#define AMDXDNA_INVALID_FENCE_HANDLE    0
#define AMDXDNA_INVALID_DOORBELL_OFFSET (~0U)
 
/*
 * Define hardware context priority
 */
#define AMDXDNA_QOS_REALTIME_PRIORITY   0x100
#define AMDXDNA_QOS_HIGH_PRIORITY   0x180
#define AMDXDNA_QOS_NORMAL_PRIORITY 0x200
#define AMDXDNA_QOS_LOW_PRIORITY    0x280
 
enum amdxdna_device_type {
    AMDXDNA_DEV_TYPE_UNKNOWN = -1,
    AMDXDNA_DEV_TYPE_KMQ = 0,
    AMDXDNA_DEV_TYPE_UMQ = 1,
    AMDXDNA_DEV_TYPE_PF = 2,
};
 
enum amdxdna_drm_ioctl_id {
    DRM_AMDXDNA_CREATE_HWCTX,
    DRM_AMDXDNA_DESTROY_HWCTX,
    DRM_AMDXDNA_CONFIG_HWCTX,
    DRM_AMDXDNA_CREATE_BO,
    DRM_AMDXDNA_GET_BO_INFO,
    DRM_AMDXDNA_SYNC_BO,
    DRM_AMDXDNA_EXEC_CMD,
    DRM_AMDXDNA_GET_INFO,
    DRM_AMDXDNA_SET_STATE,
    DRM_AMDXDNA_WAIT_CMD,
    DRM_AMDXDNA_GET_ARRAY,
};
 
struct amdxdna_qos_info {
    __u32 gops;
    __u32 fps;
    __u32 dma_bandwidth;
    __u32 latency;
    __u32 frame_exec_time;
    __u32 priority;
};
 
struct amdxdna_drm_create_hwctx {
    __u64 ext;
    __u64 ext_flags;
    __u64 qos_p;
    __u32 umq_bo;
    __u32 log_buf_bo;
    __u32 max_opc;
    __u32 num_tiles;
    __u32 mem_size;
    __u32 umq_doorbell;
    __u32 handle;
    __u32 syncobj_handle;
};
 
struct amdxdna_drm_destroy_hwctx {
    __u32 handle;
    __u32 pad;
};
 
struct amdxdna_cu_config {
    __u32 cu_bo;
    __u8  cu_func;
    __u8  pad[3];
};
 
struct amdxdna_hwctx_param_config_cu {
    __u16 num_cus;
    __u16 pad[3];
    struct amdxdna_cu_config cu_configs[] __counted_by(num_cus);
};
 
enum amdxdna_drm_config_hwctx_param {
    DRM_AMDXDNA_HWCTX_CONFIG_CU,
    DRM_AMDXDNA_HWCTX_ASSIGN_DBG_BUF,
    DRM_AMDXDNA_HWCTX_REMOVE_DBG_BUF,
};
 
struct amdxdna_drm_config_hwctx {
    __u32 handle;
    __u32 param_type;
    __u64 param_val;
    __u32 param_val_size;
    __u32 pad;
};
 
enum amdxdna_bo_type {
    AMDXDNA_BO_INVALID = 0,
    AMDXDNA_BO_SHMEM = 1, /* Be compatible with legacy application code. */
    AMDXDNA_BO_SHARE = 1,
    AMDXDNA_BO_DEV_HEAP = 2,
    AMDXDNA_BO_DEV = 3,
    AMDXDNA_BO_CMD = 4,
};
 
struct amdxdna_drm_va_entry {
    __u64 vaddr;
    __u64 len;
};
 
struct amdxdna_drm_va_tbl {
    __s32 dmabuf_fd;
    __u32 num_entries;
    struct amdxdna_drm_va_entry va_entries[];
};
 
struct amdxdna_drm_create_bo {
    __u64   flags;
    __u64   vaddr;
    __u64   size;
    __u32   type;
    __u32   handle;
};
 
struct amdxdna_drm_get_bo_info {
    __u64 ext;
    __u64 ext_flags;
    __u32 handle;
    __u32 pad;
    __u64 map_offset;
    __u64 vaddr;
    __u64 xdna_addr;
};
 
struct amdxdna_drm_sync_bo {
    __u32 handle;
#define SYNC_DIRECT_TO_DEVICE   0U
#define SYNC_DIRECT_FROM_DEVICE 1U
    __u32 direction;
    __u64 offset;
    __u64 size;
};
 
enum amdxdna_cmd_type {
    AMDXDNA_CMD_SUBMIT_EXEC_BUF = 0,
    AMDXDNA_CMD_SUBMIT_DEPENDENCY,
    AMDXDNA_CMD_SUBMIT_SIGNAL,
};
 
struct amdxdna_drm_exec_cmd {
    __u64 ext;
    __u64 ext_flags;
    __u32 hwctx;
    __u32 type;
    __u64 cmd_handles;
    __u64 args;
    __u32 cmd_count;
    __u32 arg_count;
    __u64 seq;
};
 
struct amdxdna_drm_wait_cmd {
    __u32 hwctx;
    __u32 timeout;
    __u64 seq;
};
 
struct amdxdna_drm_query_aie_status {
    __u64 buffer; /* out */
    __u32 buffer_size; /* in */
    __u32 cols_filled; /* out */
};
 
struct amdxdna_drm_query_aie_version {
    __u32 major; /* out */
    __u32 minor; /* out */
};
 
struct amdxdna_drm_query_aie_tile_metadata {
    __u16 row_count;
    __u16 row_start;
    __u16 dma_channel_count;
    __u16 lock_count;
    __u16 event_reg_count;
    __u16 pad[3];
};
 
struct amdxdna_drm_query_aie_metadata {
    __u32 col_size;
    __u16 cols;
    __u16 rows;
    struct amdxdna_drm_query_aie_version version;
    struct amdxdna_drm_query_aie_tile_metadata core;
    struct amdxdna_drm_query_aie_tile_metadata mem;
    struct amdxdna_drm_query_aie_tile_metadata shim;
};
 
struct amdxdna_drm_query_clock {
    __u8 name[16];
    __u32 freq_mhz;
    __u32 pad;
};
 
struct amdxdna_drm_query_clock_metadata {
    struct amdxdna_drm_query_clock mp_npu_clock;
    struct amdxdna_drm_query_clock h_clock;
};
 
enum amdxdna_sensor_type {
    AMDXDNA_SENSOR_TYPE_POWER,
    AMDXDNA_SENSOR_TYPE_COLUMN_UTILIZATION
};
 
struct amdxdna_drm_query_sensor {
    __u8  label[64];
    __u32 input;
    __u32 max;
    __u32 average;
    __u32 highest;
    __u8  status[64];
    __u8  units[16];
    __s8  unitm;
    __u8  type;
    __u8  pad[6];
};
 
struct amdxdna_drm_query_hwctx {
    __u32 context_id;
    __u32 start_col;
    __u32 num_col;
    __u32 pad;
    __s64 pid;
    __u64 command_submissions;
    __u64 command_completions;
    __u64 migrations;
    __u64 preemptions;
    __u64 errors;
};
 
enum amdxdna_power_mode_type {
    POWER_MODE_DEFAULT, /* Fallback to calculated DPM */
    POWER_MODE_LOW,     /* Set frequency to lowest DPM */
    POWER_MODE_MEDIUM,  /* Set frequency to medium DPM */
    POWER_MODE_HIGH,    /* Set frequency to highest DPM */
    POWER_MODE_TURBO,   /* Maximum power */
};
 
struct amdxdna_drm_get_power_mode {
    __u8 power_mode;
    __u8 pad[7];
};
 
struct amdxdna_drm_query_firmware_version {
    __u32 major; /* out */
    __u32 minor; /* out */
    __u32 patch; /* out */
    __u32 build; /* out */
};
 
enum amdxdna_drm_get_param {
    DRM_AMDXDNA_QUERY_AIE_STATUS,
    DRM_AMDXDNA_QUERY_AIE_METADATA,
    DRM_AMDXDNA_QUERY_AIE_VERSION,
    DRM_AMDXDNA_QUERY_CLOCK_METADATA,
    DRM_AMDXDNA_QUERY_SENSORS,
    DRM_AMDXDNA_QUERY_HW_CONTEXTS,
    DRM_AMDXDNA_QUERY_FIRMWARE_VERSION = 8,
    DRM_AMDXDNA_GET_POWER_MODE,
    DRM_AMDXDNA_QUERY_TELEMETRY,
    DRM_AMDXDNA_GET_FORCE_PREEMPT_STATE,
    DRM_AMDXDNA_QUERY_RESOURCE_INFO,
    DRM_AMDXDNA_GET_FRAME_BOUNDARY_PREEMPT_STATE,
};
 
struct amdxdna_drm_get_resource_info {
    __u64 npu_clk_max;
    __u64 npu_tops_max;
    __u64 npu_task_max;
    __u64 npu_tops_curr;
    __u64 npu_task_curr;
};
 
struct amdxdna_drm_attribute_state {
    __u8 state;
    __u8 pad[7];
};
 
struct amdxdna_drm_query_telemetry_header {
    __u32 major;
    __u32 minor;
    __u32 type;
    __u32 map_num_elements;
    __u32 map[];
};
 
struct amdxdna_drm_get_info {
    __u32 param; /* in */
    __u32 buffer_size; /* in/out */
    __u64 buffer; /* in/out */
};
 
#define AMDXDNA_HWCTX_STATE_IDLE    0
#define AMDXDNA_HWCTX_STATE_ACTIVE  1
 
struct amdxdna_drm_hwctx_entry {
    __u32 context_id;
    __u32 start_col;
    __u32 num_col;
    __u32 hwctx_id;
    __s64 pid;
    __u64 command_submissions;
    __u64 command_completions;
    __u64 migrations;
    __u64 preemptions;
    __u64 errors;
    __u64 priority;
    __u64 heap_usage;
    __u64 suspensions;
    __u32 state;
    __u32 pasid;
    __u32 gops;
    __u32 fps;
    __u32 dma_bandwidth;
    __u32 latency;
    __u32 frame_exec_time;
    __u32 txn_op_idx;
    __u32 ctx_pc;
    __u32 fatal_error_type;
    __u32 fatal_error_exception_type;
    __u32 fatal_error_exception_pc;
    __u32 fatal_error_app_module;
    __u32 pad;
};
 
struct amdxdna_async_error {
    __u64 err_code;
    __u64 ts_us;
    __u64 ex_err_code;
};
 
struct amdxdna_drm_bo_usage {
    __s64 pid;
    __u64 total_usage;
    __u64 internal_usage;
    __u64 heap_usage;
};
 
/*
 * Supported params in struct amdxdna_drm_get_array
 */
#define DRM_AMDXDNA_HW_CONTEXT_ALL  0
#define DRM_AMDXDNA_HW_LAST_ASYNC_ERR   2
#define DRM_AMDXDNA_BO_USAGE        6
 
struct amdxdna_drm_get_array {
    __u32 param;
    __u32 element_size;
    __u32 num_element; /* in/out */
    __u32 pad;
    __u64 buffer;
};
 
enum amdxdna_drm_set_param {
    DRM_AMDXDNA_SET_POWER_MODE,
    DRM_AMDXDNA_WRITE_AIE_MEM,
    DRM_AMDXDNA_WRITE_AIE_REG,
    DRM_AMDXDNA_SET_FORCE_PREEMPT,
    DRM_AMDXDNA_SET_FRAME_BOUNDARY_PREEMPT,
};
 
struct amdxdna_drm_set_state {
    __u32 param; /* in */
    __u32 buffer_size; /* in */
    __u64 buffer; /* in */
};
 
struct amdxdna_drm_set_power_mode {
    __u8 power_mode;
    __u8 pad[7];
};
 
#define DRM_IOCTL_AMDXDNA_CREATE_HWCTX \
    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_HWCTX, \
         struct amdxdna_drm_create_hwctx)
 
#define DRM_IOCTL_AMDXDNA_DESTROY_HWCTX \
    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_DESTROY_HWCTX, \
         struct amdxdna_drm_destroy_hwctx)
 
#define DRM_IOCTL_AMDXDNA_CONFIG_HWCTX \
    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CONFIG_HWCTX, \
         struct amdxdna_drm_config_hwctx)
 
#define DRM_IOCTL_AMDXDNA_CREATE_BO \
    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_CREATE_BO, \
         struct amdxdna_drm_create_bo)
 
#define DRM_IOCTL_AMDXDNA_GET_BO_INFO \
    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_BO_INFO, \
         struct amdxdna_drm_get_bo_info)
 
#define DRM_IOCTL_AMDXDNA_SYNC_BO \
    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SYNC_BO, \
         struct amdxdna_drm_sync_bo)
 
#define DRM_IOCTL_AMDXDNA_EXEC_CMD \
    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_EXEC_CMD, \
         struct amdxdna_drm_exec_cmd)
 
#define DRM_IOCTL_AMDXDNA_GET_INFO \
    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_INFO, \
         struct amdxdna_drm_get_info)
 
#define DRM_IOCTL_AMDXDNA_SET_STATE \
    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_SET_STATE, \
         struct amdxdna_drm_set_state)
 
#define DRM_IOCTL_AMDXDNA_GET_ARRAY \
    DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDXDNA_GET_ARRAY, \
         struct amdxdna_drm_get_array)
 
#define DRM_IOCTL_AMDXDNA_WAIT_CMD \
    DRM_IOW(DRM_COMMAND_BASE + DRM_AMDXDNA_WAIT_CMD, \
        struct amdxdna_drm_wait_cmd)
 
#if defined(__cplusplus)
} /* extern c end */
#endif
 
#endif /* _UAPI_AMDXDNA_ACCEL_H_ */