msm_drm.h File Reference

#include "drm.h"

Include dependency graph for msm_drm.h:

Go to the source code of this file.

Classes
struct	drm_msm_timespec
struct	drm_msm_param
struct	drm_msm_gem_new
struct	drm_msm_gem_info
struct	drm_msm_gem_cpu_prep
struct	drm_msm_gem_cpu_fini
struct	drm_msm_syncobj
struct	drm_msm_gem_submit_reloc
struct	drm_msm_gem_submit_cmd
struct	drm_msm_gem_submit_bo
struct	drm_msm_gem_submit
struct	drm_msm_vm_bind_op
struct	drm_msm_vm_bind
struct	drm_msm_wait_fence
struct	drm_msm_gem_madvise
struct	drm_msm_submitqueue
struct	drm_msm_submitqueue_query
struct	drm_msm_perfcntr_group
struct	drm_msm_perfcntr_config

Macros
#define	MSM_PIPE_NONE   0x00
#define	MSM_PIPE_2D0   0x01
#define	MSM_PIPE_2D1   0x02
#define	MSM_PIPE_3D0   0x10
#define	MSM_PIPE_ID_MASK   0xffff
#define	MSM_PIPE_ID(x)   ((x) & MSM_PIPE_ID_MASK)
#define	MSM_PIPE_FLAGS(x)   ((x) & ~MSM_PIPE_ID_MASK)
#define	MSM_PARAM_GPU_ID   0x01 /* RO */
#define	MSM_PARAM_GMEM_SIZE   0x02 /* RO */
#define	MSM_PARAM_CHIP_ID   0x03 /* RO */
#define	MSM_PARAM_MAX_FREQ   0x04 /* RO */
#define	MSM_PARAM_TIMESTAMP   0x05 /* RO */
#define	MSM_PARAM_GMEM_BASE   0x06 /* RO */
#define	MSM_PARAM_PRIORITIES   0x07 /* RO: The # of priority levels */
#define	MSM_PARAM_PP_PGTABLE   0x08 /* RO: Deprecated, always returns zero */
#define	MSM_PARAM_FAULTS   0x09 /* RO */
#define	MSM_PARAM_SUSPENDS   0x0a /* RO */
#define	MSM_PARAM_SYSPROF   0x0b /* WO: 1 preserves perfcntrs, 2 also disables suspend */
#define	MSM_PARAM_COMM   0x0c /* WO: override for task->comm */
#define	MSM_PARAM_CMDLINE   0x0d /* WO: override for task cmdline */
#define	MSM_PARAM_VA_START   0x0e /* RO: start of valid GPU iova range */
#define	MSM_PARAM_VA_SIZE   0x0f /* RO: size of valid GPU iova range (bytes) */
#define	MSM_PARAM_HIGHEST_BANK_BIT   0x10 /* RO */
#define	MSM_PARAM_RAYTRACING   0x11 /* RO */
#define	MSM_PARAM_UBWC_SWIZZLE   0x12 /* RO */
#define	MSM_PARAM_MACROTILE_MODE   0x13 /* RO */
#define	MSM_PARAM_UCHE_TRAP_BASE   0x14 /* RO */
#define	MSM_PARAM_HAS_PRR   0x15 /* RO */
#define	MSM_PARAM_EN_VM_BIND   0x16 /* WO, once */
#define	MSM_PARAM_AQE   0x17 /* RO */
#define	MSM_PARAM_NR_RINGS   MSM_PARAM_PRIORITIES
#define	MSM_BO_SCANOUT   0x00000001 /* scanout capable */
#define	MSM_BO_GPU_READONLY   0x00000002
#define	MSM_BO_NO_SHARE   0x00000004
#define	MSM_BO_CACHE_MASK   0x000f0000
#define	MSM_BO_CACHED   0x00010000
#define	MSM_BO_WC   0x00020000
#define	MSM_BO_UNCACHED   0x00040000 /* deprecated, use MSM_BO_WC */
#define	MSM_BO_CACHED_COHERENT   0x080000
#define	MSM_BO_FLAGS
#define	MSM_INFO_GET_OFFSET   0x00 /* get mmap() offset, returned by value */
#define	MSM_INFO_GET_IOVA   0x01 /* get iova, returned by value */
#define	MSM_INFO_SET_NAME   0x02 /* set the debug name (by pointer) */
#define	MSM_INFO_GET_NAME   0x03 /* get debug name, returned by pointer */
#define	MSM_INFO_SET_IOVA   0x04 /* set the iova, passed by value */
#define	MSM_INFO_GET_FLAGS   0x05 /* get the MSM_BO_x flags */
#define	MSM_INFO_SET_METADATA   0x06 /* set userspace metadata */
#define	MSM_INFO_GET_METADATA   0x07 /* get userspace metadata */
#define	MSM_PREP_READ   0x01
#define	MSM_PREP_WRITE   0x02
#define	MSM_PREP_NOSYNC   0x04
#define	MSM_PREP_BOOST   0x08
#define	MSM_PREP_FLAGS
#define	MSM_SYNCOBJ_RESET   0x00000001 /* Reset syncobj after wait. */
#define	MSM_SYNCOBJ_FLAGS
#define	MSM_SUBMIT_CMD_BUF   0x0001
#define	MSM_SUBMIT_CMD_IB_TARGET_BUF   0x0002
#define	MSM_SUBMIT_CMD_CTX_RESTORE_BUF   0x0003
#define	MSM_SUBMIT_BO_READ   0x0001
#define	MSM_SUBMIT_BO_WRITE   0x0002
#define	MSM_SUBMIT_BO_DUMP   0x0004
#define	MSM_SUBMIT_BO_NO_IMPLICIT   0x0008
#define	MSM_SUBMIT_BO_FLAGS
#define	MSM_SUBMIT_NO_IMPLICIT   0x80000000 /* disable implicit sync */
#define	MSM_SUBMIT_FENCE_FD_IN   0x40000000 /* enable input fence_fd */
#define	MSM_SUBMIT_FENCE_FD_OUT   0x20000000 /* enable output fence_fd */
#define	MSM_SUBMIT_SUDO   0x10000000 /* run submitted cmds from RB */
#define	MSM_SUBMIT_SYNCOBJ_IN   0x08000000 /* enable input syncobj */
#define	MSM_SUBMIT_SYNCOBJ_OUT   0x04000000 /* enable output syncobj */
#define	MSM_SUBMIT_FENCE_SN_IN   0x02000000 /* userspace passes in seqno fence */
#define	MSM_SUBMIT_FLAGS
#define	MSM_VM_BIND_OP_UNMAP   0
#define	MSM_VM_BIND_OP_MAP   1
#define	MSM_VM_BIND_OP_MAP_NULL   2
#define	MSM_VM_BIND_OP_DUMP   1
#define	MSM_VM_BIND_OP_FLAGS
#define	MSM_VM_BIND_FENCE_FD_IN   0x00000001
#define	MSM_VM_BIND_FENCE_FD_OUT   0x00000002
#define	MSM_VM_BIND_FLAGS
#define	MSM_WAIT_FENCE_BOOST   0x00000001
#define	MSM_WAIT_FENCE_FLAGS
#define	MSM_MADV_WILLNEED   0 /* backing pages are needed, status returned in 'retained' */
#define	MSM_MADV_DONTNEED   1 /* backing pages not needed */
#define	__MSM_MADV_PURGED   2 /* internal state */
#define	MSM_SUBMITQUEUE_ALLOW_PREEMPT   0x00000001
#define	MSM_SUBMITQUEUE_VM_BIND   0x00000002 /* virtual queue for VM_BIND ops */
#define	MSM_SUBMITQUEUE_FLAGS
#define	MSM_SUBMITQUEUE_PARAM_FAULTS   0
#define	MSM_PERFCNTR_STREAM   0x00000001
#define	MSM_PERFCNTR_UPDATE   0x00000002
#define	MSM_PERFCNTR_FLAGS
#define	DRM_MSM_GET_PARAM   0x00
#define	DRM_MSM_SET_PARAM   0x01
#define	DRM_MSM_GEM_NEW   0x02
#define	DRM_MSM_GEM_INFO   0x03
#define	DRM_MSM_GEM_CPU_PREP   0x04
#define	DRM_MSM_GEM_CPU_FINI   0x05
#define	DRM_MSM_GEM_SUBMIT   0x06
#define	DRM_MSM_WAIT_FENCE   0x07
#define	DRM_MSM_GEM_MADVISE   0x08
#define	DRM_MSM_SUBMITQUEUE_NEW   0x0A
#define	DRM_MSM_SUBMITQUEUE_CLOSE   0x0B
#define	DRM_MSM_SUBMITQUEUE_QUERY   0x0C
#define	DRM_MSM_VM_BIND   0x0D
#define	DRM_MSM_PERFCNTR_CONFIG   0x0E
#define	DRM_IOCTL_MSM_GET_PARAM   DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
#define	DRM_IOCTL_MSM_SET_PARAM   DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param)
#define	DRM_IOCTL_MSM_GEM_NEW   DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
#define	DRM_IOCTL_MSM_GEM_INFO   DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
#define	DRM_IOCTL_MSM_GEM_CPU_PREP   DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
#define	DRM_IOCTL_MSM_GEM_CPU_FINI   DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
#define	DRM_IOCTL_MSM_GEM_SUBMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
#define	DRM_IOCTL_MSM_WAIT_FENCE   DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
#define	DRM_IOCTL_MSM_GEM_MADVISE   DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
#define	DRM_IOCTL_MSM_SUBMITQUEUE_NEW   DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
#define	DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE   DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
#define	DRM_IOCTL_MSM_SUBMITQUEUE_QUERY   DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
#define	DRM_IOCTL_MSM_VM_BIND   DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_VM_BIND, struct drm_msm_vm_bind)
#define	DRM_IOCTL_MSM_PERFCNTR_CONFIG   DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_PERFCNTR_CONFIG, struct drm_msm_perfcntr_config)

Macro Definition Documentation

__MSM_MADV_PURGED

#define __MSM_MADV_PURGED   2 /* internal state */

DRM_IOCTL_MSM_GEM_CPU_FINI

#define DRM_IOCTL_MSM_GEM_CPU_FINI   DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)

DRM_IOCTL_MSM_GEM_CPU_PREP

#define DRM_IOCTL_MSM_GEM_CPU_PREP   DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)

DRM_IOCTL_MSM_GEM_INFO

#define DRM_IOCTL_MSM_GEM_INFO   DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)

DRM_IOCTL_MSM_GEM_MADVISE

#define DRM_IOCTL_MSM_GEM_MADVISE   DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)

DRM_IOCTL_MSM_GEM_NEW

#define DRM_IOCTL_MSM_GEM_NEW   DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)

DRM_IOCTL_MSM_GEM_SUBMIT

#define DRM_IOCTL_MSM_GEM_SUBMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)

DRM_IOCTL_MSM_GET_PARAM

#define DRM_IOCTL_MSM_GET_PARAM   DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)

DRM_IOCTL_MSM_PERFCNTR_CONFIG

#define DRM_IOCTL_MSM_PERFCNTR_CONFIG   DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_PERFCNTR_CONFIG, struct drm_msm_perfcntr_config)

DRM_IOCTL_MSM_SET_PARAM

#define DRM_IOCTL_MSM_SET_PARAM   DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param)

DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE

#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE   DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)

DRM_IOCTL_MSM_SUBMITQUEUE_NEW

#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW   DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)

DRM_IOCTL_MSM_SUBMITQUEUE_QUERY

#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY   DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)

DRM_IOCTL_MSM_VM_BIND

#define DRM_IOCTL_MSM_VM_BIND   DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_VM_BIND, struct drm_msm_vm_bind)

DRM_IOCTL_MSM_WAIT_FENCE

#define DRM_IOCTL_MSM_WAIT_FENCE   DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)

DRM_MSM_GEM_CPU_FINI

#define DRM_MSM_GEM_CPU_FINI   0x05

DRM_MSM_GEM_CPU_PREP

#define DRM_MSM_GEM_CPU_PREP   0x04

DRM_MSM_GEM_INFO

#define DRM_MSM_GEM_INFO   0x03

DRM_MSM_GEM_MADVISE

#define DRM_MSM_GEM_MADVISE   0x08

DRM_MSM_GEM_NEW

#define DRM_MSM_GEM_NEW   0x02

DRM_MSM_GEM_SUBMIT

#define DRM_MSM_GEM_SUBMIT   0x06

DRM_MSM_GET_PARAM

#define DRM_MSM_GET_PARAM   0x00

DRM_MSM_PERFCNTR_CONFIG

#define DRM_MSM_PERFCNTR_CONFIG   0x0E

DRM_MSM_SET_PARAM

#define DRM_MSM_SET_PARAM   0x01

DRM_MSM_SUBMITQUEUE_CLOSE

#define DRM_MSM_SUBMITQUEUE_CLOSE   0x0B

DRM_MSM_SUBMITQUEUE_NEW

#define DRM_MSM_SUBMITQUEUE_NEW   0x0A

DRM_MSM_SUBMITQUEUE_QUERY

#define DRM_MSM_SUBMITQUEUE_QUERY   0x0C

DRM_MSM_VM_BIND

#define DRM_MSM_VM_BIND   0x0D

DRM_MSM_WAIT_FENCE

#define DRM_MSM_WAIT_FENCE   0x07

MSM_BO_CACHE_MASK

#define MSM_BO_CACHE_MASK   0x000f0000

MSM_BO_CACHED

#define MSM_BO_CACHED   0x00010000

MSM_BO_CACHED_COHERENT

#define MSM_BO_CACHED_COHERENT   0x080000

MSM_BO_FLAGS

#define MSM_BO_FLAGS

Value:

                              (MSM_BO_SCANOUT | \
                              MSM_BO_GPU_READONLY | \
                              MSM_BO_NO_SHARE | \
                              MSM_BO_CACHE_MASK)

MSM_BO_GPU_READONLY

#define MSM_BO_GPU_READONLY   0x00000002

MSM_BO_NO_SHARE

#define MSM_BO_NO_SHARE   0x00000004

MSM_BO_SCANOUT

#define MSM_BO_SCANOUT   0x00000001 /* scanout capable */

MSM_BO_UNCACHED

#define MSM_BO_UNCACHED   0x00040000 /* deprecated, use MSM_BO_WC */

MSM_BO_WC

#define MSM_BO_WC   0x00020000

MSM_INFO_GET_FLAGS

#define MSM_INFO_GET_FLAGS   0x05 /* get the MSM_BO_x flags */

MSM_INFO_GET_IOVA

#define MSM_INFO_GET_IOVA   0x01 /* get iova, returned by value */

MSM_INFO_GET_METADATA

#define MSM_INFO_GET_METADATA   0x07 /* get userspace metadata */

MSM_INFO_GET_NAME

#define MSM_INFO_GET_NAME   0x03 /* get debug name, returned by pointer */

MSM_INFO_GET_OFFSET

#define MSM_INFO_GET_OFFSET   0x00 /* get mmap() offset, returned by value */

MSM_INFO_SET_IOVA

#define MSM_INFO_SET_IOVA   0x04 /* set the iova, passed by value */

MSM_INFO_SET_METADATA

#define MSM_INFO_SET_METADATA   0x06 /* set userspace metadata */

MSM_INFO_SET_NAME

#define MSM_INFO_SET_NAME   0x02 /* set the debug name (by pointer) */

MSM_MADV_DONTNEED

#define MSM_MADV_DONTNEED   1 /* backing pages not needed */

MSM_MADV_WILLNEED

#define MSM_MADV_WILLNEED   0 /* backing pages are needed, status returned in 'retained' */

MSM_PARAM_AQE

#define MSM_PARAM_AQE   0x17 /* RO */

MSM_PARAM_CHIP_ID

#define MSM_PARAM_CHIP_ID   0x03 /* RO */

MSM_PARAM_CMDLINE

#define MSM_PARAM_CMDLINE   0x0d /* WO: override for task cmdline */

MSM_PARAM_COMM

#define MSM_PARAM_COMM   0x0c /* WO: override for task->comm */

MSM_PARAM_EN_VM_BIND

#define MSM_PARAM_EN_VM_BIND   0x16 /* WO, once */

MSM_PARAM_FAULTS

#define MSM_PARAM_FAULTS   0x09 /* RO */

MSM_PARAM_GMEM_BASE

#define MSM_PARAM_GMEM_BASE   0x06 /* RO */

MSM_PARAM_GMEM_SIZE

#define MSM_PARAM_GMEM_SIZE   0x02 /* RO */

MSM_PARAM_GPU_ID

#define MSM_PARAM_GPU_ID   0x01 /* RO */

MSM_PARAM_HAS_PRR

#define MSM_PARAM_HAS_PRR   0x15 /* RO */

MSM_PARAM_HIGHEST_BANK_BIT

#define MSM_PARAM_HIGHEST_BANK_BIT   0x10 /* RO */

MSM_PARAM_MACROTILE_MODE

#define MSM_PARAM_MACROTILE_MODE   0x13 /* RO */

MSM_PARAM_MAX_FREQ

#define MSM_PARAM_MAX_FREQ   0x04 /* RO */

MSM_PARAM_NR_RINGS

#define MSM_PARAM_NR_RINGS   MSM_PARAM_PRIORITIES

MSM_PARAM_PP_PGTABLE

#define MSM_PARAM_PP_PGTABLE   0x08 /* RO: Deprecated, always returns zero */

MSM_PARAM_PRIORITIES

#define MSM_PARAM_PRIORITIES   0x07 /* RO: The # of priority levels */

MSM_PARAM_RAYTRACING

#define MSM_PARAM_RAYTRACING   0x11 /* RO */

MSM_PARAM_SUSPENDS

#define MSM_PARAM_SUSPENDS   0x0a /* RO */

MSM_PARAM_SYSPROF

#define MSM_PARAM_SYSPROF   0x0b /* WO: 1 preserves perfcntrs, 2 also disables suspend */

MSM_PARAM_TIMESTAMP

#define MSM_PARAM_TIMESTAMP   0x05 /* RO */

MSM_PARAM_UBWC_SWIZZLE

#define MSM_PARAM_UBWC_SWIZZLE   0x12 /* RO */

MSM_PARAM_UCHE_TRAP_BASE

#define MSM_PARAM_UCHE_TRAP_BASE   0x14 /* RO */

MSM_PARAM_VA_SIZE

#define MSM_PARAM_VA_SIZE   0x0f /* RO: size of valid GPU iova range (bytes) */

MSM_PARAM_VA_START

#define MSM_PARAM_VA_START   0x0e /* RO: start of valid GPU iova range */

MSM_PERFCNTR_FLAGS

#define MSM_PERFCNTR_FLAGS

Value:

        ( \
        MSM_PERFCNTR_STREAM | \
        MSM_PERFCNTR_UPDATE | \
        0)

MSM_PERFCNTR_STREAM

#define MSM_PERFCNTR_STREAM   0x00000001

MSM_PERFCNTR_UPDATE

#define MSM_PERFCNTR_UPDATE   0x00000002

MSM_PIPE_2D0

#define MSM_PIPE_2D0   0x01

MSM_PIPE_2D1

#define MSM_PIPE_2D1   0x02

MSM_PIPE_3D0

#define MSM_PIPE_3D0   0x10

MSM_PIPE_FLAGS

#define MSM_PIPE_FLAGS

(

x

)

((x) & ~MSM_PIPE_ID_MASK)

MSM_PIPE_ID

#define MSM_PIPE_ID

(

x

)

((x) & MSM_PIPE_ID_MASK)

MSM_PIPE_ID_MASK

#define MSM_PIPE_ID_MASK   0xffff

MSM_PIPE_NONE

#define MSM_PIPE_NONE   0x00

MSM_PREP_BOOST

#define MSM_PREP_BOOST   0x08

MSM_PREP_FLAGS

#define MSM_PREP_FLAGS

Value:

                  (MSM_PREP_READ | \
                  MSM_PREP_WRITE | \
                  MSM_PREP_NOSYNC | \
                  MSM_PREP_BOOST | \
                  0)

MSM_PREP_NOSYNC

#define MSM_PREP_NOSYNC   0x04

MSM_PREP_READ

#define MSM_PREP_READ   0x01

MSM_PREP_WRITE

#define MSM_PREP_WRITE   0x02

MSM_SUBMIT_BO_DUMP

#define MSM_SUBMIT_BO_DUMP   0x0004

MSM_SUBMIT_BO_FLAGS

#define MSM_SUBMIT_BO_FLAGS

Value:

                    (MSM_SUBMIT_BO_READ | \
                    MSM_SUBMIT_BO_WRITE | \
                    MSM_SUBMIT_BO_DUMP | \
                    MSM_SUBMIT_BO_NO_IMPLICIT)

MSM_SUBMIT_BO_NO_IMPLICIT

#define MSM_SUBMIT_BO_NO_IMPLICIT   0x0008

MSM_SUBMIT_BO_READ

#define MSM_SUBMIT_BO_READ   0x0001

MSM_SUBMIT_BO_WRITE

#define MSM_SUBMIT_BO_WRITE   0x0002

MSM_SUBMIT_CMD_BUF

#define MSM_SUBMIT_CMD_BUF   0x0001

MSM_SUBMIT_CMD_CTX_RESTORE_BUF

#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF   0x0003

MSM_SUBMIT_CMD_IB_TARGET_BUF

#define MSM_SUBMIT_CMD_IB_TARGET_BUF   0x0002

MSM_SUBMIT_FENCE_FD_IN

#define MSM_SUBMIT_FENCE_FD_IN   0x40000000 /* enable input fence_fd */

MSM_SUBMIT_FENCE_FD_OUT

#define MSM_SUBMIT_FENCE_FD_OUT   0x20000000 /* enable output fence_fd */

MSM_SUBMIT_FENCE_SN_IN

#define MSM_SUBMIT_FENCE_SN_IN   0x02000000 /* userspace passes in seqno fence */

MSM_SUBMIT_FLAGS

#define MSM_SUBMIT_FLAGS

Value:

        ( \
        MSM_SUBMIT_NO_IMPLICIT   | \
        MSM_SUBMIT_FENCE_FD_IN   | \
        MSM_SUBMIT_FENCE_FD_OUT  | \
        MSM_SUBMIT_SUDO          | \
        MSM_SUBMIT_SYNCOBJ_IN    | \
        MSM_SUBMIT_SYNCOBJ_OUT   | \
        MSM_SUBMIT_FENCE_SN_IN   | \
        0)

MSM_SUBMIT_NO_IMPLICIT

#define MSM_SUBMIT_NO_IMPLICIT   0x80000000 /* disable implicit sync */

MSM_SUBMIT_SUDO

#define MSM_SUBMIT_SUDO   0x10000000 /* run submitted cmds from RB */

MSM_SUBMIT_SYNCOBJ_IN

#define MSM_SUBMIT_SYNCOBJ_IN   0x08000000 /* enable input syncobj */

MSM_SUBMIT_SYNCOBJ_OUT

#define MSM_SUBMIT_SYNCOBJ_OUT   0x04000000 /* enable output syncobj */

MSM_SUBMITQUEUE_ALLOW_PREEMPT

#define MSM_SUBMITQUEUE_ALLOW_PREEMPT   0x00000001

MSM_SUBMITQUEUE_FLAGS

#define MSM_SUBMITQUEUE_FLAGS

Value:

        ( \
        MSM_SUBMITQUEUE_ALLOW_PREEMPT | \
        MSM_SUBMITQUEUE_VM_BIND | \
        0)

MSM_SUBMITQUEUE_PARAM_FAULTS

#define MSM_SUBMITQUEUE_PARAM_FAULTS   0

MSM_SUBMITQUEUE_VM_BIND

#define MSM_SUBMITQUEUE_VM_BIND   0x00000002 /* virtual queue for VM_BIND ops */

MSM_SYNCOBJ_FLAGS

#define MSM_SYNCOBJ_FLAGS

Value:

        ( \
        MSM_SYNCOBJ_RESET | \
        0)

MSM_SYNCOBJ_RESET

#define MSM_SYNCOBJ_RESET   0x00000001 /* Reset syncobj after wait. */

MSM_VM_BIND_FENCE_FD_IN

#define MSM_VM_BIND_FENCE_FD_IN   0x00000001

MSM_VM_BIND_FENCE_FD_OUT

#define MSM_VM_BIND_FENCE_FD_OUT   0x00000002

MSM_VM_BIND_FLAGS

#define MSM_VM_BIND_FLAGS

Value:

        ( \
        MSM_VM_BIND_FENCE_FD_IN | \
        MSM_VM_BIND_FENCE_FD_OUT | \
        0)

MSM_VM_BIND_OP_DUMP

#define MSM_VM_BIND_OP_DUMP   1

MSM_VM_BIND_OP_FLAGS

#define MSM_VM_BIND_OP_FLAGS

Value:

        ( \
        MSM_VM_BIND_OP_DUMP | \
        0)

MSM_VM_BIND_OP_MAP

#define MSM_VM_BIND_OP_MAP   1

MSM_VM_BIND_OP_MAP_NULL

#define MSM_VM_BIND_OP_MAP_NULL   2

MSM_VM_BIND_OP_UNMAP

#define MSM_VM_BIND_OP_UNMAP   0

MSM_WAIT_FENCE_BOOST

#define MSM_WAIT_FENCE_BOOST   0x00000001

MSM_WAIT_FENCE_FLAGS

#define MSM_WAIT_FENCE_FLAGS

Value:

        ( \
        MSM_WAIT_FENCE_BOOST | \
        0)