#include <TpmTis.h>
◆ Access
| UINT8 TIS_PC_REGISTERS::Access |
Used to gain ownership for this particular port.
◆ BurstCount
| UINT16 TIS_PC_REGISTERS::BurstCount |
Number of consecutive writes that can be done to the TPM.
◆ DataFifo
| UINT32 TIS_PC_REGISTERS::DataFifo |
Read or write FIFO, depending on transaction.
◆ Did
◆ IntEnable
| UINT32 TIS_PC_REGISTERS::IntEnable |
◆ IntfCapability
| UINT32 TIS_PC_REGISTERS::IntfCapability |
Shows which interrupts are supported by that particular TPM.
◆ IntSts
| UINT32 TIS_PC_REGISTERS::IntSts |
◆ IntVector
| UINT8 TIS_PC_REGISTERS::IntVector |
SIRQ vector to be used by the TPM.
◆ LegacyAddress1
| UINT32 TIS_PC_REGISTERS::LegacyAddress1 |
Alias to I/O legacy space.
◆ LegacyAddress1Ex
| UINT32 TIS_PC_REGISTERS::LegacyAddress1Ex |
Additional 8 bits for I/O legacy space extension.
◆ LegacyAddress2
| UINT32 TIS_PC_REGISTERS::LegacyAddress2 |
Alias to second I/O legacy space.
◆ LegacyAddress2Ex
| UINT32 TIS_PC_REGISTERS::LegacyAddress2Ex |
Additional 8 bits for second I/O legacy space extension.
◆ Reserved
| UINT8 TIS_PC_REGISTERS::Reserved[0x7b] |
◆ Reserved1
| UINT8 TIS_PC_REGISTERS::Reserved1[7] |
◆ Reserved2
| UINT8 TIS_PC_REGISTERS::Reserved2[3] |
◆ Reserved3
| UINT8 TIS_PC_REGISTERS::Reserved3[9] |
◆ Reserved4
| UINT8 TIS_PC_REGISTERS::Reserved4[0xed8] |
◆ Rid
| UINT8 TIS_PC_REGISTERS::Rid |
◆ Status
| UINT8 TIS_PC_REGISTERS::Status |
Status Register. Provides status of the TPM.
◆ VendorDefined
| UINT8 TIS_PC_REGISTERS::VendorDefined[0x70] |
Vendor-defined configuration registers.
◆ Vid
The documentation for this struct was generated from the following file:
- XenevaOS/Boot/include/IndustryStandard/TpmTis.h