TpmTis.h

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#ifndef _TPM_TIS_H_
#define _TPM_TIS_H_
 
//
// Set structure alignment to 1-byte
//
#pragma pack (1)
 
//
// Register set map as specified in TIS specification Chapter 10
//
typedef struct {
  UINT8                             Access;             // 0
  UINT8                             Reserved1[7];       // 1
  UINT32                            IntEnable;          // 8
  UINT8                             IntVector;          // 0ch
  UINT8                             Reserved2[3];       // 0dh
  UINT32                            IntSts;             // 10h
  UINT32                            IntfCapability;     // 14h
  UINT8                             Status;             // 18h
  UINT16                            BurstCount;         // 19h
  UINT8                             Reserved3[9];
  UINT32                            DataFifo;           // 24h
  UINT8                             Reserved4[0xed8];   // 28h
  UINT16                            Vid;                // 0f00h
  UINT16                            Did;                // 0f02h
  UINT8                             Rid;                // 0f04h
  UINT8                             Reserved[0x7b];     // 0f05h
  UINT32                            LegacyAddress1;     // 0f80h
  UINT32                            LegacyAddress1Ex;   // 0f84h
  UINT32                            LegacyAddress2;     // 0f88h
  UINT32                            LegacyAddress2Ex;   // 0f8ch
  UINT8                             VendorDefined[0x70];// 0f90h
} TIS_PC_REGISTERS;
 
//
// Restore original structure alignment
//
#pragma pack ()
 
//
// Define pointer types used to access TIS registers on PC
//
typedef TIS_PC_REGISTERS  *TIS_PC_REGISTERS_PTR;
 
//
// Define bits of ACCESS and STATUS registers
//
 
#define TIS_PC_VALID                BIT7
#define TIS_PC_ACC_ACTIVE           BIT5
#define TIS_PC_ACC_SEIZED           BIT4
#define TIS_PC_ACC_SEIZE            BIT3
#define TIS_PC_ACC_PENDIND          BIT2
#define TIS_PC_ACC_RQUUSE           BIT1
#define TIS_PC_ACC_ESTABLISH        BIT0
 
#define TIS_PC_STS_CANCEL           BIT24
#define TIS_PC_STS_VALID            BIT7
#define TIS_PC_STS_READY            BIT6
#define TIS_PC_STS_GO               BIT5
#define TIS_PC_STS_DATA             BIT4
#define TIS_PC_STS_EXPECT           BIT3
#define TIS_PC_STS_SELFTEST_DONE    BIT2
#define TIS_PC_STS_RETRY            BIT1
 
//
// Default TimeOut value
//
#define TIS_TIMEOUT_A               (750  * 1000)  // 750ms
#define TIS_TIMEOUT_B               (2000 * 1000)  // 2s
#define TIS_TIMEOUT_C               (750  * 1000)  // 750ms
#define TIS_TIMEOUT_D               (750  * 1000)  // 750ms
 
#endif