TpmTis.h File Reference

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Classes
struct	TIS_PC_REGISTERS

Macros
#define	TIS_PC_VALID   BIT7
#define	TIS_PC_ACC_ACTIVE   BIT5
#define	TIS_PC_ACC_SEIZED   BIT4
#define	TIS_PC_ACC_SEIZE   BIT3
#define	TIS_PC_ACC_PENDIND   BIT2
#define	TIS_PC_ACC_RQUUSE   BIT1
#define	TIS_PC_ACC_ESTABLISH   BIT0
#define	TIS_PC_STS_CANCEL   BIT24
#define	TIS_PC_STS_VALID   BIT7
#define	TIS_PC_STS_READY   BIT6
#define	TIS_PC_STS_GO   BIT5
#define	TIS_PC_STS_DATA   BIT4
#define	TIS_PC_STS_EXPECT   BIT3
#define	TIS_PC_STS_SELFTEST_DONE   BIT2
#define	TIS_PC_STS_RETRY   BIT1
#define	TIS_TIMEOUT_A   (750 * 1000)
#define	TIS_TIMEOUT_B   (2000 * 1000)
#define	TIS_TIMEOUT_C   (750 * 1000)
#define	TIS_TIMEOUT_D   (750 * 1000)

Typedefs
typedef TIS_PC_REGISTERS *	TIS_PC_REGISTERS_PTR

Detailed Description

TPM Interface Specification definition. It covers both TPM1.2 and TPM2.0.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Macro Definition Documentation

TIS_PC_ACC_ACTIVE

#define TIS_PC_ACC_ACTIVE   BIT5

Indicate that this locality is active.

TIS_PC_ACC_ESTABLISH

#define TIS_PC_ACC_ESTABLISH   BIT0

A value of 1 indicates that a T/OS has not been established on the platform

TIS_PC_ACC_PENDIND

#define TIS_PC_ACC_PENDIND   BIT2

When this bit is 1, another locality is requesting usage of the TPM.

TIS_PC_ACC_RQUUSE

#define TIS_PC_ACC_RQUUSE   BIT1

Set to 1 to indicate that this locality is requesting to use TPM.

TIS_PC_ACC_SEIZE

#define TIS_PC_ACC_SEIZE   BIT3

Set to 1 to indicate that TPM MUST reset the TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the locality that is writing this bit.

TIS_PC_ACC_SEIZED

#define TIS_PC_ACC_SEIZED   BIT4

Set to 1 to indicate that this locality had the TPM taken away while this locality had the TIS_PC_ACC_ACTIVE bit set.

TIS_PC_STS_CANCEL

#define TIS_PC_STS_CANCEL   BIT24

Write a 1 to this bit to notify TPM to cancel currently executing command

TIS_PC_STS_DATA

#define TIS_PC_STS_DATA   BIT4

This bit indicates that the TPM has data available as a response.

TIS_PC_STS_EXPECT

#define TIS_PC_STS_EXPECT   BIT3

The TPM sets this bit to a value of 1 when it expects another byte of data for a command.

TIS_PC_STS_GO

#define TIS_PC_STS_GO   BIT5

Write a 1 to this bit to cause the TPM to execute that command.

TIS_PC_STS_READY

#define TIS_PC_STS_READY   BIT6

When this bit is 1, TPM is in the Ready state, indicating it is ready to receive a new command.

TIS_PC_STS_RETRY

#define TIS_PC_STS_RETRY   BIT1

Writes a 1 to this bit to force the TPM to re-send the response.

TIS_PC_STS_SELFTEST_DONE

#define TIS_PC_STS_SELFTEST_DONE   BIT2

Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.

TIS_PC_STS_VALID

#define TIS_PC_STS_VALID   BIT7

This field indicates that STS_DATA and STS_EXPECT are valid

TIS_PC_VALID

#define TIS_PC_VALID   BIT7

This bit is a 1 to indicate that the other bits in this register are valid.

TIS_TIMEOUT_A

#define TIS_TIMEOUT_A   (750 * 1000)

TIS_TIMEOUT_B

#define TIS_TIMEOUT_B   (2000 * 1000)

TIS_TIMEOUT_C

#define TIS_TIMEOUT_C   (750 * 1000)

TIS_TIMEOUT_D

#define TIS_TIMEOUT_D   (750 * 1000)

Typedef Documentation

TIS_PC_REGISTERS_PTR

typedef TIS_PC_REGISTERS* TIS_PC_REGISTERS_PTR