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XenevaOS
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#include <i915_drm.h>
Public Attributes | |
| __u64 | size |
| __u32 | handle |
| __u32 | flags |
| __u64 | extensions |
DOC: GuC HWCONFIG blob uAPI
The GuC produces a blob with information about the current device. i915 reads this blob from GuC and makes it available via this uAPI.
The format and meaning of the blob content are documented in the Programmer's Reference Manual. struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added extension support using struct i915_user_extension.
Note that new buffer flags should be added here, at least for the stuff that is immutable. Previously we would have two ioctls, one to create the object with gem_create, and another to apply various parameters, however this creates some ambiguity for the params which are considered immutable. Also in general we're phasing out the various SET/GET ioctls.
| __u64 drm_i915_gem_create_ext::extensions |
| __u32 drm_i915_gem_create_ext::flags |
| __u32 drm_i915_gem_create_ext::handle |
@handle: Returned handle for the object.
Object handles are nonzero.
| __u64 drm_i915_gem_create_ext::size |
@size: Requested size for the object.
The (page-aligned) allocated size for the object will be returned.
On platforms like DG2/ATS the kernel will always use 64K or larger pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a minimum of 64K GTT alignment for such objects.
NOTE: Previously the ABI here required a minimum GTT alignment of 2M on DG2/ATS, due to how the hardware implemented 64K GTT page support, where we had the following complications:
1) The entire PDE (which covers a 2MB virtual address range), must contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same PDE is forbidden by the hardware.
2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM objects.
However on actual production HW this was completely changed to now allow setting a TLB hint at the PTE level (see PS64), which is a lot more flexible than the above. With this the 2M restriction was dropped where we now only require 64K.