i915_drm.h

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/*
 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */
 
#ifndef _UAPI_I915_DRM_H_
#define _UAPI_I915_DRM_H_
 
#include "drm.h"
 
#if defined(__cplusplus)
extern "C" {
#endif
 
/* Please note that modifications to all structs defined here are
 * subject to backwards-compatibility constraints.
 */
 
#define I915_L3_PARITY_UEVENT       "L3_PARITY_ERROR"
#define I915_ERROR_UEVENT       "ERROR"
#define I915_RESET_UEVENT       "RESET"
 
struct i915_user_extension {
    __u64 next_extension;
    __u32 name;
    __u32 flags;
    __u32 rsvd[4];
};
 
/*
 * MOCS indexes used for GPU surfaces, defining the cacheability of the
 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
 */
enum i915_mocs_table_index {
    /*
     * Not cached anywhere, coherency between CPU and GPU accesses is
     * guaranteed.
     */
    I915_MOCS_UNCACHED,
    /*
     * Cacheability and coherency controlled by the kernel automatically
     * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
     * usage of the surface (used for display scanout or not).
     */
    I915_MOCS_PTE,
    /*
     * Cached in all GPU caches available on the platform.
     * Coherency between CPU and GPU accesses to the surface is not
     * guaranteed without extra synchronization.
     */
    I915_MOCS_CACHED,
};
 
enum drm_i915_gem_engine_class {
    I915_ENGINE_CLASS_RENDER    = 0,
 
    I915_ENGINE_CLASS_COPY      = 1,
 
    I915_ENGINE_CLASS_VIDEO     = 2,
 
    I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
 
    I915_ENGINE_CLASS_COMPUTE   = 4,
 
    /* Values in this enum should be kept compact. */
 
    I915_ENGINE_CLASS_INVALID   = -1
};
 
struct i915_engine_class_instance {
    __u16 engine_class;
#define I915_ENGINE_CLASS_INVALID_NONE -1
#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
 
    __u16 engine_instance;
};
 
enum drm_i915_pmu_engine_sample {
    I915_SAMPLE_BUSY = 0,
    I915_SAMPLE_WAIT = 1,
    I915_SAMPLE_SEMA = 2
};
 
#define I915_PMU_SAMPLE_BITS (4)
#define I915_PMU_SAMPLE_MASK (0xf)
#define I915_PMU_SAMPLE_INSTANCE_BITS (8)
#define I915_PMU_CLASS_SHIFT \
    (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
 
#define __I915_PMU_ENGINE(class, instance, sample) \
    ((class) << I915_PMU_CLASS_SHIFT | \
    (instance) << I915_PMU_SAMPLE_BITS | \
    (sample))
 
#define I915_PMU_ENGINE_BUSY(class, instance) \
    __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
 
#define I915_PMU_ENGINE_WAIT(class, instance) \
    __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
 
#define I915_PMU_ENGINE_SEMA(class, instance) \
    __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
 
/*
 * Top 4 bits of every non-engine counter are GT id.
 */
#define __I915_PMU_GT_SHIFT (60)
 
#define ___I915_PMU_OTHER(gt, x) \
    (((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \
    ((__u64)(gt) << __I915_PMU_GT_SHIFT))
 
#define __I915_PMU_OTHER(x) ___I915_PMU_OTHER(0, x)
 
#define I915_PMU_ACTUAL_FREQUENCY   __I915_PMU_OTHER(0)
#define I915_PMU_REQUESTED_FREQUENCY    __I915_PMU_OTHER(1)
#define I915_PMU_INTERRUPTS     __I915_PMU_OTHER(2)
#define I915_PMU_RC6_RESIDENCY      __I915_PMU_OTHER(3)
#define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4)
 
#define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
 
#define __I915_PMU_ACTUAL_FREQUENCY(gt)     ___I915_PMU_OTHER(gt, 0)
#define __I915_PMU_REQUESTED_FREQUENCY(gt)  ___I915_PMU_OTHER(gt, 1)
#define __I915_PMU_INTERRUPTS(gt)       ___I915_PMU_OTHER(gt, 2)
#define __I915_PMU_RC6_RESIDENCY(gt)        ___I915_PMU_OTHER(gt, 3)
#define __I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt)   ___I915_PMU_OTHER(gt, 4)
 
/* Each region is a minimum of 16k, and there are at most 255 of them.
 */
#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
                 * of chars for next/prev indices */
#define I915_LOG_MIN_TEX_REGION_SIZE 14
 
typedef struct _drm_i915_init {
    enum {
        I915_INIT_DMA = 0x01,
        I915_CLEANUP_DMA = 0x02,
        I915_RESUME_DMA = 0x03
    } func;
    unsigned int mmio_offset;
    int sarea_priv_offset;
    unsigned int ring_start;
    unsigned int ring_end;
    unsigned int ring_size;
    unsigned int front_offset;
    unsigned int back_offset;
    unsigned int depth_offset;
    unsigned int w;
    unsigned int h;
    unsigned int pitch;
    unsigned int pitch_bits;
    unsigned int back_pitch;
    unsigned int depth_pitch;
    unsigned int cpp;
    unsigned int chipset;
} drm_i915_init_t;
 
typedef struct _drm_i915_sarea {
    struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
    int last_upload;    /* last time texture was uploaded */
    int last_enqueue;   /* last time a buffer was enqueued */
    int last_dispatch;  /* age of the most recently dispatched buffer */
    int ctxOwner;       /* last context to upload state */
    int texAge;
    int pf_enabled;     /* is pageflipping allowed? */
    int pf_active;
    int pf_current_page;    /* which buffer is being displayed? */
    int perf_boxes;     /* performance boxes to be displayed */
    int width, height;      /* screen size in pixels */
 
    drm_handle_t front_handle;
    int front_offset;
    int front_size;
 
    drm_handle_t back_handle;
    int back_offset;
    int back_size;
 
    drm_handle_t depth_handle;
    int depth_offset;
    int depth_size;
 
    drm_handle_t tex_handle;
    int tex_offset;
    int tex_size;
    int log_tex_granularity;
    int pitch;
    int rotation;           /* 0, 90, 180 or 270 */
    int rotated_offset;
    int rotated_size;
    int rotated_pitch;
    int virtualX, virtualY;
 
    unsigned int front_tiled;
    unsigned int back_tiled;
    unsigned int depth_tiled;
    unsigned int rotated_tiled;
    unsigned int rotated2_tiled;
 
    int pipeA_x;
    int pipeA_y;
    int pipeA_w;
    int pipeA_h;
    int pipeB_x;
    int pipeB_y;
    int pipeB_w;
    int pipeB_h;
 
    /* fill out some space for old userspace triple buffer */
    drm_handle_t unused_handle;
    __u32 unused1, unused2, unused3;
 
    /* buffer object handles for static buffers. May change
     * over the lifetime of the client.
     */
    __u32 front_bo_handle;
    __u32 back_bo_handle;
    __u32 unused_bo_handle;
    __u32 depth_bo_handle;
 
} drm_i915_sarea_t;
 
/* due to userspace building against these headers we need some compat here */
#define planeA_x pipeA_x
#define planeA_y pipeA_y
#define planeA_w pipeA_w
#define planeA_h pipeA_h
#define planeB_x pipeB_x
#define planeB_y pipeB_y
#define planeB_w pipeB_w
#define planeB_h pipeB_h
 
/* Flags for perf_boxes
 */
#define I915_BOX_RING_EMPTY    0x1
#define I915_BOX_FLIP          0x2
#define I915_BOX_WAIT          0x4
#define I915_BOX_TEXTURE_LOAD  0x8
#define I915_BOX_LOST_CONTEXT  0x10
 
/*
 * i915 specific ioctls.
 *
 * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
 * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
 * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
 */
#define DRM_I915_INIT       0x00
#define DRM_I915_FLUSH      0x01
#define DRM_I915_FLIP       0x02
#define DRM_I915_BATCHBUFFER    0x03
#define DRM_I915_IRQ_EMIT   0x04
#define DRM_I915_IRQ_WAIT   0x05
#define DRM_I915_GETPARAM   0x06
#define DRM_I915_SETPARAM   0x07
#define DRM_I915_ALLOC      0x08
#define DRM_I915_FREE       0x09
#define DRM_I915_INIT_HEAP  0x0a
#define DRM_I915_CMDBUFFER  0x0b
#define DRM_I915_DESTROY_HEAP   0x0c
#define DRM_I915_SET_VBLANK_PIPE    0x0d
#define DRM_I915_GET_VBLANK_PIPE    0x0e
#define DRM_I915_VBLANK_SWAP    0x0f
#define DRM_I915_HWS_ADDR   0x11
#define DRM_I915_GEM_INIT   0x13
#define DRM_I915_GEM_EXECBUFFER 0x14
#define DRM_I915_GEM_PIN    0x15
#define DRM_I915_GEM_UNPIN  0x16
#define DRM_I915_GEM_BUSY   0x17
#define DRM_I915_GEM_THROTTLE   0x18
#define DRM_I915_GEM_ENTERVT    0x19
#define DRM_I915_GEM_LEAVEVT    0x1a
#define DRM_I915_GEM_CREATE 0x1b
#define DRM_I915_GEM_PREAD  0x1c
#define DRM_I915_GEM_PWRITE 0x1d
#define DRM_I915_GEM_MMAP   0x1e
#define DRM_I915_GEM_SET_DOMAIN 0x1f
#define DRM_I915_GEM_SW_FINISH  0x20
#define DRM_I915_GEM_SET_TILING 0x21
#define DRM_I915_GEM_GET_TILING 0x22
#define DRM_I915_GEM_GET_APERTURE 0x23
#define DRM_I915_GEM_MMAP_GTT   0x24
#define DRM_I915_GET_PIPE_FROM_CRTC_ID  0x25
#define DRM_I915_GEM_MADVISE    0x26
#define DRM_I915_OVERLAY_PUT_IMAGE  0x27
#define DRM_I915_OVERLAY_ATTRS  0x28
#define DRM_I915_GEM_EXECBUFFER2    0x29
#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
#define DRM_I915_GET_SPRITE_COLORKEY    0x2a
#define DRM_I915_SET_SPRITE_COLORKEY    0x2b
#define DRM_I915_GEM_WAIT   0x2c
#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
#define DRM_I915_GEM_CONTEXT_DESTROY    0x2e
#define DRM_I915_GEM_SET_CACHING    0x2f
#define DRM_I915_GEM_GET_CACHING    0x30
#define DRM_I915_REG_READ       0x31
#define DRM_I915_GET_RESET_STATS    0x32
#define DRM_I915_GEM_USERPTR        0x33
#define DRM_I915_GEM_CONTEXT_GETPARAM   0x34
#define DRM_I915_GEM_CONTEXT_SETPARAM   0x35
#define DRM_I915_PERF_OPEN      0x36
#define DRM_I915_PERF_ADD_CONFIG    0x37
#define DRM_I915_PERF_REMOVE_CONFIG 0x38
#define DRM_I915_QUERY          0x39
#define DRM_I915_GEM_VM_CREATE      0x3a
#define DRM_I915_GEM_VM_DESTROY     0x3b
#define DRM_I915_GEM_CREATE_EXT     0x3c
/* Must be kept compact -- no holes */
 
#define DRM_IOCTL_I915_INIT     DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
#define DRM_IOCTL_I915_FLUSH        DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
#define DRM_IOCTL_I915_FLIP     DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
#define DRM_IOCTL_I915_BATCHBUFFER  DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
#define DRM_IOCTL_I915_IRQ_EMIT         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
#define DRM_IOCTL_I915_IRQ_WAIT         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
#define DRM_IOCTL_I915_GETPARAM         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
#define DRM_IOCTL_I915_SETPARAM         DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
#define DRM_IOCTL_I915_ALLOC            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
#define DRM_IOCTL_I915_FREE             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
#define DRM_IOCTL_I915_INIT_HEAP        DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
#define DRM_IOCTL_I915_CMDBUFFER    DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
#define DRM_IOCTL_I915_SET_VBLANK_PIPE  DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
#define DRM_IOCTL_I915_GET_VBLANK_PIPE  DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
#define DRM_IOCTL_I915_VBLANK_SWAP  DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
#define DRM_IOCTL_I915_HWS_ADDR     DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
#define DRM_IOCTL_I915_GEM_INIT     DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
#define DRM_IOCTL_I915_GEM_EXECBUFFER   DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
#define DRM_IOCTL_I915_GEM_EXECBUFFER2  DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR   DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
#define DRM_IOCTL_I915_GEM_PIN      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
#define DRM_IOCTL_I915_GEM_UNPIN    DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
#define DRM_IOCTL_I915_GEM_BUSY     DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
#define DRM_IOCTL_I915_GEM_SET_CACHING      DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
#define DRM_IOCTL_I915_GEM_GET_CACHING      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
#define DRM_IOCTL_I915_GEM_ENTERVT  DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
#define DRM_IOCTL_I915_GEM_LEAVEVT  DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
#define DRM_IOCTL_I915_GEM_CREATE   DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
#define DRM_IOCTL_I915_GEM_CREATE_EXT   DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext)
#define DRM_IOCTL_I915_GEM_PREAD    DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
#define DRM_IOCTL_I915_GEM_PWRITE   DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
#define DRM_IOCTL_I915_GEM_MMAP     DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
#define DRM_IOCTL_I915_GEM_MMAP_OFFSET  DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset)
#define DRM_IOCTL_I915_GEM_SET_DOMAIN   DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
#define DRM_IOCTL_I915_GEM_SW_FINISH    DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
#define DRM_IOCTL_I915_GEM_SET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
#define DRM_IOCTL_I915_GEM_GET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
#define DRM_IOCTL_I915_GEM_MADVISE  DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE    DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
#define DRM_IOCTL_I915_OVERLAY_ATTRS    DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
#define DRM_IOCTL_I915_GEM_WAIT     DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY  DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
#define DRM_IOCTL_I915_REG_READ         DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
#define DRM_IOCTL_I915_GET_RESET_STATS      DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
#define DRM_IOCTL_I915_GEM_USERPTR          DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
#define DRM_IOCTL_I915_PERF_OPEN    DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
#define DRM_IOCTL_I915_PERF_ADD_CONFIG  DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG   DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
#define DRM_IOCTL_I915_QUERY            DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
#define DRM_IOCTL_I915_GEM_VM_CREATE    DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
#define DRM_IOCTL_I915_GEM_VM_DESTROY   DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
 
/* Allow drivers to submit batchbuffers directly to hardware, relying
 * on the security mechanisms provided by hardware.
 */
typedef struct drm_i915_batchbuffer {
    int start;      /* agp offset */
    int used;       /* nr bytes in use */
    int DR1;        /* hw flags for GFX_OP_DRAWRECT_INFO */
    int DR4;        /* window origin for GFX_OP_DRAWRECT_INFO */
    int num_cliprects;  /* mulitpass with multiple cliprects? */
    struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
} drm_i915_batchbuffer_t;
 
/* As above, but pass a pointer to userspace buffer which can be
 * validated by the kernel prior to sending to hardware.
 */
typedef struct _drm_i915_cmdbuffer {
    char __user *buf;   /* pointer to userspace command buffer */
    int sz;         /* nr bytes in buf */
    int DR1;        /* hw flags for GFX_OP_DRAWRECT_INFO */
    int DR4;        /* window origin for GFX_OP_DRAWRECT_INFO */
    int num_cliprects;  /* mulitpass with multiple cliprects? */
    struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
} drm_i915_cmdbuffer_t;
 
/* Userspace can request & wait on irq's:
 */
typedef struct drm_i915_irq_emit {
    int __user *irq_seq;
} drm_i915_irq_emit_t;
 
typedef struct drm_i915_irq_wait {
    int irq_seq;
} drm_i915_irq_wait_t;
 
/*
 * Different modes of per-process Graphics Translation Table,
 * see I915_PARAM_HAS_ALIASING_PPGTT
 */
#define I915_GEM_PPGTT_NONE 0
#define I915_GEM_PPGTT_ALIASING 1
#define I915_GEM_PPGTT_FULL 2
 
/* Ioctl to query kernel params:
 */
#define I915_PARAM_IRQ_ACTIVE            1
#define I915_PARAM_ALLOW_BATCHBUFFER     2
#define I915_PARAM_LAST_DISPATCH         3
#define I915_PARAM_CHIPSET_ID            4
#define I915_PARAM_HAS_GEM               5
#define I915_PARAM_NUM_FENCES_AVAIL      6
#define I915_PARAM_HAS_OVERLAY           7
#define I915_PARAM_HAS_PAGEFLIPPING  8
#define I915_PARAM_HAS_EXECBUF2          9
#define I915_PARAM_HAS_BSD       10
#define I915_PARAM_HAS_BLT       11
#define I915_PARAM_HAS_RELAXED_FENCING   12
#define I915_PARAM_HAS_COHERENT_RINGS    13
#define I915_PARAM_HAS_EXEC_CONSTANTS    14
#define I915_PARAM_HAS_RELAXED_DELTA     15
#define I915_PARAM_HAS_GEN7_SOL_RESET    16
#define I915_PARAM_HAS_LLC           17
#define I915_PARAM_HAS_ALIASING_PPGTT    18
#define I915_PARAM_HAS_WAIT_TIMEOUT  19
#define I915_PARAM_HAS_SEMAPHORES    20
#define I915_PARAM_HAS_PRIME_VMAP_FLUSH  21
#define I915_PARAM_HAS_VEBOX         22
#define I915_PARAM_HAS_SECURE_BATCHES    23
#define I915_PARAM_HAS_PINNED_BATCHES    24
#define I915_PARAM_HAS_EXEC_NO_RELOC     25
#define I915_PARAM_HAS_EXEC_HANDLE_LUT   26
#define I915_PARAM_HAS_WT            27
#define I915_PARAM_CMD_PARSER_VERSION    28
#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
#define I915_PARAM_MMAP_VERSION          30
#define I915_PARAM_HAS_BSD2      31
#define I915_PARAM_REVISION              32
#define I915_PARAM_SUBSLICE_TOTAL    33
#define I915_PARAM_EU_TOTAL      34
#define I915_PARAM_HAS_GPU_RESET     35
#define I915_PARAM_HAS_RESOURCE_STREAMER 36
#define I915_PARAM_HAS_EXEC_SOFTPIN  37
#define I915_PARAM_HAS_POOLED_EU     38
#define I915_PARAM_MIN_EU_IN_POOL    39
#define I915_PARAM_MMAP_GTT_VERSION  40
 
/*
 * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
 * priorities and the driver will attempt to execute batches in priority order.
 * The param returns a capability bitmask, nonzero implies that the scheduler
 * is enabled, with different features present according to the mask.
 *
 * The initial priority for each batch is supplied by the context and is
 * controlled via I915_CONTEXT_PARAM_PRIORITY.
 */
#define I915_PARAM_HAS_SCHEDULER     41
#define   I915_SCHEDULER_CAP_ENABLED    (1ul << 0)
#define   I915_SCHEDULER_CAP_PRIORITY   (1ul << 1)
#define   I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
#define   I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
#define   I915_SCHEDULER_CAP_ENGINE_BUSY_STATS  (1ul << 4)
/*
 * Indicates the 2k user priority levels are statically mapped into 3 buckets as
 * follows:
 *
 * -1k to -1    Low priority
 * 0        Normal priority
 * 1 to 1k  Highest priority
 */
#define   I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP    (1ul << 5)
 
/*
 * Query the status of HuC load.
 *
 * The query can fail in the following scenarios with the listed error codes:
 *  -ENODEV if HuC is not present on this platform,
 *  -EOPNOTSUPP if HuC firmware usage is disabled,
 *  -ENOPKG if HuC firmware fetch failed,
 *  -ENOEXEC if HuC firmware is invalid or mismatched,
 *  -ENOMEM if i915 failed to prepare the FW objects for transfer to the uC,
 *  -EIO if the FW transfer or the FW authentication failed.
 *
 * If the IOCTL is successful, the returned parameter will be set to one of the
 * following values:
 *  * 0 if HuC firmware load is not complete,
 *  * 1 if HuC firmware is loaded and fully authenticated,
 *  * 2 if HuC firmware is loaded and authenticated for clear media only
 */
#define I915_PARAM_HUC_STATUS        42
 
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
 * synchronisation with implicit fencing on individual objects.
 * See EXEC_OBJECT_ASYNC.
 */
#define I915_PARAM_HAS_EXEC_ASYNC    43
 
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
 * both being able to pass in a sync_file fd to wait upon before executing,
 * and being able to return a new sync_file fd that is signaled when the
 * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
 */
#define I915_PARAM_HAS_EXEC_FENCE    44
 
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
 * user-specified buffers for post-mortem debugging of GPU hangs. See
 * EXEC_OBJECT_CAPTURE.
 */
#define I915_PARAM_HAS_EXEC_CAPTURE  45
 
#define I915_PARAM_SLICE_MASK        46
 
/* Assuming it's uniform for each slice, this queries the mask of subslices
 * per-slice for this system.
 */
#define I915_PARAM_SUBSLICE_MASK     47
 
/*
 * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer
 * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST.
 */
#define I915_PARAM_HAS_EXEC_BATCH_FIRST  48
 
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
 * drm_i915_gem_exec_fence structures.  See I915_EXEC_FENCE_ARRAY.
 */
#define I915_PARAM_HAS_EXEC_FENCE_ARRAY  49
 
/*
 * Query whether every context (both per-file default and user created) is
 * isolated (insofar as HW supports). If this parameter is not true, then
 * freshly created contexts may inherit values from an existing context,
 * rather than default HW values. If true, it also ensures (insofar as HW
 * supports) that all state set by this context will not leak to any other
 * context.
 *
 * As not every engine across every gen support contexts, the returned
 * value reports the support of context isolation for individual engines by
 * returning a bitmask of each engine class set to true if that class supports
 * isolation.
 */
#define I915_PARAM_HAS_CONTEXT_ISOLATION 50
 
/* Frequency of the command streamer timestamps given by the *_TIMESTAMP
 * registers. This used to be fixed per platform but from CNL onwards, this
 * might vary depending on the parts.
 */
#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
 
/*
 * Once upon a time we supposed that writes through the GGTT would be
 * immediately in physical memory (once flushed out of the CPU path). However,
 * on a few different processors and chipsets, this is not necessarily the case
 * as the writes appear to be buffered internally. Thus a read of the backing
 * storage (physical memory) via a different path (with different physical tags
 * to the indirect write via the GGTT) will see stale values from before
 * the GGTT write. Inside the kernel, we can for the most part keep track of
 * the different read/write domains in use (e.g. set-domain), but the assumption
 * of coherency is baked into the ABI, hence reporting its true state in this
 * parameter.
 *
 * Reports true when writes via mmap_gtt are immediately visible following an
 * lfence to flush the WCB.
 *
 * Reports false when writes via mmap_gtt are indeterminately delayed in an in
 * internal buffer and are _not_ immediately visible to third parties accessing
 * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
 * communications channel when reporting false is strongly disadvised.
 */
#define I915_PARAM_MMAP_GTT_COHERENT    52
 
/*
 * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
 * execution through use of explicit fence support.
 * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
 */
#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
 
/*
 * Revision of the i915-perf uAPI. The value returned helps determine what
 * i915-perf features are available. See drm_i915_perf_property_id.
 */
#define I915_PARAM_PERF_REVISION    54
 
/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
 * timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See
 * I915_EXEC_USE_EXTENSIONS.
 */
#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
 
/* Query if the kernel supports the I915_USERPTR_PROBE flag. */
#define I915_PARAM_HAS_USERPTR_PROBE 56
 
/*
 * Frequency of the timestamps in OA reports. This used to be the same as the CS
 * timestamp frequency, but differs on some platforms.
 */
#define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57
 
/*
 * Query the status of PXP support in i915.
 *
 * The query can fail in the following scenarios with the listed error codes:
 *     -ENODEV = PXP support is not available on the GPU device or in the
 *               kernel due to missing component drivers or kernel configs.
 *
 * If the IOCTL is successful, the returned parameter will be set to one of
 * the following values:
 *     1 = PXP feature is supported and is ready for use.
 *     2 = PXP feature is supported but should be ready soon (pending
 *         initialization of non-i915 system dependencies).
 *
 * NOTE: When param is supported (positive return values), user space should
 *       still refer to the GEM PXP context-creation UAPI header specs to be
 *       aware of possible failure due to system state machine at the time.
 */
#define I915_PARAM_PXP_STATUS        58
 
/*
 * Query if kernel allows marking a context to send a Freq hint to SLPC. This
 * will enable use of the strategies allowed by the SLPC algorithm.
 */
#define I915_PARAM_HAS_CONTEXT_FREQ_HINT    59
 
/* Must be kept compact -- no holes and well documented */
 
struct drm_i915_getparam {
    __s32 param;
 
    int __user *value;
};
 
typedef struct drm_i915_getparam drm_i915_getparam_t;
 
/* Ioctl to set kernel params:
 */
#define I915_SETPARAM_USE_MI_BATCHBUFFER_START            1
#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY             2
#define I915_SETPARAM_ALLOW_BATCHBUFFER                   3
#define I915_SETPARAM_NUM_USED_FENCES                     4
/* Must be kept compact -- no holes */
 
typedef struct drm_i915_setparam {
    int param;
    int value;
} drm_i915_setparam_t;
 
/* A memory manager for regions of shared memory:
 */
#define I915_MEM_REGION_AGP 1
 
typedef struct drm_i915_mem_alloc {
    int region;
    int alignment;
    int size;
    int __user *region_offset;  /* offset from start of fb or agp */
} drm_i915_mem_alloc_t;
 
typedef struct drm_i915_mem_free {
    int region;
    int region_offset;
} drm_i915_mem_free_t;
 
typedef struct drm_i915_mem_init_heap {
    int region;
    int size;
    int start;
} drm_i915_mem_init_heap_t;
 
/* Allow memory manager to be torn down and re-initialized (eg on
 * rotate):
 */
typedef struct drm_i915_mem_destroy_heap {
    int region;
} drm_i915_mem_destroy_heap_t;
 
/* Allow X server to configure which pipes to monitor for vblank signals
 */
#define DRM_I915_VBLANK_PIPE_A  1
#define DRM_I915_VBLANK_PIPE_B  2
 
typedef struct drm_i915_vblank_pipe {
    int pipe;
} drm_i915_vblank_pipe_t;
 
/* Schedule buffer swap at given vertical blank:
 */
typedef struct drm_i915_vblank_swap {
    drm_drawable_t drawable;
    enum drm_vblank_seq_type seqtype;
    unsigned int sequence;
} drm_i915_vblank_swap_t;
 
typedef struct drm_i915_hws_addr {
    __u64 addr;
} drm_i915_hws_addr_t;
 
struct drm_i915_gem_init {
    __u64 gtt_start;
    __u64 gtt_end;
};
 
struct drm_i915_gem_create {
    __u64 size;
    __u32 handle;
    __u32 pad;
};
 
struct drm_i915_gem_pread {
    __u32 handle;
    __u32 pad;
    __u64 offset;
    __u64 size;
    __u64 data_ptr;
};
 
struct drm_i915_gem_pwrite {
    __u32 handle;
    __u32 pad;
    __u64 offset;
    __u64 size;
    __u64 data_ptr;
};
 
struct drm_i915_gem_mmap {
    __u32 handle;
    __u32 pad;
    __u64 offset;
    __u64 size;
    __u64 addr_ptr;
 
    __u64 flags;
#define I915_MMAP_WC 0x1
};
 
struct drm_i915_gem_mmap_gtt {
    __u32 handle;
    __u32 pad;
    __u64 offset;
};
 
struct drm_i915_gem_mmap_offset {
    __u32 handle;
    __u32 pad;
    __u64 offset;
 
    __u64 flags;
 
#define I915_MMAP_OFFSET_GTT    0
#define I915_MMAP_OFFSET_WC 1
#define I915_MMAP_OFFSET_WB 2
#define I915_MMAP_OFFSET_UC 3
#define I915_MMAP_OFFSET_FIXED  4
 
    __u64 extensions;
};
 
struct drm_i915_gem_set_domain {
    __u32 handle;
 
    __u32 read_domains;
 
    __u32 write_domain;
};
 
struct drm_i915_gem_sw_finish {
    __u32 handle;
};
 
struct drm_i915_gem_relocation_entry {
    __u32 target_handle;
 
    __u32 delta;
 
    __u64 offset;
 
    __u64 presumed_offset;
 
    __u32 read_domains;
 
    __u32 write_domain;
};
 
#define I915_GEM_DOMAIN_CPU     0x00000001
#define I915_GEM_DOMAIN_RENDER      0x00000002
#define I915_GEM_DOMAIN_SAMPLER     0x00000004
#define I915_GEM_DOMAIN_COMMAND     0x00000008
#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
#define I915_GEM_DOMAIN_VERTEX      0x00000020
#define I915_GEM_DOMAIN_GTT     0x00000040
#define I915_GEM_DOMAIN_WC      0x00000080
struct drm_i915_gem_exec_object {
    __u32 handle;
 
    __u32 relocation_count;
    __u64 relocs_ptr;
 
    __u64 alignment;
 
    __u64 offset;
};
 
/* DRM_IOCTL_I915_GEM_EXECBUFFER was removed in Linux 5.13 */
struct drm_i915_gem_execbuffer {
    __u64 buffers_ptr;
    __u32 buffer_count;
 
    __u32 batch_start_offset;
    __u32 batch_len;
    __u32 DR1;
    __u32 DR4;
    __u32 num_cliprects;
    __u64 cliprects_ptr;
};
 
struct drm_i915_gem_exec_object2 {
    __u32 handle;
 
    __u32 relocation_count;
    __u64 relocs_ptr;
 
    __u64 alignment;
 
    __u64 offset;
 
#define EXEC_OBJECT_NEEDS_FENCE      (1<<0)
#define EXEC_OBJECT_NEEDS_GTT        (1<<1)
#define EXEC_OBJECT_WRITE        (1<<2)
#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
#define EXEC_OBJECT_PINNED       (1<<4)
#define EXEC_OBJECT_PAD_TO_SIZE      (1<<5)
/* The kernel implicitly tracks GPU activity on all GEM objects, and
 * synchronises operations with outstanding rendering. This includes
 * rendering on other devices if exported via dma-buf. However, sometimes
 * this tracking is too coarse and the user knows better. For example,
 * if the object is split into non-overlapping ranges shared between different
 * clients or engines (i.e. suballocating objects), the implicit tracking
 * by kernel assumes that each operation affects the whole object rather
 * than an individual range, causing needless synchronisation between clients.
 * The kernel will also forgo any CPU cache flushes prior to rendering from
 * the object as the client is expected to be also handling such domain
 * tracking.
 *
 * The kernel maintains the implicit tracking in order to manage resources
 * used by the GPU - this flag only disables the synchronisation prior to
 * rendering with this object in this execbuf.
 *
 * Opting out of implicit synhronisation requires the user to do its own
 * explicit tracking to avoid rendering corruption. See, for example,
 * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
 */
#define EXEC_OBJECT_ASYNC       (1<<6)
/* Request that the contents of this execobject be copied into the error
 * state upon a GPU hang involving this batch for post-mortem debugging.
 * These buffers are recorded in no particular order as "user" in
 * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
 * if the kernel supports this flag.
 */
#define EXEC_OBJECT_CAPTURE     (1<<7)
/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
    __u64 flags;
 
    union {
        __u64 rsvd1;
        __u64 pad_to_size;
    };
    __u64 rsvd2;
};
 
struct drm_i915_gem_exec_fence {
    __u32 handle;
 
    __u32 flags;
#define I915_EXEC_FENCE_WAIT            (1<<0)
#define I915_EXEC_FENCE_SIGNAL          (1<<1)
#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
};
 
struct drm_i915_gem_execbuffer_ext_timeline_fences {
#define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
    struct i915_user_extension base;
 
    __u64 fence_count;
 
    __u64 handles_ptr;
 
    __u64 values_ptr;
};
 
struct drm_i915_gem_execbuffer2 {
    __u64 buffers_ptr;
 
    __u32 buffer_count;
 
    __u32 batch_start_offset;
 
    __u32 batch_len;
 
    __u32 DR1;
 
    __u32 DR4;
 
    __u32 num_cliprects;
 
    __u64 cliprects_ptr;
 
    __u64 flags;
#define I915_EXEC_RING_MASK              (0x3f)
#define I915_EXEC_DEFAULT                (0<<0)
#define I915_EXEC_RENDER                 (1<<0)
#define I915_EXEC_BSD                    (2<<0)
#define I915_EXEC_BLT                    (3<<0)
#define I915_EXEC_VEBOX                  (4<<0)
 
/* Used for switching the constants addressing mode on gen4+ RENDER ring.
 * Gen6+ only supports relative addressing to dynamic state (default) and
 * absolute addressing.
 *
 * These flags are ignored for the BSD and BLT rings.
 */
#define I915_EXEC_CONSTANTS_MASK    (3<<6)
#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
#define I915_EXEC_CONSTANTS_ABSOLUTE    (1<<6)
#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
 
#define I915_EXEC_GEN7_SOL_RESET    (1<<8)
 
#define I915_EXEC_SECURE        (1<<9)
 
#define I915_EXEC_IS_PINNED     (1<<10)
 
#define I915_EXEC_NO_RELOC      (1<<11)
 
#define I915_EXEC_HANDLE_LUT        (1<<12)
 
#define I915_EXEC_BSD_SHIFT  (13)
#define I915_EXEC_BSD_MASK   (3 << I915_EXEC_BSD_SHIFT)
/* default ping-pong mode */
#define I915_EXEC_BSD_DEFAULT    (0 << I915_EXEC_BSD_SHIFT)
#define I915_EXEC_BSD_RING1  (1 << I915_EXEC_BSD_SHIFT)
#define I915_EXEC_BSD_RING2  (2 << I915_EXEC_BSD_SHIFT)
 
#define I915_EXEC_RESOURCE_STREAMER     (1<<15)
 
/* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
 * the batch.
 *
 * Returns -EINVAL if the sync_file fd cannot be found.
 */
#define I915_EXEC_FENCE_IN      (1<<16)
 
/* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
 * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
 * to the caller, and it should be close() after use. (The fd is a regular
 * file descriptor and will be cleaned up on process termination. It holds
 * a reference to the request, but nothing else.)
 *
 * The sync_file fd can be combined with other sync_file and passed either
 * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
 * will only occur after this request completes), or to other devices.
 *
 * Using I915_EXEC_FENCE_OUT requires use of
 * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
 * back to userspace. Failure to do so will cause the out-fence to always
 * be reported as zero, and the real fence fd to be leaked.
 */
#define I915_EXEC_FENCE_OUT     (1<<17)
 
/*
 * Traditionally the execbuf ioctl has only considered the final element in
 * the execobject[] to be the executable batch. Often though, the client
 * will known the batch object prior to construction and being able to place
 * it into the execobject[] array first can simplify the relocation tracking.
 * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the
 * execobject[] as the * batch instead (the default is to use the last
 * element).
 */
#define I915_EXEC_BATCH_FIRST       (1<<18)
 
/* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr
 * define an array of i915_gem_exec_fence structures which specify a set of
 * dma fences to wait upon or signal.
 */
#define I915_EXEC_FENCE_ARRAY   (1<<19)
 
/*
 * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
 * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
 * the batch.
 *
 * Returns -EINVAL if the sync_file fd cannot be found.
 */
#define I915_EXEC_FENCE_SUBMIT      (1 << 20)
 
/*
 * Setting I915_EXEC_USE_EXTENSIONS implies that
 * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked
 * list of i915_user_extension. Each i915_user_extension node is the base of a
 * larger structure. The list of supported structures are listed in the
 * drm_i915_gem_execbuffer_ext enum.
 */
#define I915_EXEC_USE_EXTENSIONS    (1 << 21)
#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1))
 
    __u64 rsvd1;
 
    __u64 rsvd2;
};
 
#define I915_EXEC_CONTEXT_ID_MASK   (0xffffffff)
#define i915_execbuffer2_set_context_id(eb2, context) \
    (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
#define i915_execbuffer2_get_context_id(eb2) \
    ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
 
struct drm_i915_gem_pin {
    __u32 handle;
    __u32 pad;
 
    __u64 alignment;
 
    __u64 offset;
};
 
struct drm_i915_gem_unpin {
    __u32 handle;
    __u32 pad;
};
 
struct drm_i915_gem_busy {
    __u32 handle;
 
    __u32 busy;
};
 
struct drm_i915_gem_caching {
    __u32 handle;
 
#define I915_CACHING_NONE       0
#define I915_CACHING_CACHED     1
#define I915_CACHING_DISPLAY        2
    __u32 caching;
};
 
#define I915_TILING_NONE    0
#define I915_TILING_X       1
#define I915_TILING_Y       2
/*
 * Do not add new tiling types here.  The I915_TILING_* values are for
 * de-tiling fence registers that no longer exist on modern platforms.  Although
 * the hardware may support new types of tiling in general (e.g., Tile4), we
 * do not need to add them to the uapi that is specific to now-defunct ioctls.
 */
#define I915_TILING_LAST    I915_TILING_Y
 
#define I915_BIT_6_SWIZZLE_NONE     0
#define I915_BIT_6_SWIZZLE_9        1
#define I915_BIT_6_SWIZZLE_9_10     2
#define I915_BIT_6_SWIZZLE_9_11     3
#define I915_BIT_6_SWIZZLE_9_10_11  4
/* Not seen by userland */
#define I915_BIT_6_SWIZZLE_UNKNOWN  5
/* Seen by userland. */
#define I915_BIT_6_SWIZZLE_9_17     6
#define I915_BIT_6_SWIZZLE_9_10_17  7
 
struct drm_i915_gem_set_tiling {
    __u32 handle;
 
    __u32 tiling_mode;
 
    __u32 stride;
 
    __u32 swizzle_mode;
};
 
struct drm_i915_gem_get_tiling {
    __u32 handle;
 
    __u32 tiling_mode;
 
    __u32 swizzle_mode;
 
    __u32 phys_swizzle_mode;
};
 
struct drm_i915_gem_get_aperture {
    __u64 aper_size;
 
    __u64 aper_available_size;
};
 
struct drm_i915_get_pipe_from_crtc_id {
    __u32 crtc_id;
 
    __u32 pipe;
};
 
#define I915_MADV_WILLNEED 0
#define I915_MADV_DONTNEED 1
#define __I915_MADV_PURGED 2 /* internal state */
 
struct drm_i915_gem_madvise {
    __u32 handle;
 
    /* Advice: either the buffer will be needed again in the near future,
     *         or won't be and could be discarded under memory pressure.
     */
    __u32 madv;
 
    __u32 retained;
};
 
/* flags */
#define I915_OVERLAY_TYPE_MASK      0xff
#define I915_OVERLAY_YUV_PLANAR     0x01
#define I915_OVERLAY_YUV_PACKED     0x02
#define I915_OVERLAY_RGB        0x03
 
#define I915_OVERLAY_DEPTH_MASK     0xff00
#define I915_OVERLAY_RGB24      0x1000
#define I915_OVERLAY_RGB16      0x2000
#define I915_OVERLAY_RGB15      0x3000
#define I915_OVERLAY_YUV422     0x0100
#define I915_OVERLAY_YUV411     0x0200
#define I915_OVERLAY_YUV420     0x0300
#define I915_OVERLAY_YUV410     0x0400
 
#define I915_OVERLAY_SWAP_MASK      0xff0000
#define I915_OVERLAY_NO_SWAP        0x000000
#define I915_OVERLAY_UV_SWAP        0x010000
#define I915_OVERLAY_Y_SWAP     0x020000
#define I915_OVERLAY_Y_AND_UV_SWAP  0x030000
 
#define I915_OVERLAY_FLAGS_MASK     0xff000000
#define I915_OVERLAY_ENABLE     0x01000000
 
struct drm_intel_overlay_put_image {
    /* various flags and src format description */
    __u32 flags;
    /* source picture description */
    __u32 bo_handle;
    /* stride values and offsets are in bytes, buffer relative */
    __u16 stride_Y; /* stride for packed formats */
    __u16 stride_UV;
    __u32 offset_Y; /* offset for packet formats */
    __u32 offset_U;
    __u32 offset_V;
    /* in pixels */
    __u16 src_width;
    __u16 src_height;
    /* to compensate the scaling factors for partially covered surfaces */
    __u16 src_scan_width;
    __u16 src_scan_height;
    /* output crtc description */
    __u32 crtc_id;
    __u16 dst_x;
    __u16 dst_y;
    __u16 dst_width;
    __u16 dst_height;
};
 
/* flags */
#define I915_OVERLAY_UPDATE_ATTRS   (1<<0)
#define I915_OVERLAY_UPDATE_GAMMA   (1<<1)
#define I915_OVERLAY_DISABLE_DEST_COLORKEY  (1<<2)
struct drm_intel_overlay_attrs {
    __u32 flags;
    __u32 color_key;
    __s32 brightness;
    __u32 contrast;
    __u32 saturation;
    __u32 gamma0;
    __u32 gamma1;
    __u32 gamma2;
    __u32 gamma3;
    __u32 gamma4;
    __u32 gamma5;
};
 
/*
 * Intel sprite handling
 *
 * Color keying works with a min/mask/max tuple.  Both source and destination
 * color keying is allowed.
 *
 * Source keying:
 * Sprite pixels within the min & max values, masked against the color channels
 * specified in the mask field, will be transparent.  All other pixels will
 * be displayed on top of the primary plane.  For RGB surfaces, only the min
 * and mask fields will be used; ranged compares are not allowed.
 *
 * Destination keying:
 * Primary plane pixels that match the min value, masked against the color
 * channels specified in the mask field, will be replaced by corresponding
 * pixels from the sprite plane.
 *
 * Note that source & destination keying are exclusive; only one can be
 * active on a given plane.
 */
 
#define I915_SET_COLORKEY_NONE      (1<<0) /* Deprecated. Instead set
                        * flags==0 to disable colorkeying.
                        */
#define I915_SET_COLORKEY_DESTINATION   (1<<1)
#define I915_SET_COLORKEY_SOURCE    (1<<2)
struct drm_intel_sprite_colorkey {
    __u32 plane_id;
    __u32 min_value;
    __u32 channel_mask;
    __u32 max_value;
    __u32 flags;
};
 
struct drm_i915_gem_wait {
    __u32 bo_handle;
    __u32 flags;
    __s64 timeout_ns;
};
 
struct drm_i915_gem_context_create {
    __u32 ctx_id; /* output: id of new context*/
    __u32 pad;
};
 
struct drm_i915_gem_context_create_ext {
    __u32 ctx_id;
 
    __u32 flags;
#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS    (1u << 0)
#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE   (1u << 1)
#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
    (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
 
    __u64 extensions;
#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
#define I915_CONTEXT_CREATE_EXT_CLONE 1
};
 
struct drm_i915_gem_context_param {
    __u32 ctx_id;
 
    __u32 size;
 
    __u64 param;
#define I915_CONTEXT_PARAM_BAN_PERIOD   0x1
/* I915_CONTEXT_PARAM_NO_ZEROMAP has been removed.  On the off chance
 * someone somewhere has attempted to use it, never re-use this context
 * param number.
 */
#define I915_CONTEXT_PARAM_NO_ZEROMAP   0x2
#define I915_CONTEXT_PARAM_GTT_SIZE 0x3
#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
#define I915_CONTEXT_PARAM_BANNABLE 0x5
#define I915_CONTEXT_PARAM_PRIORITY 0x6
#define   I915_CONTEXT_MAX_USER_PRIORITY    1023 /* inclusive */
#define   I915_CONTEXT_DEFAULT_PRIORITY     0
#define   I915_CONTEXT_MIN_USER_PRIORITY    -1023 /* inclusive */
    /*
     * When using the following param, value should be a pointer to
     * drm_i915_gem_context_param_sseu.
     */
#define I915_CONTEXT_PARAM_SSEU     0x7
 
/*
 * Not all clients may want to attempt automatic recover of a context after
 * a hang (for example, some clients may only submit very small incremental
 * batches relying on known logical state of previous batches which will never
 * recover correctly and each attempt will hang), and so would prefer that
 * the context is forever banned instead.
 *
 * If set to false (0), after a reset, subsequent (and in flight) rendering
 * from this context is discarded, and the client will need to create a new
 * context to use instead.
 *
 * If set to true (1), the kernel will automatically attempt to recover the
 * context by skipping the hanging batch and executing the next batch starting
 * from the default context state (discarding the incomplete logical context
 * state lost due to the reset).
 *
 * On creation, all new contexts are marked as recoverable.
 */
#define I915_CONTEXT_PARAM_RECOVERABLE  0x8
 
    /*
     * The id of the associated virtual memory address space (ppGTT) of
     * this context. Can be retrieved and passed to another context
     * (on the same fd) for both to use the same ppGTT and so share
     * address layouts, and avoid reloading the page tables on context
     * switches between themselves.
     *
     * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
     */
#define I915_CONTEXT_PARAM_VM       0x9
 
/*
 * I915_CONTEXT_PARAM_ENGINES:
 *
 * Bind this context to operate on this subset of available engines. Henceforth,
 * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
 * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
 * and upwards. Slots 0...N are filled in using the specified (class, instance).
 * Use
 *  engine_class: I915_ENGINE_CLASS_INVALID,
 *  engine_instance: I915_ENGINE_CLASS_INVALID_NONE
 * to specify a gap in the array that can be filled in later, e.g. by a
 * virtual engine used for load balancing.
 *
 * Setting the number of engines bound to the context to 0, by passing a zero
 * sized argument, will revert back to default settings.
 *
 * See struct i915_context_param_engines.
 *
 * Extensions:
 *   i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
 *   i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
 *   i915_context_engines_parallel_submit (I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT)
 */
#define I915_CONTEXT_PARAM_ENGINES  0xa
 
/*
 * I915_CONTEXT_PARAM_PERSISTENCE:
 *
 * Allow the context and active rendering to survive the process until
 * completion. Persistence allows fire-and-forget clients to queue up a
 * bunch of work, hand the output over to a display server and then quit.
 * If the context is marked as not persistent, upon closing (either via
 * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure
 * or process termination), the context and any outstanding requests will be
 * cancelled (and exported fences for cancelled requests marked as -EIO).
 *
 * By default, new contexts allow persistence.
 */
#define I915_CONTEXT_PARAM_PERSISTENCE  0xb
 
/* This API has been removed.  On the off chance someone somewhere has
 * attempted to use it, never re-use this context param number.
 */
#define I915_CONTEXT_PARAM_RINGSIZE 0xc
 
/*
 * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
 *
 * Mark that the context makes use of protected content, which will result
 * in the context being invalidated when the protected content session is.
 * Given that the protected content session is killed on suspend, the device
 * is kept awake for the lifetime of a protected context, so the user should
 * make sure to dispose of them once done.
 * This flag can only be set at context creation time and, when set to true,
 * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE
 * to false. This flag can't be set to true in conjunction with setting the
 * I915_CONTEXT_PARAM_BANNABLE flag to false. Creation example:
 *
 * .. code-block:: C
 *
 *  struct drm_i915_gem_context_create_ext_setparam p_protected = {
 *      .base = {
 *          .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
 *      },
 *      .param = {
 *          .param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
 *          .value = 1,
 *      }
 *  };
 *  struct drm_i915_gem_context_create_ext_setparam p_norecover = {
 *      .base = {
 *          .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
 *          .next_extension = to_user_pointer(&p_protected),
 *      },
 *      .param = {
 *          .param = I915_CONTEXT_PARAM_RECOVERABLE,
 *          .value = 0,
 *      }
 *  };
 *  struct drm_i915_gem_context_create_ext create = {
 *      .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
 *      .extensions = to_user_pointer(&p_norecover);
 *  };
 *
 *  ctx_id = gem_context_create_ext(drm_fd, &create);
 *
 * In addition to the normal failure cases, setting this flag during context
 * creation can result in the following errors:
 *
 * -ENODEV: feature not available
 * -EPERM: trying to mark a recoverable or not bannable context as protected
 * -ENXIO: A dependency such as a component driver or firmware is not yet
 *         loaded so user space may need to attempt again. Depending on the
 *         device, this error may be reported if protected context creation is
 *         attempted very early after kernel start because the internal timeout
 *         waiting for such dependencies is not guaranteed to be larger than
 *         required (numbers differ depending on system and kernel config):
 *            - ADL/RPL: dependencies may take up to 3 seconds from kernel start
 *                       while context creation internal timeout is 250 milisecs
 *            - MTL: dependencies may take up to 8 seconds from kernel start
 *                   while context creation internal timeout is 250 milisecs
 *         NOTE: such dependencies happen once, so a subsequent call to create a
 *         protected context after a prior successful call will not experience
 *         such timeouts and will not return -ENXIO (unless the driver is reloaded,
 *         or, depending on the device, resumes from a suspended state).
 * -EIO: The firmware did not succeed in creating the protected context.
 */
#define I915_CONTEXT_PARAM_PROTECTED_CONTENT    0xd
 
/*
 * I915_CONTEXT_PARAM_LOW_LATENCY:
 *
 * Mark this context as a low latency workload which requires aggressive GT
 * frequency scaling. Use I915_PARAM_HAS_CONTEXT_FREQ_HINT to check if the kernel
 * supports this per context flag.
 */
#define I915_CONTEXT_PARAM_LOW_LATENCY      0xe
 
/*
 * I915_CONTEXT_PARAM_CONTEXT_IMAGE:
 *
 * Allows userspace to provide own context images.
 *
 * Note that this is a debug API not available on production kernel builds.
 */
#define I915_CONTEXT_PARAM_CONTEXT_IMAGE    0xf
/* Must be kept compact -- no holes and well documented */
 
    __u64 value;
};
 
/*
 * Context SSEU programming
 *
 * It may be necessary for either functional or performance reason to configure
 * a context to run with a reduced number of SSEU (where SSEU stands for Slice/
 * Sub-slice/EU).
 *
 * This is done by configuring SSEU configuration using the below
 * @struct drm_i915_gem_context_param_sseu for every supported engine which
 * userspace intends to use.
 *
 * Not all GPUs or engines support this functionality in which case an error
 * code -ENODEV will be returned.
 *
 * Also, flexibility of possible SSEU configuration permutations varies between
 * GPU generations and software imposed limitations. Requesting such a
 * combination will return an error code of -EINVAL.
 *
 * NOTE: When perf/OA is active the context's SSEU configuration is ignored in
 * favour of a single global setting.
 */
struct drm_i915_gem_context_param_sseu {
    /*
     * Engine class & instance to be configured or queried.
     */
    struct i915_engine_class_instance engine;
 
    /*
     * Unknown flags must be cleared to zero.
     */
    __u32 flags;
#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
 
    /*
     * Mask of slices to enable for the context. Valid values are a subset
     * of the bitmask value returned for I915_PARAM_SLICE_MASK.
     */
    __u64 slice_mask;
 
    /*
     * Mask of subslices to enable for the context. Valid values are a
     * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
     */
    __u64 subslice_mask;
 
    /*
     * Minimum/Maximum number of EUs to enable per subslice for the
     * context. min_eus_per_subslice must be inferior or equal to
     * max_eus_per_subslice.
     */
    __u16 min_eus_per_subslice;
    __u16 max_eus_per_subslice;
 
    /*
     * Unused for now. Must be cleared to zero.
     */
    __u32 rsvd;
};
 
/*
 * i915_context_engines_load_balance:
 *
 * Enable load balancing across this set of engines.
 *
 * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
 * used will proxy the execbuffer request onto one of the set of engines
 * in such a way as to distribute the load evenly across the set.
 *
 * The set of engines must be compatible (e.g. the same HW class) as they
 * will share the same logical GPU context and ring.
 *
 * To intermix rendering with the virtual engine and direct rendering onto
 * the backing engines (bypassing the load balancing proxy), the context must
 * be defined to use a single timeline for all engines.
 */
struct i915_context_engines_load_balance {
    struct i915_user_extension base;
 
    __u16 engine_index;
    __u16 num_siblings;
    __u32 flags; /* all undefined flags must be zero */
 
    __u64 mbz64; /* reserved for future use; must be zero */
 
    struct i915_engine_class_instance engines[];
} __attribute__((packed));
 
#define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
    struct i915_user_extension base; \
    __u16 engine_index; \
    __u16 num_siblings; \
    __u32 flags; \
    __u64 mbz64; \
    struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
 
/*
 * i915_context_engines_bond:
 *
 * Constructed bonded pairs for execution within a virtual engine.
 *
 * All engines are equal, but some are more equal than others. Given
 * the distribution of resources in the HW, it may be preferable to run
 * a request on a given subset of engines in parallel to a request on a
 * specific engine. We enable this selection of engines within a virtual
 * engine by specifying bonding pairs, for any given master engine we will
 * only execute on one of the corresponding siblings within the virtual engine.
 *
 * To execute a request in parallel on the master engine and a sibling requires
 * coordination with a I915_EXEC_FENCE_SUBMIT.
 */
struct i915_context_engines_bond {
    struct i915_user_extension base;
 
    struct i915_engine_class_instance master;
 
    __u16 virtual_index; /* index of virtual engine in ctx->engines[] */
    __u16 num_bonds;
 
    __u64 flags; /* all undefined flags must be zero */
    __u64 mbz64[4]; /* reserved for future use; must be zero */
 
    struct i915_engine_class_instance engines[];
} __attribute__((packed));
 
#define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
    struct i915_user_extension base; \
    struct i915_engine_class_instance master; \
    __u16 virtual_index; \
    __u16 num_bonds; \
    __u64 flags; \
    __u64 mbz64[4]; \
    struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
 
struct i915_context_engines_parallel_submit {
    struct i915_user_extension base;
 
    __u16 engine_index;
 
    __u16 width;
 
    __u16 num_siblings;
 
    __u16 mbz16;
 
    __u64 flags;
 
    __u64 mbz64[3];
 
    struct i915_engine_class_instance engines[];
 
} __packed;
 
#define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__, N__) struct { \
    struct i915_user_extension base; \
    __u16 engine_index; \
    __u16 width; \
    __u16 num_siblings; \
    __u16 mbz16; \
    __u64 flags; \
    __u64 mbz64[3]; \
    struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
 
struct i915_context_param_engines {
    __u64 extensions; /* linked chain of extension blocks, 0 terminates */
#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
    struct i915_engine_class_instance engines[];
} __attribute__((packed));
 
#define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
    __u64 extensions; \
    struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__
 
struct i915_gem_context_param_context_image {
    struct i915_engine_class_instance engine;
 
    __u32 flags;
#define I915_CONTEXT_IMAGE_FLAG_ENGINE_INDEX (1u << 0)
 
    __u32 size;
 
    __u32 mbz;
 
    __u64 image;
} __attribute__((packed));
 
struct drm_i915_gem_context_create_ext_setparam {
    struct i915_user_extension base;
 
    struct drm_i915_gem_context_param param;
};
 
struct drm_i915_gem_context_destroy {
    __u32 ctx_id;
    __u32 pad;
};
 
struct drm_i915_gem_vm_control {
    __u64 extensions;
 
    __u32 flags;
 
    __u32 vm_id;
};
 
struct drm_i915_reg_read {
    /*
     * Register offset.
     * For 64bit wide registers where the upper 32bits don't immediately
     * follow the lower 32bits, the offset of the lower 32bits must
     * be specified
     */
    __u64 offset;
#define I915_REG_READ_8B_WA (1ul << 0)
 
    __u64 val; /* Return value */
};
 
/* Known registers:
 *
 * Render engine timestamp - 0x2358 + 64bit - gen7+
 * - Note this register returns an invalid value if using the default
 *   single instruction 8byte read, in order to workaround that pass
 *   flag I915_REG_READ_8B_WA in offset field.
 *
 */
 
/*
 * struct drm_i915_reset_stats - Return global reset and other context stats
 *
 * Driver keeps few stats for each contexts and also global reset count.
 * This struct can be used to query those stats.
 */
struct drm_i915_reset_stats {
    __u32 ctx_id;
 
    __u32 flags;
 
    __u32 reset_count;
 
    __u32 batch_active;
 
    __u32 batch_pending;
 
    __u32 pad;
};
 
struct drm_i915_gem_userptr {
    __u64 user_ptr;
 
    __u64 user_size;
 
    __u32 flags;
#define I915_USERPTR_READ_ONLY 0x1
#define I915_USERPTR_PROBE 0x2
#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
    __u32 handle;
};
 
enum drm_i915_oa_format {
    I915_OA_FORMAT_A13 = 1,     /* HSW only */
    I915_OA_FORMAT_A29,     /* HSW only */
    I915_OA_FORMAT_A13_B8_C8,   /* HSW only */
    I915_OA_FORMAT_B4_C8,       /* HSW only */
    I915_OA_FORMAT_A45_B8_C8,   /* HSW only */
    I915_OA_FORMAT_B4_C8_A16,   /* HSW only */
    I915_OA_FORMAT_C4_B8,       /* HSW+ */
 
    /* Gen8+ */
    I915_OA_FORMAT_A12,
    I915_OA_FORMAT_A12_B8_C8,
    I915_OA_FORMAT_A32u40_A4u32_B8_C8,
 
    /* DG2 */
    I915_OAR_FORMAT_A32u40_A4u32_B8_C8,
    I915_OA_FORMAT_A24u40_A14u32_B8_C8,
 
    /* MTL OAM */
    I915_OAM_FORMAT_MPEC8u64_B8_C8,
    I915_OAM_FORMAT_MPEC8u32_B8_C8,
 
    I915_OA_FORMAT_MAX      /* non-ABI */
};
 
enum drm_i915_perf_property_id {
    DRM_I915_PERF_PROP_CTX_HANDLE = 1,
 
    DRM_I915_PERF_PROP_SAMPLE_OA,
 
    DRM_I915_PERF_PROP_OA_METRICS_SET,
 
    DRM_I915_PERF_PROP_OA_FORMAT,
 
    DRM_I915_PERF_PROP_OA_EXPONENT,
 
    DRM_I915_PERF_PROP_HOLD_PREEMPTION,
 
    DRM_I915_PERF_PROP_GLOBAL_SSEU,
 
    DRM_I915_PERF_PROP_POLL_OA_PERIOD,
 
    DRM_I915_PERF_PROP_OA_ENGINE_CLASS,
 
    DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE,
 
    DRM_I915_PERF_PROP_MAX /* non-ABI */
};
 
struct drm_i915_perf_open_param {
    __u32 flags;
#define I915_PERF_FLAG_FD_CLOEXEC   (1<<0)
#define I915_PERF_FLAG_FD_NONBLOCK  (1<<1)
#define I915_PERF_FLAG_DISABLED     (1<<2)
 
    __u32 num_properties;
 
    __u64 properties_ptr;
};
 
/*
 * Enable data capture for a stream that was either opened in a disabled state
 * via I915_PERF_FLAG_DISABLED or was later disabled via
 * I915_PERF_IOCTL_DISABLE.
 *
 * It is intended to be cheaper to disable and enable a stream than it may be
 * to close and re-open a stream with the same configuration.
 *
 * It's undefined whether any pending data for the stream will be lost.
 *
 * This ioctl is available in perf revision 1.
 */
#define I915_PERF_IOCTL_ENABLE  _IO('i', 0x0)
 
/*
 * Disable data capture for a stream.
 *
 * It is an error to try and read a stream that is disabled.
 *
 * This ioctl is available in perf revision 1.
 */
#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
 
/*
 * Change metrics_set captured by a stream.
 *
 * If the stream is bound to a specific context, the configuration change
 * will performed inline with that context such that it takes effect before
 * the next execbuf submission.
 *
 * Returns the previously bound metrics set id, or a negative error code.
 *
 * This ioctl is available in perf revision 2.
 */
#define I915_PERF_IOCTL_CONFIG  _IO('i', 0x2)
 
/*
 * Common to all i915 perf records
 */
struct drm_i915_perf_record_header {
    __u32 type;
    __u16 pad;
    __u16 size;
};
 
enum drm_i915_perf_record_type {
 
    DRM_I915_PERF_RECORD_SAMPLE = 1,
 
    /*
     * Indicates that one or more OA reports were not written by the
     * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
     * command collides with periodic sampling - which would be more likely
     * at higher sampling frequencies.
     */
    DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
 
    DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
 
    DRM_I915_PERF_RECORD_MAX /* non-ABI */
};
 
struct drm_i915_perf_oa_config {
    char uuid[36];
 
    __u32 n_mux_regs;
 
    __u32 n_boolean_regs;
 
    __u32 n_flex_regs;
 
    __u64 mux_regs_ptr;
 
    __u64 boolean_regs_ptr;
 
    __u64 flex_regs_ptr;
};
 
struct drm_i915_query_item {
    __u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO        1
#define DRM_I915_QUERY_ENGINE_INFO      2
#define DRM_I915_QUERY_PERF_CONFIG      3
#define DRM_I915_QUERY_MEMORY_REGIONS       4
#define DRM_I915_QUERY_HWCONFIG_BLOB        5
#define DRM_I915_QUERY_GEOMETRY_SUBSLICES   6
#define DRM_I915_QUERY_GUC_SUBMISSION_VERSION   7
/* Must be kept compact -- no holes and well documented */
 
    __s32 length;
 
    __u32 flags;
#define DRM_I915_QUERY_PERF_CONFIG_LIST          1
#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID   3
 
    __u64 data_ptr;
};
 
struct drm_i915_query {
    __u32 num_items;
 
    __u32 flags;
 
    __u64 items_ptr;
};
 
struct drm_i915_query_topology_info {
    __u16 flags;
 
    __u16 max_slices;
 
    __u16 max_subslices;
 
    __u16 max_eus_per_subslice;
 
    __u16 subslice_offset;
 
    __u16 subslice_stride;
 
    __u16 eu_offset;
 
    __u16 eu_stride;
 
    __u8 data[];
};
 
struct drm_i915_engine_info {
    struct i915_engine_class_instance engine;
 
    __u32 rsvd0;
 
    __u64 flags;
#define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE       (1 << 0)
 
    __u64 capabilities;
#define I915_VIDEO_CLASS_CAPABILITY_HEVC        (1 << 0)
#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
 
    __u16 logical_instance;
 
    __u16 rsvd1[3];
    __u64 rsvd2[3];
};
 
struct drm_i915_query_engine_info {
    __u32 num_engines;
 
    __u32 rsvd[3];
 
    struct drm_i915_engine_info engines[];
};
 
struct drm_i915_query_perf_config {
    union {
        __u64 n_configs;
 
        __u64 config;
 
        char uuid[36];
    };
 
    __u32 flags;
 
    __u8 data[];
};
 
enum drm_i915_gem_memory_class {
    I915_MEMORY_CLASS_SYSTEM = 0,
    I915_MEMORY_CLASS_DEVICE,
};
 
struct drm_i915_gem_memory_class_instance {
    __u16 memory_class;
 
    __u16 memory_instance;
};
 
struct drm_i915_memory_region_info {
    struct drm_i915_gem_memory_class_instance region;
 
    __u32 rsvd0;
 
    __u64 probed_size;
 
    __u64 unallocated_size;
 
    union {
        __u64 rsvd1[8];
        struct {
            __u64 probed_cpu_visible_size;
 
            __u64 unallocated_cpu_visible_size;
        };
    };
};
 
struct drm_i915_query_memory_regions {
    __u32 num_regions;
 
    __u32 rsvd[3];
 
    struct drm_i915_memory_region_info regions[];
};
 
struct drm_i915_query_guc_submission_version {
    __u32 branch;
    __u32 major;
    __u32 minor;
    __u32 patch;
};
 
struct drm_i915_gem_create_ext {
    __u64 size;
 
    __u32 handle;
 
#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0)
    __u32 flags;
 
#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
#define I915_GEM_CREATE_EXT_SET_PAT 2
    __u64 extensions;
};
 
struct drm_i915_gem_create_ext_memory_regions {
    struct i915_user_extension base;
 
    __u32 pad;
    __u32 num_regions;
    __u64 regions;
};
 
struct drm_i915_gem_create_ext_protected_content {
    struct i915_user_extension base;
    __u32 flags;
};
 
struct drm_i915_gem_create_ext_set_pat {
    struct i915_user_extension base;
    __u32 pat_index;
    __u32 rsvd;
};
 
/* ID of the protected content session managed by i915 when PXP is active */
#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
 
#if defined(__cplusplus)
}
#endif
 
#endif /* _UAPI_I915_DRM_H_ */