#include "drm.h"

Include dependency graph for i915_drm.h:

Classes
struct	i915_user_extension

struct	i915_engine_class_instance

struct	_drm_i915_init

struct	_drm_i915_sarea

struct	drm_i915_batchbuffer

struct	_drm_i915_cmdbuffer

struct	drm_i915_irq_emit

struct	drm_i915_irq_wait

struct	drm_i915_getparam

struct	drm_i915_setparam

struct	drm_i915_mem_alloc

struct	drm_i915_mem_free

struct	drm_i915_mem_init_heap

struct	drm_i915_mem_destroy_heap

struct	drm_i915_vblank_pipe

struct	drm_i915_vblank_swap

struct	drm_i915_hws_addr

struct	drm_i915_gem_init

struct	drm_i915_gem_create

struct	drm_i915_gem_pread

struct	drm_i915_gem_pwrite

struct	drm_i915_gem_mmap

struct	drm_i915_gem_mmap_gtt

struct	drm_i915_gem_mmap_offset

struct	drm_i915_gem_set_domain

struct	drm_i915_gem_sw_finish

struct	drm_i915_gem_relocation_entry

struct	drm_i915_gem_exec_object

struct	drm_i915_gem_execbuffer

struct	drm_i915_gem_exec_object2

struct	drm_i915_gem_exec_fence

struct	drm_i915_gem_execbuffer_ext_timeline_fences

struct	drm_i915_gem_execbuffer2

struct	drm_i915_gem_pin

struct	drm_i915_gem_unpin

struct	drm_i915_gem_busy

struct	drm_i915_gem_caching

struct	drm_i915_gem_set_tiling

struct	drm_i915_gem_get_tiling

struct	drm_i915_gem_get_aperture

struct	drm_i915_get_pipe_from_crtc_id

struct	drm_i915_gem_madvise

struct	drm_intel_overlay_put_image

struct	drm_intel_overlay_attrs

struct	drm_intel_sprite_colorkey

struct	drm_i915_gem_wait

struct	drm_i915_gem_context_create

struct	drm_i915_gem_context_create_ext

struct	drm_i915_gem_context_param

struct	drm_i915_gem_context_param_sseu

struct	i915_context_engines_load_balance

struct	i915_context_engines_bond

struct	i915_context_engines_parallel_submit

struct	i915_context_param_engines

struct	i915_gem_context_param_context_image

struct	drm_i915_gem_context_create_ext_setparam

struct	drm_i915_gem_context_destroy

struct	drm_i915_gem_vm_control

struct	drm_i915_reg_read

struct	drm_i915_reset_stats

struct	drm_i915_gem_userptr

struct	drm_i915_perf_open_param

struct	drm_i915_perf_record_header

struct	drm_i915_perf_oa_config

struct	drm_i915_query_item

struct	drm_i915_query

struct	drm_i915_query_topology_info

struct	drm_i915_engine_info

struct	drm_i915_query_engine_info

struct	drm_i915_query_perf_config

struct	drm_i915_gem_memory_class_instance

struct	drm_i915_memory_region_info

struct	drm_i915_query_memory_regions

struct	drm_i915_query_guc_submission_version

struct	drm_i915_gem_create_ext

struct	drm_i915_gem_create_ext_memory_regions

struct	drm_i915_gem_create_ext_protected_content

struct	drm_i915_gem_create_ext_set_pat

Macros
#define	I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"

#define	I915_ERROR_UEVENT "ERROR"

#define	I915_RESET_UEVENT "RESET"

#define	I915_ENGINE_CLASS_INVALID_NONE -1

#define	I915_ENGINE_CLASS_INVALID_VIRTUAL -2

#define	I915_PMU_SAMPLE_BITS (4)

#define	I915_PMU_SAMPLE_MASK (0xf)

#define	I915_PMU_SAMPLE_INSTANCE_BITS (8)

#define	I915_PMU_CLASS_SHIFT (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)

#define	__I915_PMU_ENGINE(class, instance, sample)

#define	I915_PMU_ENGINE_BUSY(class, instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)

#define	I915_PMU_ENGINE_WAIT(class, instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)

#define	I915_PMU_ENGINE_SEMA(class, instance) __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)

#define	__I915_PMU_GT_SHIFT (60)

#define	___I915_PMU_OTHER(gt, x)

#define	__I915_PMU_OTHER(x) ___I915_PMU_OTHER(0, x)

#define	I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)

#define	I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)

#define	I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)

#define	I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)

#define	I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4)

#define	I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY

#define	__I915_PMU_ACTUAL_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 0)

#define	__I915_PMU_REQUESTED_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 1)

#define	__I915_PMU_INTERRUPTS(gt) ___I915_PMU_OTHER(gt, 2)

#define	__I915_PMU_RC6_RESIDENCY(gt) ___I915_PMU_OTHER(gt, 3)

#define	__I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt) ___I915_PMU_OTHER(gt, 4)

#define	I915_NR_TEX_REGIONS

#define	I915_LOG_MIN_TEX_REGION_SIZE 14

#define	planeA_x pipeA_x

#define	planeA_y pipeA_y

#define	planeA_w pipeA_w

#define	planeA_h pipeA_h

#define	planeB_x pipeB_x

#define	planeB_y pipeB_y

#define	planeB_w pipeB_w

#define	planeB_h pipeB_h

#define	I915_BOX_RING_EMPTY 0x1

#define	I915_BOX_FLIP 0x2

#define	I915_BOX_WAIT 0x4

#define	I915_BOX_TEXTURE_LOAD 0x8

#define	I915_BOX_LOST_CONTEXT 0x10

#define	DRM_I915_INIT 0x00

#define	DRM_I915_FLUSH 0x01

#define	DRM_I915_FLIP 0x02

#define	DRM_I915_BATCHBUFFER 0x03

#define	DRM_I915_IRQ_EMIT 0x04

#define	DRM_I915_IRQ_WAIT 0x05

#define	DRM_I915_GETPARAM 0x06

#define	DRM_I915_SETPARAM 0x07

#define	DRM_I915_ALLOC 0x08

#define	DRM_I915_FREE 0x09

#define	DRM_I915_INIT_HEAP 0x0a

#define	DRM_I915_CMDBUFFER 0x0b

#define	DRM_I915_DESTROY_HEAP 0x0c

#define	DRM_I915_SET_VBLANK_PIPE 0x0d

#define	DRM_I915_GET_VBLANK_PIPE 0x0e

#define	DRM_I915_VBLANK_SWAP 0x0f

#define	DRM_I915_HWS_ADDR 0x11

#define	DRM_I915_GEM_INIT 0x13

#define	DRM_I915_GEM_EXECBUFFER 0x14

#define	DRM_I915_GEM_PIN 0x15

#define	DRM_I915_GEM_UNPIN 0x16

#define	DRM_I915_GEM_BUSY 0x17

#define	DRM_I915_GEM_THROTTLE 0x18

#define	DRM_I915_GEM_ENTERVT 0x19

#define	DRM_I915_GEM_LEAVEVT 0x1a

#define	DRM_I915_GEM_CREATE 0x1b

#define	DRM_I915_GEM_PREAD 0x1c

#define	DRM_I915_GEM_PWRITE 0x1d

#define	DRM_I915_GEM_MMAP 0x1e

#define	DRM_I915_GEM_SET_DOMAIN 0x1f

#define	DRM_I915_GEM_SW_FINISH 0x20

#define	DRM_I915_GEM_SET_TILING 0x21

#define	DRM_I915_GEM_GET_TILING 0x22

#define	DRM_I915_GEM_GET_APERTURE 0x23

#define	DRM_I915_GEM_MMAP_GTT 0x24

#define	DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25

#define	DRM_I915_GEM_MADVISE 0x26

#define	DRM_I915_OVERLAY_PUT_IMAGE 0x27

#define	DRM_I915_OVERLAY_ATTRS 0x28

#define	DRM_I915_GEM_EXECBUFFER2 0x29

#define	DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2

#define	DRM_I915_GET_SPRITE_COLORKEY 0x2a

#define	DRM_I915_SET_SPRITE_COLORKEY 0x2b

#define	DRM_I915_GEM_WAIT 0x2c

#define	DRM_I915_GEM_CONTEXT_CREATE 0x2d

#define	DRM_I915_GEM_CONTEXT_DESTROY 0x2e

#define	DRM_I915_GEM_SET_CACHING 0x2f

#define	DRM_I915_GEM_GET_CACHING 0x30

#define	DRM_I915_REG_READ 0x31

#define	DRM_I915_GET_RESET_STATS 0x32

#define	DRM_I915_GEM_USERPTR 0x33

#define	DRM_I915_GEM_CONTEXT_GETPARAM 0x34

#define	DRM_I915_GEM_CONTEXT_SETPARAM 0x35

#define	DRM_I915_PERF_OPEN 0x36

#define	DRM_I915_PERF_ADD_CONFIG 0x37

#define	DRM_I915_PERF_REMOVE_CONFIG 0x38

#define	DRM_I915_QUERY 0x39

#define	DRM_I915_GEM_VM_CREATE 0x3a

#define	DRM_I915_GEM_VM_DESTROY 0x3b

#define	DRM_I915_GEM_CREATE_EXT 0x3c

#define	DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)

#define	DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)

#define	DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)

#define	DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)

#define	DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)

#define	DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)

#define	DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)

#define	DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)

#define	DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)

#define	DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)

#define	DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)

#define	DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)

#define	DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)

#define	DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)

#define	DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)

#define	DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)

#define	DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)

#define	DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)

#define	DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)

#define	DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)

#define	DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)

#define	DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)

#define	DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)

#define	DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)

#define	DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)

#define	DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)

#define	DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)

#define	DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)

#define	DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)

#define	DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)

#define	DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext)

#define	DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)

#define	DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)

#define	DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)

#define	DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)

#define	DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset)

#define	DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)

#define	DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)

#define	DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)

#define	DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)

#define	DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)

#define	DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)

#define	DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)

#define	DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)

#define	DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)

#define	DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)

#define	DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)

#define	DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)

#define	DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)

#define	DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)

#define	DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)

#define	DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)

#define	DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)

#define	DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)

#define	DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)

#define	DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)

#define	DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)

#define	DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)

#define	DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)

#define	DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)

#define	DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)

#define	DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)

#define	I915_GEM_PPGTT_NONE 0

#define	I915_GEM_PPGTT_ALIASING 1

#define	I915_GEM_PPGTT_FULL 2

#define	I915_PARAM_IRQ_ACTIVE 1

#define	I915_PARAM_ALLOW_BATCHBUFFER 2

#define	I915_PARAM_LAST_DISPATCH 3

#define	I915_PARAM_CHIPSET_ID 4

#define	I915_PARAM_HAS_GEM 5

#define	I915_PARAM_NUM_FENCES_AVAIL 6

#define	I915_PARAM_HAS_OVERLAY 7

#define	I915_PARAM_HAS_PAGEFLIPPING 8

#define	I915_PARAM_HAS_EXECBUF2 9

#define	I915_PARAM_HAS_BSD 10

#define	I915_PARAM_HAS_BLT 11

#define	I915_PARAM_HAS_RELAXED_FENCING 12

#define	I915_PARAM_HAS_COHERENT_RINGS 13

#define	I915_PARAM_HAS_EXEC_CONSTANTS 14

#define	I915_PARAM_HAS_RELAXED_DELTA 15

#define	I915_PARAM_HAS_GEN7_SOL_RESET 16

#define	I915_PARAM_HAS_LLC 17

#define	I915_PARAM_HAS_ALIASING_PPGTT 18

#define	I915_PARAM_HAS_WAIT_TIMEOUT 19

#define	I915_PARAM_HAS_SEMAPHORES 20

#define	I915_PARAM_HAS_PRIME_VMAP_FLUSH 21

#define	I915_PARAM_HAS_VEBOX 22

#define	I915_PARAM_HAS_SECURE_BATCHES 23

#define	I915_PARAM_HAS_PINNED_BATCHES 24

#define	I915_PARAM_HAS_EXEC_NO_RELOC 25

#define	I915_PARAM_HAS_EXEC_HANDLE_LUT 26

#define	I915_PARAM_HAS_WT 27

#define	I915_PARAM_CMD_PARSER_VERSION 28

#define	I915_PARAM_HAS_COHERENT_PHYS_GTT 29

#define	I915_PARAM_MMAP_VERSION 30

#define	I915_PARAM_HAS_BSD2 31

#define	I915_PARAM_REVISION 32

#define	I915_PARAM_SUBSLICE_TOTAL 33

#define	I915_PARAM_EU_TOTAL 34

#define	I915_PARAM_HAS_GPU_RESET 35

#define	I915_PARAM_HAS_RESOURCE_STREAMER 36

#define	I915_PARAM_HAS_EXEC_SOFTPIN 37

#define	I915_PARAM_HAS_POOLED_EU 38

#define	I915_PARAM_MIN_EU_IN_POOL 39

#define	I915_PARAM_MMAP_GTT_VERSION 40

#define	I915_PARAM_HAS_SCHEDULER 41

#define	I915_SCHEDULER_CAP_ENABLED (1ul << 0)

#define	I915_SCHEDULER_CAP_PRIORITY (1ul << 1)

#define	I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)

#define	I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)

#define	I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)

#define	I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)

#define	I915_PARAM_HUC_STATUS 42

#define	I915_PARAM_HAS_EXEC_ASYNC 43

#define	I915_PARAM_HAS_EXEC_FENCE 44

#define	I915_PARAM_HAS_EXEC_CAPTURE 45

#define	I915_PARAM_SLICE_MASK 46

#define	I915_PARAM_SUBSLICE_MASK 47

#define	I915_PARAM_HAS_EXEC_BATCH_FIRST 48

#define	I915_PARAM_HAS_EXEC_FENCE_ARRAY 49

#define	I915_PARAM_HAS_CONTEXT_ISOLATION 50

#define	I915_PARAM_CS_TIMESTAMP_FREQUENCY 51

#define	I915_PARAM_MMAP_GTT_COHERENT 52

#define	I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53

#define	I915_PARAM_PERF_REVISION 54

#define	I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55

#define	I915_PARAM_HAS_USERPTR_PROBE 56

#define	I915_PARAM_OA_TIMESTAMP_FREQUENCY 57

#define	I915_PARAM_PXP_STATUS 58

#define	I915_PARAM_HAS_CONTEXT_FREQ_HINT 59

#define	I915_SETPARAM_USE_MI_BATCHBUFFER_START 1

#define	I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2

#define	I915_SETPARAM_ALLOW_BATCHBUFFER 3

#define	I915_SETPARAM_NUM_USED_FENCES 4

#define	I915_MEM_REGION_AGP 1

#define	DRM_I915_VBLANK_PIPE_A 1

#define	DRM_I915_VBLANK_PIPE_B 2

#define	I915_MMAP_WC 0x1

#define	I915_MMAP_OFFSET_GTT 0

#define	I915_MMAP_OFFSET_WC 1

#define	I915_MMAP_OFFSET_WB 2

#define	I915_MMAP_OFFSET_UC 3

#define	I915_MMAP_OFFSET_FIXED 4

#define	EXEC_OBJECT_NEEDS_FENCE (1<<0)

#define	EXEC_OBJECT_NEEDS_GTT (1<<1)

#define	EXEC_OBJECT_WRITE (1<<2)

#define	EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)

#define	EXEC_OBJECT_PINNED (1<<4)

#define	EXEC_OBJECT_PAD_TO_SIZE (1<<5)

#define	EXEC_OBJECT_ASYNC (1<<6)

#define	EXEC_OBJECT_CAPTURE (1<<7)

#define	__EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)

#define	I915_EXEC_FENCE_WAIT (1<<0)

#define	I915_EXEC_FENCE_SIGNAL (1<<1)

#define	__I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))

#define	DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0

#define	I915_EXEC_RING_MASK (0x3f)

#define	I915_EXEC_DEFAULT (0<<0)

#define	I915_EXEC_RENDER (1<<0)

#define	I915_EXEC_BSD (2<<0)

#define	I915_EXEC_BLT (3<<0)

#define	I915_EXEC_VEBOX (4<<0)

#define	I915_EXEC_CONSTANTS_MASK (3<<6)

#define	I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */

#define	I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)

#define	I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */

#define	I915_EXEC_GEN7_SOL_RESET (1<<8)

#define	I915_EXEC_SECURE (1<<9)

#define	I915_EXEC_IS_PINNED (1<<10)

#define	I915_EXEC_NO_RELOC (1<<11)

#define	I915_EXEC_HANDLE_LUT (1<<12)

#define	I915_EXEC_BSD_SHIFT (13)

#define	I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)

#define	I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)

#define	I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)

#define	I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)

#define	I915_EXEC_RESOURCE_STREAMER (1<<15)

#define	I915_EXEC_FENCE_IN (1<<16)

#define	I915_EXEC_FENCE_OUT (1<<17)

#define	I915_EXEC_BATCH_FIRST (1<<18)

#define	I915_EXEC_FENCE_ARRAY (1<<19)

#define	I915_EXEC_FENCE_SUBMIT (1 << 20)

#define	I915_EXEC_USE_EXTENSIONS (1 << 21)

#define	__I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1))

#define	I915_EXEC_CONTEXT_ID_MASK (0xffffffff)

#define	i915_execbuffer2_set_context_id(eb2, context) (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK

#define	i915_execbuffer2_get_context_id(eb2) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)

#define	I915_CACHING_NONE 0

#define	I915_CACHING_CACHED 1

#define	I915_CACHING_DISPLAY 2

#define	I915_TILING_NONE 0

#define	I915_TILING_X 1

#define	I915_TILING_Y 2

#define	I915_TILING_LAST I915_TILING_Y

#define	I915_BIT_6_SWIZZLE_NONE 0

#define	I915_BIT_6_SWIZZLE_9 1

#define	I915_BIT_6_SWIZZLE_9_10 2

#define	I915_BIT_6_SWIZZLE_9_11 3

#define	I915_BIT_6_SWIZZLE_9_10_11 4

#define	I915_BIT_6_SWIZZLE_UNKNOWN 5

#define	I915_BIT_6_SWIZZLE_9_17 6

#define	I915_BIT_6_SWIZZLE_9_10_17 7

#define	I915_MADV_WILLNEED 0

#define	I915_MADV_DONTNEED 1

#define	__I915_MADV_PURGED 2 /* internal state */

#define	I915_OVERLAY_TYPE_MASK 0xff

#define	I915_OVERLAY_YUV_PLANAR 0x01

#define	I915_OVERLAY_YUV_PACKED 0x02

#define	I915_OVERLAY_RGB 0x03

#define	I915_OVERLAY_DEPTH_MASK 0xff00

#define	I915_OVERLAY_RGB24 0x1000

#define	I915_OVERLAY_RGB16 0x2000

#define	I915_OVERLAY_RGB15 0x3000

#define	I915_OVERLAY_YUV422 0x0100

#define	I915_OVERLAY_YUV411 0x0200

#define	I915_OVERLAY_YUV420 0x0300

#define	I915_OVERLAY_YUV410 0x0400

#define	I915_OVERLAY_SWAP_MASK 0xff0000

#define	I915_OVERLAY_NO_SWAP 0x000000

#define	I915_OVERLAY_UV_SWAP 0x010000

#define	I915_OVERLAY_Y_SWAP 0x020000

#define	I915_OVERLAY_Y_AND_UV_SWAP 0x030000

#define	I915_OVERLAY_FLAGS_MASK 0xff000000

#define	I915_OVERLAY_ENABLE 0x01000000

#define	I915_OVERLAY_UPDATE_ATTRS (1<<0)

#define	I915_OVERLAY_UPDATE_GAMMA (1<<1)

#define	I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)

#define	I915_SET_COLORKEY_NONE

#define	I915_SET_COLORKEY_DESTINATION (1<<1)

#define	I915_SET_COLORKEY_SOURCE (1<<2)

#define	I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)

#define	I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)

#define	I915_CONTEXT_CREATE_FLAGS_UNKNOWN (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))

#define	I915_CONTEXT_CREATE_EXT_SETPARAM 0

#define	I915_CONTEXT_CREATE_EXT_CLONE 1

#define	I915_CONTEXT_PARAM_BAN_PERIOD 0x1

#define	I915_CONTEXT_PARAM_NO_ZEROMAP 0x2

#define	I915_CONTEXT_PARAM_GTT_SIZE 0x3

#define	I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4

#define	I915_CONTEXT_PARAM_BANNABLE 0x5

#define	I915_CONTEXT_PARAM_PRIORITY 0x6

#define	I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */

#define	I915_CONTEXT_DEFAULT_PRIORITY 0

#define	I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */

#define	I915_CONTEXT_PARAM_SSEU 0x7

#define	I915_CONTEXT_PARAM_RECOVERABLE 0x8

#define	I915_CONTEXT_PARAM_VM 0x9

#define	I915_CONTEXT_PARAM_ENGINES 0xa

#define	I915_CONTEXT_PARAM_PERSISTENCE 0xb

#define	I915_CONTEXT_PARAM_RINGSIZE 0xc

#define	I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd

#define	I915_CONTEXT_PARAM_LOW_LATENCY 0xe

#define	I915_CONTEXT_PARAM_CONTEXT_IMAGE 0xf

#define	I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)

#define	I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__)

#define	I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__)

#define	I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__, N__)

#define	I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */

#define	I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */

#define	I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */

#define	I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__)

#define	I915_CONTEXT_IMAGE_FLAG_ENGINE_INDEX (1u << 0)

#define	I915_REG_READ_8B_WA (1ul << 0)

#define	I915_USERPTR_READ_ONLY 0x1

#define	I915_USERPTR_PROBE 0x2

#define	I915_USERPTR_UNSYNCHRONIZED 0x80000000

#define	I915_PERF_FLAG_FD_CLOEXEC (1<<0)

#define	I915_PERF_FLAG_FD_NONBLOCK (1<<1)

#define	I915_PERF_FLAG_DISABLED (1<<2)

#define	I915_PERF_IOCTL_ENABLE _IO('i', 0x0)

#define	I915_PERF_IOCTL_DISABLE _IO('i', 0x1)

#define	I915_PERF_IOCTL_CONFIG _IO('i', 0x2)

#define	DRM_I915_QUERY_TOPOLOGY_INFO 1

#define	DRM_I915_QUERY_ENGINE_INFO 2

#define	DRM_I915_QUERY_PERF_CONFIG 3

#define	DRM_I915_QUERY_MEMORY_REGIONS 4

#define	DRM_I915_QUERY_HWCONFIG_BLOB 5

#define	DRM_I915_QUERY_GEOMETRY_SUBSLICES 6

#define	DRM_I915_QUERY_GUC_SUBMISSION_VERSION 7

#define	DRM_I915_QUERY_PERF_CONFIG_LIST 1

#define	DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2

#define	DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3

#define	I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0)

#define	I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)

#define	I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)

#define	I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0)

#define	I915_GEM_CREATE_EXT_MEMORY_REGIONS 0

#define	I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1

#define	I915_GEM_CREATE_EXT_SET_PAT 2

#define	I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf


#define	I915_GEM_DOMAIN_CPU 0x00000001

#define	I915_GEM_DOMAIN_RENDER 0x00000002

#define	I915_GEM_DOMAIN_SAMPLER 0x00000004

#define	I915_GEM_DOMAIN_COMMAND 0x00000008

#define	I915_GEM_DOMAIN_INSTRUCTION 0x00000010

#define	I915_GEM_DOMAIN_VERTEX 0x00000020

#define	I915_GEM_DOMAIN_GTT 0x00000040

#define	I915_GEM_DOMAIN_WC 0x00000080

Typedefs
typedef struct _drm_i915_init	drm_i915_init_t

typedef struct _drm_i915_sarea	drm_i915_sarea_t

typedef struct drm_i915_batchbuffer	drm_i915_batchbuffer_t

typedef struct _drm_i915_cmdbuffer	drm_i915_cmdbuffer_t

typedef struct drm_i915_irq_emit	drm_i915_irq_emit_t

typedef struct drm_i915_irq_wait	drm_i915_irq_wait_t

typedef struct drm_i915_getparam	drm_i915_getparam_t

typedef struct drm_i915_setparam	drm_i915_setparam_t

typedef struct drm_i915_mem_alloc	drm_i915_mem_alloc_t

typedef struct drm_i915_mem_free	drm_i915_mem_free_t

typedef struct drm_i915_mem_init_heap	drm_i915_mem_init_heap_t

typedef struct drm_i915_mem_destroy_heap	drm_i915_mem_destroy_heap_t

typedef struct drm_i915_vblank_pipe	drm_i915_vblank_pipe_t

typedef struct drm_i915_vblank_swap	drm_i915_vblank_swap_t

typedef struct drm_i915_hws_addr	drm_i915_hws_addr_t

Enumerations
enum	i915_mocs_table_index { I915_MOCS_UNCACHED , I915_MOCS_PTE , I915_MOCS_CACHED }

enum	drm_i915_gem_engine_class { I915_ENGINE_CLASS_RENDER = 0 , I915_ENGINE_CLASS_COPY = 1 , I915_ENGINE_CLASS_VIDEO = 2 , I915_ENGINE_CLASS_VIDEO_ENHANCE = 3 , I915_ENGINE_CLASS_COMPUTE = 4 , I915_ENGINE_CLASS_INVALID = -1 }

enum	drm_i915_pmu_engine_sample { I915_SAMPLE_BUSY = 0 , I915_SAMPLE_WAIT = 1 , I915_SAMPLE_SEMA = 2 }

enum	drm_i915_oa_format { I915_OA_FORMAT_A13 = 1 , I915_OA_FORMAT_A29 , I915_OA_FORMAT_A13_B8_C8 , I915_OA_FORMAT_B4_C8 , I915_OA_FORMAT_A45_B8_C8 , I915_OA_FORMAT_B4_C8_A16 , I915_OA_FORMAT_C4_B8 , I915_OA_FORMAT_A12 , I915_OA_FORMAT_A12_B8_C8 , I915_OA_FORMAT_A32u40_A4u32_B8_C8 , I915_OAR_FORMAT_A32u40_A4u32_B8_C8 , I915_OA_FORMAT_A24u40_A14u32_B8_C8 , I915_OAM_FORMAT_MPEC8u64_B8_C8 , I915_OAM_FORMAT_MPEC8u32_B8_C8 , I915_OA_FORMAT_MAX }

enum	drm_i915_perf_property_id { DRM_I915_PERF_PROP_CTX_HANDLE = 1 , DRM_I915_PERF_PROP_SAMPLE_OA , DRM_I915_PERF_PROP_OA_METRICS_SET , DRM_I915_PERF_PROP_OA_FORMAT , DRM_I915_PERF_PROP_OA_EXPONENT , DRM_I915_PERF_PROP_HOLD_PREEMPTION , DRM_I915_PERF_PROP_GLOBAL_SSEU , DRM_I915_PERF_PROP_POLL_OA_PERIOD , DRM_I915_PERF_PROP_OA_ENGINE_CLASS , DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE , DRM_I915_PERF_PROP_MAX }

enum	drm_i915_perf_record_type { DRM_I915_PERF_RECORD_SAMPLE = 1 , DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2 , DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3 , DRM_I915_PERF_RECORD_MAX }

enum	drm_i915_gem_memory_class { I915_MEMORY_CLASS_SYSTEM = 0 , I915_MEMORY_CLASS_DEVICE }

Functions
struct i915_context_engines_load_balance	__attribute__ ((packed))

Variables
struct i915_user_extension	base

__u16	engine_index

__u16	num_siblings

__u32	flags

__u64	mbz64

struct i915_engine_class_instance	engines []

struct i915_engine_class_instance	master

__u16	virtual_index

__u16	num_bonds

struct i915_context_engines_parallel_submit	__packed

__u64	extensions

struct i915_engine_class_instance	engine

__u32	size

__u32	mbz

__u64	image

struct drm_i915_gem_context_create_ext_setparam	__attribute__

Macro Definition Documentation

◆ ___I915_PMU_OTHER

#define ___I915_PMU_OTHER	(	gt,
		x
	)

Value:

(((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \

((__u64)(gt) << __I915_PMU_GT_SHIFT))

__u64

uint64_t __u64

Definition drm.h:44

__I915_PMU_GT_SHIFT

#define __I915_PMU_GT_SHIFT

Definition i915_drm.h:286

__I915_PMU_ENGINE

#define __I915_PMU_ENGINE(class, instance, sample)

Definition i915_drm.h:269

x

int x

Definition layout.c:118

◆ __EXEC_OBJECT_UNKNOWN_FLAGS

#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)

◆ __I915_EXEC_FENCE_UNKNOWN_FLAGS

#define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))

◆ __I915_EXEC_UNKNOWN_FLAGS

#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1))

◆ __I915_MADV_PURGED

#define __I915_MADV_PURGED 2 /* internal state */

◆ __I915_PMU_ACTUAL_FREQUENCY

#define __I915_PMU_ACTUAL_FREQUENCY ( gt ) ___I915_PMU_OTHER(gt, 0)

◆ __I915_PMU_ENGINE

#define __I915_PMU_ENGINE	(	class,
		instance,
		sample
	)

Value:

    ((class) << I915_PMU_CLASS_SHIFT | \
    (instance) << I915_PMU_SAMPLE_BITS | \
    (sample))

◆ __I915_PMU_GT_SHIFT

#define __I915_PMU_GT_SHIFT (60)

◆ __I915_PMU_INTERRUPTS

#define __I915_PMU_INTERRUPTS ( gt ) ___I915_PMU_OTHER(gt, 2)

◆ __I915_PMU_OTHER

#define __I915_PMU_OTHER ( x ) ___I915_PMU_OTHER(0, x)

◆ __I915_PMU_RC6_RESIDENCY

#define __I915_PMU_RC6_RESIDENCY ( gt ) ___I915_PMU_OTHER(gt, 3)

◆ __I915_PMU_REQUESTED_FREQUENCY

#define __I915_PMU_REQUESTED_FREQUENCY ( gt ) ___I915_PMU_OTHER(gt, 1)

◆ __I915_PMU_SOFTWARE_GT_AWAKE_TIME

#define __I915_PMU_SOFTWARE_GT_AWAKE_TIME ( gt ) ___I915_PMU_OTHER(gt, 4)

◆ DRM_I915_ALLOC

#define DRM_I915_ALLOC 0x08

◆ DRM_I915_BATCHBUFFER

#define DRM_I915_BATCHBUFFER 0x03

◆ DRM_I915_CMDBUFFER

#define DRM_I915_CMDBUFFER 0x0b

◆ DRM_I915_DESTROY_HEAP

#define DRM_I915_DESTROY_HEAP 0x0c

◆ DRM_I915_FLIP

#define DRM_I915_FLIP 0x02

◆ DRM_I915_FLUSH

#define DRM_I915_FLUSH 0x01

◆ DRM_I915_FREE

#define DRM_I915_FREE 0x09

◆ DRM_I915_GEM_BUSY

#define DRM_I915_GEM_BUSY 0x17

◆ DRM_I915_GEM_CONTEXT_CREATE

#define DRM_I915_GEM_CONTEXT_CREATE 0x2d

◆ DRM_I915_GEM_CONTEXT_DESTROY

#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e

◆ DRM_I915_GEM_CONTEXT_GETPARAM

#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34

◆ DRM_I915_GEM_CONTEXT_SETPARAM

#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35

◆ DRM_I915_GEM_CREATE

#define DRM_I915_GEM_CREATE 0x1b

◆ DRM_I915_GEM_CREATE_EXT

#define DRM_I915_GEM_CREATE_EXT 0x3c

◆ DRM_I915_GEM_ENTERVT

#define DRM_I915_GEM_ENTERVT 0x19

◆ DRM_I915_GEM_EXECBUFFER

#define DRM_I915_GEM_EXECBUFFER 0x14

◆ DRM_I915_GEM_EXECBUFFER2

#define DRM_I915_GEM_EXECBUFFER2 0x29

◆ DRM_I915_GEM_EXECBUFFER2_WR

#define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2

◆ DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES

#define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0

◆ DRM_I915_GEM_GET_APERTURE

#define DRM_I915_GEM_GET_APERTURE 0x23

◆ DRM_I915_GEM_GET_CACHING

#define DRM_I915_GEM_GET_CACHING 0x30

◆ DRM_I915_GEM_GET_TILING

#define DRM_I915_GEM_GET_TILING 0x22

◆ DRM_I915_GEM_INIT

#define DRM_I915_GEM_INIT 0x13

◆ DRM_I915_GEM_LEAVEVT

#define DRM_I915_GEM_LEAVEVT 0x1a

◆ DRM_I915_GEM_MADVISE

#define DRM_I915_GEM_MADVISE 0x26

◆ DRM_I915_GEM_MMAP

#define DRM_I915_GEM_MMAP 0x1e

◆ DRM_I915_GEM_MMAP_GTT

#define DRM_I915_GEM_MMAP_GTT 0x24

◆ DRM_I915_GEM_PIN

#define DRM_I915_GEM_PIN 0x15

◆ DRM_I915_GEM_PREAD

#define DRM_I915_GEM_PREAD 0x1c

◆ DRM_I915_GEM_PWRITE

#define DRM_I915_GEM_PWRITE 0x1d

◆ DRM_I915_GEM_SET_CACHING

#define DRM_I915_GEM_SET_CACHING 0x2f

◆ DRM_I915_GEM_SET_DOMAIN

#define DRM_I915_GEM_SET_DOMAIN 0x1f

◆ DRM_I915_GEM_SET_TILING

#define DRM_I915_GEM_SET_TILING 0x21

◆ DRM_I915_GEM_SW_FINISH

#define DRM_I915_GEM_SW_FINISH 0x20

◆ DRM_I915_GEM_THROTTLE

#define DRM_I915_GEM_THROTTLE 0x18

◆ DRM_I915_GEM_UNPIN

#define DRM_I915_GEM_UNPIN 0x16

◆ DRM_I915_GEM_USERPTR

#define DRM_I915_GEM_USERPTR 0x33

◆ DRM_I915_GEM_VM_CREATE

#define DRM_I915_GEM_VM_CREATE 0x3a

◆ DRM_I915_GEM_VM_DESTROY

#define DRM_I915_GEM_VM_DESTROY 0x3b

◆ DRM_I915_GEM_WAIT

#define DRM_I915_GEM_WAIT 0x2c

◆ DRM_I915_GET_PIPE_FROM_CRTC_ID

#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25

◆ DRM_I915_GET_RESET_STATS

#define DRM_I915_GET_RESET_STATS 0x32

◆ DRM_I915_GET_SPRITE_COLORKEY

#define DRM_I915_GET_SPRITE_COLORKEY 0x2a

◆ DRM_I915_GET_VBLANK_PIPE

#define DRM_I915_GET_VBLANK_PIPE 0x0e

◆ DRM_I915_GETPARAM

#define DRM_I915_GETPARAM 0x06

◆ DRM_I915_HWS_ADDR

#define DRM_I915_HWS_ADDR 0x11

◆ DRM_I915_INIT

#define DRM_I915_INIT 0x00

◆ DRM_I915_INIT_HEAP

#define DRM_I915_INIT_HEAP 0x0a

◆ DRM_I915_IRQ_EMIT

#define DRM_I915_IRQ_EMIT 0x04

◆ DRM_I915_IRQ_WAIT

#define DRM_I915_IRQ_WAIT 0x05

◆ DRM_I915_OVERLAY_ATTRS

#define DRM_I915_OVERLAY_ATTRS 0x28

◆ DRM_I915_OVERLAY_PUT_IMAGE

#define DRM_I915_OVERLAY_PUT_IMAGE 0x27

◆ DRM_I915_PERF_ADD_CONFIG

#define DRM_I915_PERF_ADD_CONFIG 0x37

◆ DRM_I915_PERF_OPEN

#define DRM_I915_PERF_OPEN 0x36

◆ DRM_I915_PERF_REMOVE_CONFIG

#define DRM_I915_PERF_REMOVE_CONFIG 0x38

◆ DRM_I915_QUERY

#define DRM_I915_QUERY 0x39

◆ DRM_I915_QUERY_ENGINE_INFO

#define DRM_I915_QUERY_ENGINE_INFO 2

◆ DRM_I915_QUERY_GEOMETRY_SUBSLICES

#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6

◆ DRM_I915_QUERY_GUC_SUBMISSION_VERSION

#define DRM_I915_QUERY_GUC_SUBMISSION_VERSION 7

◆ DRM_I915_QUERY_HWCONFIG_BLOB

#define DRM_I915_QUERY_HWCONFIG_BLOB 5

◆ DRM_I915_QUERY_MEMORY_REGIONS

#define DRM_I915_QUERY_MEMORY_REGIONS 4

◆ DRM_I915_QUERY_PERF_CONFIG

#define DRM_I915_QUERY_PERF_CONFIG 3

◆ DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID

#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3

◆ DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID

#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2

◆ DRM_I915_QUERY_PERF_CONFIG_LIST

#define DRM_I915_QUERY_PERF_CONFIG_LIST 1

◆ DRM_I915_QUERY_TOPOLOGY_INFO

#define DRM_I915_QUERY_TOPOLOGY_INFO 1

◆ DRM_I915_REG_READ

#define DRM_I915_REG_READ 0x31

◆ DRM_I915_SET_SPRITE_COLORKEY

#define DRM_I915_SET_SPRITE_COLORKEY 0x2b

◆ DRM_I915_SET_VBLANK_PIPE

#define DRM_I915_SET_VBLANK_PIPE 0x0d

◆ DRM_I915_SETPARAM

#define DRM_I915_SETPARAM 0x07

◆ DRM_I915_VBLANK_PIPE_A

#define DRM_I915_VBLANK_PIPE_A 1

◆ DRM_I915_VBLANK_PIPE_B

#define DRM_I915_VBLANK_PIPE_B 2

◆ DRM_I915_VBLANK_SWAP

#define DRM_I915_VBLANK_SWAP 0x0f

◆ DRM_IOCTL_I915_ALLOC

#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)

◆ DRM_IOCTL_I915_BATCHBUFFER

#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)

◆ DRM_IOCTL_I915_CMDBUFFER

#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)

◆ DRM_IOCTL_I915_DESTROY_HEAP

#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)

◆ DRM_IOCTL_I915_FLIP

#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)

◆ DRM_IOCTL_I915_FLUSH

#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)

◆ DRM_IOCTL_I915_FREE

#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)

◆ DRM_IOCTL_I915_GEM_BUSY

#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)

◆ DRM_IOCTL_I915_GEM_CONTEXT_CREATE

#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)

◆ DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT

#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)

◆ DRM_IOCTL_I915_GEM_CONTEXT_DESTROY

#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)

◆ DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM

#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)

◆ DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM

#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)

◆ DRM_IOCTL_I915_GEM_CREATE

#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)

◆ DRM_IOCTL_I915_GEM_CREATE_EXT

#define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext)

◆ DRM_IOCTL_I915_GEM_ENTERVT

#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)

◆ DRM_IOCTL_I915_GEM_EXECBUFFER

#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)

◆ DRM_IOCTL_I915_GEM_EXECBUFFER2

#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)

◆ DRM_IOCTL_I915_GEM_EXECBUFFER2_WR

#define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)

◆ DRM_IOCTL_I915_GEM_GET_APERTURE

#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)

◆ DRM_IOCTL_I915_GEM_GET_CACHING

#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)

◆ DRM_IOCTL_I915_GEM_GET_TILING

#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)

◆ DRM_IOCTL_I915_GEM_INIT

#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)

◆ DRM_IOCTL_I915_GEM_LEAVEVT

#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)

◆ DRM_IOCTL_I915_GEM_MADVISE

#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)

◆ DRM_IOCTL_I915_GEM_MMAP

#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)

◆ DRM_IOCTL_I915_GEM_MMAP_GTT

#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)

◆ DRM_IOCTL_I915_GEM_MMAP_OFFSET

#define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset)

◆ DRM_IOCTL_I915_GEM_PIN

#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)

◆ DRM_IOCTL_I915_GEM_PREAD

#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)

◆ DRM_IOCTL_I915_GEM_PWRITE

#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)

◆ DRM_IOCTL_I915_GEM_SET_CACHING

#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)

◆ DRM_IOCTL_I915_GEM_SET_DOMAIN

#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)

◆ DRM_IOCTL_I915_GEM_SET_TILING

#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)

◆ DRM_IOCTL_I915_GEM_SW_FINISH

#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)

◆ DRM_IOCTL_I915_GEM_THROTTLE

#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)

◆ DRM_IOCTL_I915_GEM_UNPIN

#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)

◆ DRM_IOCTL_I915_GEM_USERPTR

#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)

◆ DRM_IOCTL_I915_GEM_VM_CREATE

#define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)

◆ DRM_IOCTL_I915_GEM_VM_DESTROY

#define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)

◆ DRM_IOCTL_I915_GEM_WAIT

#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)

◆ DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID

#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)

◆ DRM_IOCTL_I915_GET_RESET_STATS

#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)

◆ DRM_IOCTL_I915_GET_SPRITE_COLORKEY

#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)

◆ DRM_IOCTL_I915_GET_VBLANK_PIPE

#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)

◆ DRM_IOCTL_I915_GETPARAM

#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)

◆ DRM_IOCTL_I915_HWS_ADDR

#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)

◆ DRM_IOCTL_I915_INIT

#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)

◆ DRM_IOCTL_I915_INIT_HEAP

#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)

◆ DRM_IOCTL_I915_IRQ_EMIT

#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)

◆ DRM_IOCTL_I915_IRQ_WAIT

#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)

◆ DRM_IOCTL_I915_OVERLAY_ATTRS

#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)

◆ DRM_IOCTL_I915_OVERLAY_PUT_IMAGE

#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)

◆ DRM_IOCTL_I915_PERF_ADD_CONFIG

#define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)

◆ DRM_IOCTL_I915_PERF_OPEN

#define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)

◆ DRM_IOCTL_I915_PERF_REMOVE_CONFIG

#define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)

◆ DRM_IOCTL_I915_QUERY

#define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)

◆ DRM_IOCTL_I915_REG_READ

#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)

◆ DRM_IOCTL_I915_SET_SPRITE_COLORKEY

#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)

◆ DRM_IOCTL_I915_SET_VBLANK_PIPE

#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)

◆ DRM_IOCTL_I915_SETPARAM

#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)

◆ DRM_IOCTL_I915_VBLANK_SWAP

#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)

◆ EXEC_OBJECT_ASYNC

#define EXEC_OBJECT_ASYNC (1<<6)

◆ EXEC_OBJECT_CAPTURE

#define EXEC_OBJECT_CAPTURE (1<<7)

◆ EXEC_OBJECT_NEEDS_FENCE

#define EXEC_OBJECT_NEEDS_FENCE (1<<0)

◆ EXEC_OBJECT_NEEDS_GTT

#define EXEC_OBJECT_NEEDS_GTT (1<<1)

◆ EXEC_OBJECT_PAD_TO_SIZE

#define EXEC_OBJECT_PAD_TO_SIZE (1<<5)

◆ EXEC_OBJECT_PINNED

#define EXEC_OBJECT_PINNED (1<<4)

◆ EXEC_OBJECT_SUPPORTS_48B_ADDRESS

#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)

◆ EXEC_OBJECT_WRITE

#define EXEC_OBJECT_WRITE (1<<2)

◆ I915_BIT_6_SWIZZLE_9

#define I915_BIT_6_SWIZZLE_9 1

◆ I915_BIT_6_SWIZZLE_9_10

#define I915_BIT_6_SWIZZLE_9_10 2

◆ I915_BIT_6_SWIZZLE_9_10_11

#define I915_BIT_6_SWIZZLE_9_10_11 4

◆ I915_BIT_6_SWIZZLE_9_10_17

#define I915_BIT_6_SWIZZLE_9_10_17 7

◆ I915_BIT_6_SWIZZLE_9_11

#define I915_BIT_6_SWIZZLE_9_11 3

◆ I915_BIT_6_SWIZZLE_9_17

#define I915_BIT_6_SWIZZLE_9_17 6

◆ I915_BIT_6_SWIZZLE_NONE

#define I915_BIT_6_SWIZZLE_NONE 0

◆ I915_BIT_6_SWIZZLE_UNKNOWN

#define I915_BIT_6_SWIZZLE_UNKNOWN 5

◆ I915_BOX_FLIP

#define I915_BOX_FLIP 0x2

◆ I915_BOX_LOST_CONTEXT

#define I915_BOX_LOST_CONTEXT 0x10

◆ I915_BOX_RING_EMPTY

#define I915_BOX_RING_EMPTY 0x1

◆ I915_BOX_TEXTURE_LOAD

#define I915_BOX_TEXTURE_LOAD 0x8

◆ I915_BOX_WAIT

#define I915_BOX_WAIT 0x4

◆ I915_CACHING_CACHED

#define I915_CACHING_CACHED 1

◆ I915_CACHING_DISPLAY

#define I915_CACHING_DISPLAY 2

◆ I915_CACHING_NONE

#define I915_CACHING_NONE 0

@caching: The GTT caching level to apply or possible return value.

The supported @caching values:

I915_CACHING_NONE:

GPU access is not coherent with CPU caches. Default for machines without an LLC. This means manual flushing might be needed, if we want GPU access to be coherent.

I915_CACHING_CACHED:

GPU access is coherent with CPU caches and furthermore the data is cached in last-level caches shared between CPU cores and the GPU GT.

I915_CACHING_DISPLAY:

Special GPU caching mode which is coherent with the scanout engines. Transparently falls back to I915_CACHING_NONE on platforms where no special cache mode (like write-through or gfdt flushing) is available. The kernel automatically sets this mode when using a buffer as a scanout target. Userspace can manually set this mode to avoid a costly stall and clflush in the hotpath of drawing the first frame.

◆ I915_CONTEXT_CREATE_EXT_CLONE

#define I915_CONTEXT_CREATE_EXT_CLONE 1

◆ I915_CONTEXT_CREATE_EXT_SETPARAM

#define I915_CONTEXT_CREATE_EXT_SETPARAM 0

◆ I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE

#define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)

◆ I915_CONTEXT_CREATE_FLAGS_UNKNOWN

#define I915_CONTEXT_CREATE_FLAGS_UNKNOWN (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))

◆ I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS

#define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)

◆ I915_CONTEXT_DEFAULT_PRIORITY

#define I915_CONTEXT_DEFAULT_PRIORITY 0

◆ I915_CONTEXT_ENGINES_EXT_BOND

#define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */

◆ I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE

#define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */

◆ I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT

#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */

◆ I915_CONTEXT_IMAGE_FLAG_ENGINE_INDEX

#define I915_CONTEXT_IMAGE_FLAG_ENGINE_INDEX (1u << 0)

◆ I915_CONTEXT_MAX_USER_PRIORITY

#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */

◆ I915_CONTEXT_MIN_USER_PRIORITY

#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */

◆ I915_CONTEXT_PARAM_BAN_PERIOD

#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1

◆ I915_CONTEXT_PARAM_BANNABLE

#define I915_CONTEXT_PARAM_BANNABLE 0x5

◆ I915_CONTEXT_PARAM_CONTEXT_IMAGE

#define I915_CONTEXT_PARAM_CONTEXT_IMAGE 0xf

◆ I915_CONTEXT_PARAM_ENGINES

#define I915_CONTEXT_PARAM_ENGINES 0xa

◆ I915_CONTEXT_PARAM_GTT_SIZE

#define I915_CONTEXT_PARAM_GTT_SIZE 0x3

◆ I915_CONTEXT_PARAM_LOW_LATENCY

#define I915_CONTEXT_PARAM_LOW_LATENCY 0xe

◆ I915_CONTEXT_PARAM_NO_ERROR_CAPTURE

#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4

◆ I915_CONTEXT_PARAM_NO_ZEROMAP

#define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2

◆ I915_CONTEXT_PARAM_PERSISTENCE

#define I915_CONTEXT_PARAM_PERSISTENCE 0xb

◆ I915_CONTEXT_PARAM_PRIORITY

#define I915_CONTEXT_PARAM_PRIORITY 0x6

◆ I915_CONTEXT_PARAM_PROTECTED_CONTENT

#define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd

◆ I915_CONTEXT_PARAM_RECOVERABLE

#define I915_CONTEXT_PARAM_RECOVERABLE 0x8

◆ I915_CONTEXT_PARAM_RINGSIZE

#define I915_CONTEXT_PARAM_RINGSIZE 0xc

◆ I915_CONTEXT_PARAM_SSEU

#define I915_CONTEXT_PARAM_SSEU 0x7

◆ I915_CONTEXT_PARAM_VM

#define I915_CONTEXT_PARAM_VM 0x9

◆ I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX

#define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)

◆ I915_DEFINE_CONTEXT_ENGINES_BOND

#define I915_DEFINE_CONTEXT_ENGINES_BOND	(	name__,
		N__
	)

Value:

    struct { \
    struct i915_user_extension base; \
    struct i915_engine_class_instance master; \
    __u16 virtual_index; \
    __u16 num_bonds; \
    __u64 flags; \
    __u64 mbz64[4]; \
    struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__

◆ I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE

#define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE	(	name__,
		N__
	)

Value:

    struct { \
    struct i915_user_extension base; \
    __u16 engine_index; \
    __u16 num_siblings; \
    __u32 flags; \
    __u64 mbz64; \
    struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__

◆ I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT

#define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT	(	name__,
		N__
	)

Value:

    struct { \
    struct i915_user_extension base; \
    __u16 engine_index; \
    __u16 width; \
    __u16 num_siblings; \
    __u16 mbz16; \
    __u64 flags; \
    __u64 mbz64[3]; \
    struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__

◆ I915_DEFINE_CONTEXT_PARAM_ENGINES

#define I915_DEFINE_CONTEXT_PARAM_ENGINES	(	name__,
		N__
	)

Value:

    struct { \
    __u64 extensions; \
    struct i915_engine_class_instance engines[N__]; \
} __attribute__((packed)) name__

◆ I915_ENGINE_CLASS_INVALID_NONE

#define I915_ENGINE_CLASS_INVALID_NONE -1

◆ I915_ENGINE_CLASS_INVALID_VIRTUAL

#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2

◆ I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE

#define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0)

◆ I915_ERROR_UEVENT

#define I915_ERROR_UEVENT "ERROR"

◆ I915_EXEC_BATCH_FIRST

#define I915_EXEC_BATCH_FIRST (1<<18)

◆ I915_EXEC_BLT

#define I915_EXEC_BLT (3<<0)

◆ I915_EXEC_BSD

#define I915_EXEC_BSD (2<<0)

◆ I915_EXEC_BSD_DEFAULT

#define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)

◆ I915_EXEC_BSD_MASK

#define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)

◆ I915_EXEC_BSD_RING1

#define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)

◆ I915_EXEC_BSD_RING2

#define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)

◆ I915_EXEC_BSD_SHIFT

#define I915_EXEC_BSD_SHIFT (13)

Used for switching BSD rings on the platforms with two BSD rings

◆ I915_EXEC_CONSTANTS_ABSOLUTE

#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)

◆ I915_EXEC_CONSTANTS_MASK

#define I915_EXEC_CONSTANTS_MASK (3<<6)

◆ I915_EXEC_CONSTANTS_REL_GENERAL

#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */

◆ I915_EXEC_CONSTANTS_REL_SURFACE

#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */

◆ I915_EXEC_CONTEXT_ID_MASK

#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)

◆ I915_EXEC_DEFAULT

#define I915_EXEC_DEFAULT (0<<0)

◆ I915_EXEC_FENCE_ARRAY

#define I915_EXEC_FENCE_ARRAY (1<<19)

◆ I915_EXEC_FENCE_IN

#define I915_EXEC_FENCE_IN (1<<16)

◆ I915_EXEC_FENCE_OUT

#define I915_EXEC_FENCE_OUT (1<<17)

◆ I915_EXEC_FENCE_SIGNAL

#define I915_EXEC_FENCE_SIGNAL (1<<1)

◆ I915_EXEC_FENCE_SUBMIT

#define I915_EXEC_FENCE_SUBMIT (1 << 20)

◆ I915_EXEC_FENCE_WAIT

#define I915_EXEC_FENCE_WAIT (1<<0)

◆ I915_EXEC_GEN7_SOL_RESET

#define I915_EXEC_GEN7_SOL_RESET (1<<8)

Resets the SO write offset registers for transform feedback on gen7.

◆ I915_EXEC_HANDLE_LUT

#define I915_EXEC_HANDLE_LUT (1<<12)

Use the reloc.handle as an index into the exec object array rather than as the per-file handle.

◆ I915_EXEC_IS_PINNED

#define I915_EXEC_IS_PINNED (1<<10)

Inform the kernel that the batch is and will always be pinned. This negates the requirement for a workaround to be performed to avoid an incoherent CS (such as can be found on 830/845). If this flag is not passed, the kernel will endeavour to make sure the batch is coherent with the CS before execution. If this flag is passed, userspace assumes the responsibility for ensuring the same.

◆ I915_EXEC_NO_RELOC

#define I915_EXEC_NO_RELOC (1<<11)

Provide a hint to the kernel that the command stream and auxiliary state buffers already holds the correct presumed addresses and so the relocation process may be skipped if no buffers need to be moved in preparation for the execbuffer.

◆ I915_EXEC_RENDER

#define I915_EXEC_RENDER (1<<0)

◆ I915_EXEC_RESOURCE_STREAMER

#define I915_EXEC_RESOURCE_STREAMER (1<<15)

Tell the kernel that the batchbuffer is processed by the resource streamer.

◆ I915_EXEC_RING_MASK

#define I915_EXEC_RING_MASK (0x3f)

◆ I915_EXEC_SECURE

#define I915_EXEC_SECURE (1<<9)

Request a privileged ("secure") batch buffer. Note only available for DRM_ROOT_ONLY | DRM_MASTER processes.

◆ I915_EXEC_USE_EXTENSIONS

#define I915_EXEC_USE_EXTENSIONS (1 << 21)

◆ I915_EXEC_VEBOX

#define I915_EXEC_VEBOX (4<<0)

◆ i915_execbuffer2_get_context_id

#define i915_execbuffer2_get_context_id ( eb2 ) ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)

◆ i915_execbuffer2_set_context_id

#define i915_execbuffer2_set_context_id	(	eb2,
		context
	)	(eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK

◆ I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS

#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0)

@flags: Optional flags.

Supported values:

I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that the object will need to be accessed via the CPU.

Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only strictly required on configurations where some subset of the device memory is directly visible/mappable through the CPU (which we also call small BAR), like on some DG2+ systems. Note that this is quite undesirable, but due to various factors like the client CPU, BIOS etc it's something we can expect to see in the wild. See &drm_i915_memory_region_info.probed_cpu_visible_size for how to determine if this system applies.

Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to ensure the kernel can always spill the allocation to system memory, if the object can't be allocated in the mappable part of I915_MEMORY_CLASS_DEVICE.

Also note that since the kernel only supports flat-CCS on objects that can only be placed in I915_MEMORY_CLASS_DEVICE, we therefore don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with flat-CCS.

Without this hint, the kernel will assume that non-mappable I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the kernel can still migrate the object to the mappable part, as a last resort, if userspace ever CPU faults this object, but this might be expensive, and so ideally should be avoided.

On older kernels which lack the relevant small-bar uAPI support (see also &drm_i915_memory_region_info.probed_cpu_visible_size), usage of the flag will result in an error, but it should NEVER be possible to end up with a small BAR configuration, assuming we can also successfully load the i915 kernel module. In such cases the entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as such there are zero restrictions on where the object can be placed.

◆ I915_GEM_CREATE_EXT_MEMORY_REGIONS

#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0

@extensions: The chain of extensions to apply to this object.

This will be useful in the future when we need to support several different extensions, and we need to apply more than one when creating the object. See struct i915_user_extension.

If we don't supply any extensions then we get the same old gem_create behaviour.

For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see struct drm_i915_gem_create_ext_memory_regions.

For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see struct drm_i915_gem_create_ext_protected_content.

For I915_GEM_CREATE_EXT_SET_PAT usage see struct drm_i915_gem_create_ext_set_pat.

◆ I915_GEM_CREATE_EXT_PROTECTED_CONTENT

#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1

◆ I915_GEM_CREATE_EXT_SET_PAT

#define I915_GEM_CREATE_EXT_SET_PAT 2

◆ I915_GEM_DOMAIN_COMMAND

#define I915_GEM_DOMAIN_COMMAND 0x00000008

Command queue, used to load batch buffers

◆ I915_GEM_DOMAIN_CPU

#define I915_GEM_DOMAIN_CPU 0x00000001

Intel memory domains

Most of these just align with the various caches in the system and are used to flush and invalidate as objects end up cached in different domains. CPU cache

◆ I915_GEM_DOMAIN_GTT

#define I915_GEM_DOMAIN_GTT 0x00000040

GTT domain - aperture and scanout

◆ I915_GEM_DOMAIN_INSTRUCTION

#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010

Instruction cache, used by shader programs

◆ I915_GEM_DOMAIN_RENDER

#define I915_GEM_DOMAIN_RENDER 0x00000002

Render cache, used by 2D and 3D drawing

◆ I915_GEM_DOMAIN_SAMPLER

#define I915_GEM_DOMAIN_SAMPLER 0x00000004

Sampler cache, used by texture engine

◆ I915_GEM_DOMAIN_VERTEX

#define I915_GEM_DOMAIN_VERTEX 0x00000020

Vertex address cache

◆ I915_GEM_DOMAIN_WC

#define I915_GEM_DOMAIN_WC 0x00000080

WC domain - uncached access

◆ I915_GEM_PPGTT_ALIASING

#define I915_GEM_PPGTT_ALIASING 1

◆ I915_GEM_PPGTT_FULL

#define I915_GEM_PPGTT_FULL 2

◆ I915_GEM_PPGTT_NONE

#define I915_GEM_PPGTT_NONE 0

◆ I915_L3_PARITY_UEVENT

#define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"

DOC: uevents generated by i915 on its device node

I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch event from the GPU L3 cache. Additional information supplied is ROW, BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep track of these events, and if a specific cache-line seems to have a persistent error, remap it with the L3 remapping tool supplied in intel-gpu-tools. The value supplied with the event is always 1.

I915_ERROR_UEVENT - Generated upon error detection, currently only via hangcheck. The error detection event is a good indicator of when things began to go badly. The value supplied with the event is a 1 upon error detection, and a 0 upon reset completion, signifying no more error exists. NOTE: Disabling hangcheck or reset via module parameter will cause the related events to not be seen.

I915_RESET_UEVENT - Event is generated just before an attempt to reset the GPU. The value supplied with the event is always 1. NOTE: Disable reset via module parameter will cause this event to not be seen.

◆ I915_LOG_MIN_TEX_REGION_SIZE

#define I915_LOG_MIN_TEX_REGION_SIZE 14

◆ I915_MADV_DONTNEED

#define I915_MADV_DONTNEED 1

◆ I915_MADV_WILLNEED

#define I915_MADV_WILLNEED 0

◆ I915_MEM_REGION_AGP

#define I915_MEM_REGION_AGP 1

◆ I915_MMAP_OFFSET_FIXED

#define I915_MMAP_OFFSET_FIXED 4

◆ I915_MMAP_OFFSET_GTT

#define I915_MMAP_OFFSET_GTT 0

◆ I915_MMAP_OFFSET_UC

#define I915_MMAP_OFFSET_UC 3

◆ I915_MMAP_OFFSET_WB

#define I915_MMAP_OFFSET_WB 2

◆ I915_MMAP_OFFSET_WC

#define I915_MMAP_OFFSET_WC 1

◆ I915_MMAP_WC

#define I915_MMAP_WC 0x1

◆ I915_NR_TEX_REGIONS

#define I915_NR_TEX_REGIONS

Value:

255 /* table size 2k - maximum due to use

* of chars for next/prev indices */

◆ I915_OVERLAY_DEPTH_MASK

#define I915_OVERLAY_DEPTH_MASK 0xff00

◆ I915_OVERLAY_DISABLE_DEST_COLORKEY

#define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)

◆ I915_OVERLAY_ENABLE

#define I915_OVERLAY_ENABLE 0x01000000

◆ I915_OVERLAY_FLAGS_MASK

#define I915_OVERLAY_FLAGS_MASK 0xff000000

◆ I915_OVERLAY_NO_SWAP

#define I915_OVERLAY_NO_SWAP 0x000000

◆ I915_OVERLAY_RGB

#define I915_OVERLAY_RGB 0x03

◆ I915_OVERLAY_RGB15

#define I915_OVERLAY_RGB15 0x3000

◆ I915_OVERLAY_RGB16

#define I915_OVERLAY_RGB16 0x2000

◆ I915_OVERLAY_RGB24

#define I915_OVERLAY_RGB24 0x1000

◆ I915_OVERLAY_SWAP_MASK

#define I915_OVERLAY_SWAP_MASK 0xff0000

◆ I915_OVERLAY_TYPE_MASK

#define I915_OVERLAY_TYPE_MASK 0xff

◆ I915_OVERLAY_UPDATE_ATTRS

#define I915_OVERLAY_UPDATE_ATTRS (1<<0)

◆ I915_OVERLAY_UPDATE_GAMMA

#define I915_OVERLAY_UPDATE_GAMMA (1<<1)

◆ I915_OVERLAY_UV_SWAP

#define I915_OVERLAY_UV_SWAP 0x010000

◆ I915_OVERLAY_Y_AND_UV_SWAP

#define I915_OVERLAY_Y_AND_UV_SWAP 0x030000

◆ I915_OVERLAY_Y_SWAP

#define I915_OVERLAY_Y_SWAP 0x020000

◆ I915_OVERLAY_YUV410

#define I915_OVERLAY_YUV410 0x0400

◆ I915_OVERLAY_YUV411

#define I915_OVERLAY_YUV411 0x0200

◆ I915_OVERLAY_YUV420

#define I915_OVERLAY_YUV420 0x0300

◆ I915_OVERLAY_YUV422

#define I915_OVERLAY_YUV422 0x0100

◆ I915_OVERLAY_YUV_PACKED

#define I915_OVERLAY_YUV_PACKED 0x02

◆ I915_OVERLAY_YUV_PLANAR

#define I915_OVERLAY_YUV_PLANAR 0x01

◆ I915_PARAM_ALLOW_BATCHBUFFER

#define I915_PARAM_ALLOW_BATCHBUFFER 2

◆ I915_PARAM_CHIPSET_ID

#define I915_PARAM_CHIPSET_ID 4

◆ I915_PARAM_CMD_PARSER_VERSION

#define I915_PARAM_CMD_PARSER_VERSION 28

◆ I915_PARAM_CS_TIMESTAMP_FREQUENCY

#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51

◆ I915_PARAM_EU_TOTAL

#define I915_PARAM_EU_TOTAL 34

◆ I915_PARAM_HAS_ALIASING_PPGTT

#define I915_PARAM_HAS_ALIASING_PPGTT 18

◆ I915_PARAM_HAS_BLT

#define I915_PARAM_HAS_BLT 11

◆ I915_PARAM_HAS_BSD

#define I915_PARAM_HAS_BSD 10

◆ I915_PARAM_HAS_BSD2

#define I915_PARAM_HAS_BSD2 31

◆ I915_PARAM_HAS_COHERENT_PHYS_GTT

#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29

◆ I915_PARAM_HAS_COHERENT_RINGS

#define I915_PARAM_HAS_COHERENT_RINGS 13

◆ I915_PARAM_HAS_CONTEXT_FREQ_HINT

#define I915_PARAM_HAS_CONTEXT_FREQ_HINT 59

◆ I915_PARAM_HAS_CONTEXT_ISOLATION

#define I915_PARAM_HAS_CONTEXT_ISOLATION 50

◆ I915_PARAM_HAS_EXEC_ASYNC

#define I915_PARAM_HAS_EXEC_ASYNC 43

◆ I915_PARAM_HAS_EXEC_BATCH_FIRST

#define I915_PARAM_HAS_EXEC_BATCH_FIRST 48

◆ I915_PARAM_HAS_EXEC_CAPTURE

#define I915_PARAM_HAS_EXEC_CAPTURE 45

◆ I915_PARAM_HAS_EXEC_CONSTANTS

#define I915_PARAM_HAS_EXEC_CONSTANTS 14

◆ I915_PARAM_HAS_EXEC_FENCE

#define I915_PARAM_HAS_EXEC_FENCE 44

◆ I915_PARAM_HAS_EXEC_FENCE_ARRAY

#define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49

◆ I915_PARAM_HAS_EXEC_HANDLE_LUT

#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26

◆ I915_PARAM_HAS_EXEC_NO_RELOC

#define I915_PARAM_HAS_EXEC_NO_RELOC 25

◆ I915_PARAM_HAS_EXEC_SOFTPIN

#define I915_PARAM_HAS_EXEC_SOFTPIN 37

◆ I915_PARAM_HAS_EXEC_SUBMIT_FENCE

#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53

◆ I915_PARAM_HAS_EXEC_TIMELINE_FENCES

#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55

◆ I915_PARAM_HAS_EXECBUF2

#define I915_PARAM_HAS_EXECBUF2 9

◆ I915_PARAM_HAS_GEM

#define I915_PARAM_HAS_GEM 5

◆ I915_PARAM_HAS_GEN7_SOL_RESET

#define I915_PARAM_HAS_GEN7_SOL_RESET 16

◆ I915_PARAM_HAS_GPU_RESET

#define I915_PARAM_HAS_GPU_RESET 35

◆ I915_PARAM_HAS_LLC

#define I915_PARAM_HAS_LLC 17

◆ I915_PARAM_HAS_OVERLAY

#define I915_PARAM_HAS_OVERLAY 7

◆ I915_PARAM_HAS_PAGEFLIPPING

#define I915_PARAM_HAS_PAGEFLIPPING 8

◆ I915_PARAM_HAS_PINNED_BATCHES

#define I915_PARAM_HAS_PINNED_BATCHES 24

◆ I915_PARAM_HAS_POOLED_EU

#define I915_PARAM_HAS_POOLED_EU 38

◆ I915_PARAM_HAS_PRIME_VMAP_FLUSH

#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21

◆ I915_PARAM_HAS_RELAXED_DELTA

#define I915_PARAM_HAS_RELAXED_DELTA 15

◆ I915_PARAM_HAS_RELAXED_FENCING

#define I915_PARAM_HAS_RELAXED_FENCING 12

◆ I915_PARAM_HAS_RESOURCE_STREAMER

#define I915_PARAM_HAS_RESOURCE_STREAMER 36

◆ I915_PARAM_HAS_SCHEDULER

#define I915_PARAM_HAS_SCHEDULER 41

◆ I915_PARAM_HAS_SECURE_BATCHES

#define I915_PARAM_HAS_SECURE_BATCHES 23

◆ I915_PARAM_HAS_SEMAPHORES

#define I915_PARAM_HAS_SEMAPHORES 20

◆ I915_PARAM_HAS_USERPTR_PROBE

#define I915_PARAM_HAS_USERPTR_PROBE 56

◆ I915_PARAM_HAS_VEBOX

#define I915_PARAM_HAS_VEBOX 22

◆ I915_PARAM_HAS_WAIT_TIMEOUT

#define I915_PARAM_HAS_WAIT_TIMEOUT 19

◆ I915_PARAM_HAS_WT

#define I915_PARAM_HAS_WT 27

◆ I915_PARAM_HUC_STATUS

#define I915_PARAM_HUC_STATUS 42

◆ I915_PARAM_IRQ_ACTIVE

#define I915_PARAM_IRQ_ACTIVE 1

◆ I915_PARAM_LAST_DISPATCH

#define I915_PARAM_LAST_DISPATCH 3

◆ I915_PARAM_MIN_EU_IN_POOL

#define I915_PARAM_MIN_EU_IN_POOL 39

◆ I915_PARAM_MMAP_GTT_COHERENT

#define I915_PARAM_MMAP_GTT_COHERENT 52

◆ I915_PARAM_MMAP_GTT_VERSION

#define I915_PARAM_MMAP_GTT_VERSION 40

◆ I915_PARAM_MMAP_VERSION

#define I915_PARAM_MMAP_VERSION 30

◆ I915_PARAM_NUM_FENCES_AVAIL

#define I915_PARAM_NUM_FENCES_AVAIL 6

◆ I915_PARAM_OA_TIMESTAMP_FREQUENCY

#define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57

◆ I915_PARAM_PERF_REVISION

#define I915_PARAM_PERF_REVISION 54

◆ I915_PARAM_PXP_STATUS

#define I915_PARAM_PXP_STATUS 58

◆ I915_PARAM_REVISION

#define I915_PARAM_REVISION 32

◆ I915_PARAM_SLICE_MASK

#define I915_PARAM_SLICE_MASK 46

◆ I915_PARAM_SUBSLICE_MASK

#define I915_PARAM_SUBSLICE_MASK 47

◆ I915_PARAM_SUBSLICE_TOTAL

#define I915_PARAM_SUBSLICE_TOTAL 33

◆ I915_PERF_FLAG_DISABLED

#define I915_PERF_FLAG_DISABLED (1<<2)

◆ I915_PERF_FLAG_FD_CLOEXEC

#define I915_PERF_FLAG_FD_CLOEXEC (1<<0)

◆ I915_PERF_FLAG_FD_NONBLOCK

#define I915_PERF_FLAG_FD_NONBLOCK (1<<1)

◆ I915_PERF_IOCTL_CONFIG

#define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)

◆ I915_PERF_IOCTL_DISABLE

#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)

◆ I915_PERF_IOCTL_ENABLE

#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)

◆ I915_PMU_ACTUAL_FREQUENCY

#define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)

◆ I915_PMU_CLASS_SHIFT

#define I915_PMU_CLASS_SHIFT (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)

◆ I915_PMU_ENGINE_BUSY

#define I915_PMU_ENGINE_BUSY	(	class,
		instance
	)	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)

◆ I915_PMU_ENGINE_SEMA

#define I915_PMU_ENGINE_SEMA	(	class,
		instance
	)	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)

◆ I915_PMU_ENGINE_WAIT

#define I915_PMU_ENGINE_WAIT	(	class,
		instance
	)	__I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)

◆ I915_PMU_INTERRUPTS

#define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)

◆ I915_PMU_LAST

#define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY

◆ I915_PMU_RC6_RESIDENCY

#define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)

◆ I915_PMU_REQUESTED_FREQUENCY

#define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)

◆ I915_PMU_SAMPLE_BITS

#define I915_PMU_SAMPLE_BITS (4)

◆ I915_PMU_SAMPLE_INSTANCE_BITS

#define I915_PMU_SAMPLE_INSTANCE_BITS (8)

◆ I915_PMU_SAMPLE_MASK

#define I915_PMU_SAMPLE_MASK (0xf)

◆ I915_PMU_SOFTWARE_GT_AWAKE_TIME

#define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4)

◆ I915_PROTECTED_CONTENT_DEFAULT_SESSION

#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf

◆ I915_REG_READ_8B_WA

#define I915_REG_READ_8B_WA (1ul << 0)

◆ I915_RESET_UEVENT

#define I915_RESET_UEVENT "RESET"

◆ I915_SCHEDULER_CAP_ENABLED

#define I915_SCHEDULER_CAP_ENABLED (1ul << 0)

◆ I915_SCHEDULER_CAP_ENGINE_BUSY_STATS

#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)

◆ I915_SCHEDULER_CAP_PREEMPTION

#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)

◆ I915_SCHEDULER_CAP_PRIORITY

#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)

◆ I915_SCHEDULER_CAP_SEMAPHORES

#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)

◆ I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP

#define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)

◆ I915_SET_COLORKEY_DESTINATION

#define I915_SET_COLORKEY_DESTINATION (1<<1)

◆ I915_SET_COLORKEY_NONE

#define I915_SET_COLORKEY_NONE

Value:

                        (1<<0) /* Deprecated. Instead set
                        * flags==0 to disable colorkeying.
                        */

◆ I915_SET_COLORKEY_SOURCE

#define I915_SET_COLORKEY_SOURCE (1<<2)

◆ I915_SETPARAM_ALLOW_BATCHBUFFER

#define I915_SETPARAM_ALLOW_BATCHBUFFER 3

◆ I915_SETPARAM_NUM_USED_FENCES

#define I915_SETPARAM_NUM_USED_FENCES 4

◆ I915_SETPARAM_TEX_LRU_LOG_GRANULARITY

#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2

◆ I915_SETPARAM_USE_MI_BATCHBUFFER_START

#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1

◆ I915_TILING_LAST

#define I915_TILING_LAST I915_TILING_Y

◆ I915_TILING_NONE

#define I915_TILING_NONE 0

◆ I915_TILING_X

#define I915_TILING_X 1

◆ I915_TILING_Y

#define I915_TILING_Y 2

◆ I915_USERPTR_PROBE

#define I915_USERPTR_PROBE 0x2

◆ I915_USERPTR_READ_ONLY

#define I915_USERPTR_READ_ONLY 0x1

◆ I915_USERPTR_UNSYNCHRONIZED

#define I915_USERPTR_UNSYNCHRONIZED 0x80000000

◆ I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC

#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)

◆ I915_VIDEO_CLASS_CAPABILITY_HEVC

#define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)

◆ planeA_h

#define planeA_h pipeA_h

◆ planeA_w

#define planeA_w pipeA_w

◆ planeA_x

#define planeA_x pipeA_x

◆ planeA_y

#define planeA_y pipeA_y

◆ planeB_h

#define planeB_h pipeB_h

◆ planeB_w

#define planeB_w pipeB_w

◆ planeB_x

#define planeB_x pipeB_x

◆ planeB_y

#define planeB_y pipeB_y

Typedef Documentation

◆ drm_i915_batchbuffer_t

typedef struct drm_i915_batchbuffer drm_i915_batchbuffer_t

◆ drm_i915_cmdbuffer_t

typedef struct _drm_i915_cmdbuffer drm_i915_cmdbuffer_t

◆ drm_i915_getparam_t

typedef struct drm_i915_getparam drm_i915_getparam_t

typedef drm_i915_getparam_t - Driver parameter query structure. See struct drm_i915_getparam.

◆ drm_i915_hws_addr_t

typedef struct drm_i915_hws_addr drm_i915_hws_addr_t

◆ drm_i915_init_t

typedef struct _drm_i915_init drm_i915_init_t

◆ drm_i915_irq_emit_t

typedef struct drm_i915_irq_emit drm_i915_irq_emit_t

◆ drm_i915_irq_wait_t

typedef struct drm_i915_irq_wait drm_i915_irq_wait_t

◆ drm_i915_mem_alloc_t

typedef struct drm_i915_mem_alloc drm_i915_mem_alloc_t

◆ drm_i915_mem_destroy_heap_t

typedef struct drm_i915_mem_destroy_heap drm_i915_mem_destroy_heap_t

◆ drm_i915_mem_free_t

typedef struct drm_i915_mem_free drm_i915_mem_free_t

◆ drm_i915_mem_init_heap_t

typedef struct drm_i915_mem_init_heap drm_i915_mem_init_heap_t

◆ drm_i915_sarea_t

typedef struct _drm_i915_sarea drm_i915_sarea_t

◆ drm_i915_setparam_t

typedef struct drm_i915_setparam drm_i915_setparam_t

◆ drm_i915_vblank_pipe_t

typedef struct drm_i915_vblank_pipe drm_i915_vblank_pipe_t

◆ drm_i915_vblank_swap_t

typedef struct drm_i915_vblank_swap drm_i915_vblank_swap_t

Enumeration Type Documentation

◆ drm_i915_gem_engine_class

enum drm_i915_gem_engine_class

enum drm_i915_gem_engine_class - uapi engine type enumeration

Different engines serve different roles, and there may be more than one engine serving each role. This enum provides a classification of the role of the engine, which may be used when requesting operations to be performed on a certain subset of engines, or for providing information about that group.

Enumerator
I915_ENGINE_CLASS_RENDER	@I915_ENGINE_CLASS_RENDER: Render engines support instructions used for 3D, Compute (GPGPU), and programmable media workloads. These instructions fetch data and dispatch individual work items to threads that operate in parallel. The threads run small programs (called "kernels" or "shaders") on the GPU's execution units (EUs).
I915_ENGINE_CLASS_COPY	@I915_ENGINE_CLASS_COPY: Copy engines (also referred to as "blitters") support instructions that move blocks of data from one location in memory to another, or that fill a specified location of memory with fixed data. Copy engines can perform pre-defined logical or bitwise operations on the source, destination, or pattern data.
I915_ENGINE_CLASS_VIDEO	@I915_ENGINE_CLASS_VIDEO: Video engines (also referred to as "bit stream decode" (BSD) or "vdbox") support instructions that perform fixed-function media decode and encode.
I915_ENGINE_CLASS_VIDEO_ENHANCE	@I915_ENGINE_CLASS_VIDEO_ENHANCE: Video enhancement engines (also referred to as "vebox") support instructions related to image enhancement.
I915_ENGINE_CLASS_COMPUTE	@I915_ENGINE_CLASS_COMPUTE: Compute engines support a subset of the instructions available on render engines: compute engines support Compute (GPGPU) and programmable media workloads, but do not support the 3D pipeline.
I915_ENGINE_CLASS_INVALID	@I915_ENGINE_CLASS_INVALID: Placeholder value to represent an invalid engine class assignment.

◆ drm_i915_gem_memory_class

enum drm_i915_gem_memory_class

enum drm_i915_gem_memory_class - Supported memory classes

Enumerator
I915_MEMORY_CLASS_SYSTEM	@I915_MEMORY_CLASS_SYSTEM: System memory
I915_MEMORY_CLASS_DEVICE	@I915_MEMORY_CLASS_DEVICE: Device local-memory

◆ drm_i915_oa_format

enum drm_i915_oa_format

Enumerator
I915_OA_FORMAT_A13
I915_OA_FORMAT_A29
I915_OA_FORMAT_A13_B8_C8
I915_OA_FORMAT_B4_C8
I915_OA_FORMAT_A45_B8_C8
I915_OA_FORMAT_B4_C8_A16
I915_OA_FORMAT_C4_B8
I915_OA_FORMAT_A12
I915_OA_FORMAT_A12_B8_C8
I915_OA_FORMAT_A32u40_A4u32_B8_C8
I915_OAR_FORMAT_A32u40_A4u32_B8_C8
I915_OA_FORMAT_A24u40_A14u32_B8_C8
I915_OAM_FORMAT_MPEC8u64_B8_C8
I915_OAM_FORMAT_MPEC8u32_B8_C8
I915_OA_FORMAT_MAX

◆ drm_i915_perf_property_id

enum drm_i915_perf_property_id

Enumerator
DRM_I915_PERF_PROP_CTX_HANDLE	Open the stream for a specific context handle (as used with execbuffer2). A stream opened for a specific context this way won't typically require root privileges. This property is available in perf revision 1.
DRM_I915_PERF_PROP_SAMPLE_OA	A value of 1 requests the inclusion of raw OA unit reports as part of stream samples. This property is available in perf revision 1.
DRM_I915_PERF_PROP_OA_METRICS_SET	The value specifies which set of OA unit metrics should be configured, defining the contents of any OA unit reports. This property is available in perf revision 1.
DRM_I915_PERF_PROP_OA_FORMAT	The value specifies the size and layout of OA unit reports. This property is available in perf revision 1.
DRM_I915_PERF_PROP_OA_EXPONENT	Specifying this property implicitly requests periodic OA unit sampling and (at least on Haswell) the sampling frequency is derived from this exponent as follows: 80ns * 2^(period_exponent + 1) This property is available in perf revision 1.
DRM_I915_PERF_PROP_HOLD_PREEMPTION	Specifying this property is only valid when specify a context to filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property will hold preemption of the particular context we want to gather performance data about. The execbuf2 submissions must include a drm_i915_gem_execbuffer_ext_perf parameter for this to apply. This property is available in perf revision 3.
DRM_I915_PERF_PROP_GLOBAL_SSEU	Specifying this pins all contexts to the specified SSEU power configuration for the duration of the recording. This parameter's value is a pointer to a struct drm_i915_gem_context_param_sseu. This property is available in perf revision 4.
DRM_I915_PERF_PROP_POLL_OA_PERIOD	This optional parameter specifies the timer interval in nanoseconds at which the i915 driver will check the OA buffer for available data. Minimum allowed value is 100 microseconds. A default value is used by the driver if this parameter is not specified. Note that larger timer values will reduce cpu consumption during OA perf captures. However, excessively large values would potentially result in OA buffer overwrites as captures reach end of the OA buffer. This property is available in perf revision 5.
DRM_I915_PERF_PROP_OA_ENGINE_CLASS	Multiple engines may be mapped to the same OA unit. The OA unit is identified by class:instance of any engine mapped to it. This parameter specifies the engine class and must be passed along with DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE. This property is available in perf revision 6.
DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE	This parameter specifies the engine instance and must be passed along with DRM_I915_PERF_PROP_OA_ENGINE_CLASS. This property is available in perf revision 6.
DRM_I915_PERF_PROP_MAX

◆ drm_i915_perf_record_type

enum drm_i915_perf_record_type

Enumerator
DRM_I915_PERF_RECORD_SAMPLE	Samples are the work horse record type whose contents are extensible and defined when opening an i915 perf stream based on the given properties. Boolean properties following the naming convention DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in every sample. The order of these sample properties given by userspace has no affect on the ordering of data within a sample. The order is documented here. struct { struct drm_i915_perf_record_header header; { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA };
DRM_I915_PERF_RECORD_OA_REPORT_LOST
DRM_I915_PERF_RECORD_OA_BUFFER_LOST	An error occurred that resulted in all pending OA reports being lost.
DRM_I915_PERF_RECORD_MAX

◆ drm_i915_pmu_engine_sample

enum drm_i915_pmu_engine_sample

DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915

Enumerator
I915_SAMPLE_BUSY
I915_SAMPLE_WAIT
I915_SAMPLE_SEMA

◆ i915_mocs_table_index

enum i915_mocs_table_index

Enumerator
I915_MOCS_UNCACHED
I915_MOCS_PTE
I915_MOCS_CACHED

Function Documentation

◆ attribute()

struct i915_context_engines_load_balance __attribute__ ( (packed) )

BSD 2-Clause License

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Variable Documentation

◆ attribute

struct drm_i915_gem_context_create_ext_setparam __attribute__

◆ __packed

struct i915_context_engines_parallel_submit __packed

◆ base

struct i915_user_extension base

◆ engine

struct i915_engine_class_instance engine

@engine: Engine class & instance to be configured.

◆ engine_index

__u16 engine_index

◆ engines

struct i915_engine_class_instance engines

◆ extensions

__u64 extensions

◆ flags

__u32 flags

@flags: One of the supported flags or zero.

◆ image

__u64 image

Userspace memory containing the context image.

◆ master

struct i915_engine_class_instance master

◆ mbz

__u32 mbz

@mbz: Must be zero.

◆ mbz64

__u64 mbz64

◆ num_bonds

__u16 num_bonds

◆ num_siblings

__u16 num_siblings

◆ size

__u32 size

@size: Size of the image blob pointed to by

◆ virtual_index

__u16 virtual_index

Classes

Macros

Typedefs

Enumerations

Functions

Variables

Macro Definition Documentation

◆ ___I915_PMU_OTHER

◆ __EXEC_OBJECT_UNKNOWN_FLAGS

◆ __I915_EXEC_FENCE_UNKNOWN_FLAGS

◆ __I915_EXEC_UNKNOWN_FLAGS

◆ __I915_MADV_PURGED

◆ __I915_PMU_ACTUAL_FREQUENCY

◆ __I915_PMU_ENGINE

◆ __I915_PMU_GT_SHIFT

◆ __I915_PMU_INTERRUPTS

◆ __I915_PMU_OTHER

◆ __I915_PMU_RC6_RESIDENCY

◆ __I915_PMU_REQUESTED_FREQUENCY

◆ __I915_PMU_SOFTWARE_GT_AWAKE_TIME

◆ DRM_I915_ALLOC

◆ DRM_I915_BATCHBUFFER

◆ DRM_I915_CMDBUFFER

◆ DRM_I915_DESTROY_HEAP

◆ DRM_I915_FLIP

◆ DRM_I915_FLUSH

◆ DRM_I915_FREE

◆ DRM_I915_GEM_BUSY

◆ DRM_I915_GEM_CONTEXT_CREATE

◆ DRM_I915_GEM_CONTEXT_DESTROY

◆ DRM_I915_GEM_CONTEXT_GETPARAM

◆ DRM_I915_GEM_CONTEXT_SETPARAM

◆ DRM_I915_GEM_CREATE

◆ DRM_I915_GEM_CREATE_EXT

◆ DRM_I915_GEM_ENTERVT

◆ DRM_I915_GEM_EXECBUFFER

◆ DRM_I915_GEM_EXECBUFFER2

◆ DRM_I915_GEM_EXECBUFFER2_WR

◆ DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES

◆ DRM_I915_GEM_GET_APERTURE

◆ DRM_I915_GEM_GET_CACHING

◆ DRM_I915_GEM_GET_TILING

◆ DRM_I915_GEM_INIT

◆ DRM_I915_GEM_LEAVEVT

◆ DRM_I915_GEM_MADVISE

◆ DRM_I915_GEM_MMAP

◆ DRM_I915_GEM_MMAP_GTT

◆ DRM_I915_GEM_PIN

◆ DRM_I915_GEM_PREAD

◆ DRM_I915_GEM_PWRITE

◆ DRM_I915_GEM_SET_CACHING

◆ DRM_I915_GEM_SET_DOMAIN

◆ DRM_I915_GEM_SET_TILING

◆ DRM_I915_GEM_SW_FINISH

◆ DRM_I915_GEM_THROTTLE

◆ DRM_I915_GEM_UNPIN

◆ DRM_I915_GEM_USERPTR

◆ DRM_I915_GEM_VM_CREATE

◆ DRM_I915_GEM_VM_DESTROY

◆ DRM_I915_GEM_WAIT

◆ DRM_I915_GET_PIPE_FROM_CRTC_ID

◆ DRM_I915_GET_RESET_STATS

◆ DRM_I915_GET_SPRITE_COLORKEY

◆ DRM_I915_GET_VBLANK_PIPE

◆ DRM_I915_GETPARAM

◆ DRM_I915_HWS_ADDR

◆ DRM_I915_INIT

◆ DRM_I915_INIT_HEAP

◆ DRM_I915_IRQ_EMIT

◆ DRM_I915_IRQ_WAIT

◆ DRM_I915_OVERLAY_ATTRS

◆ DRM_I915_OVERLAY_PUT_IMAGE

◆ DRM_I915_PERF_ADD_CONFIG

◆ DRM_I915_PERF_OPEN

◆ DRM_I915_PERF_REMOVE_CONFIG

◆ DRM_I915_QUERY

◆ DRM_I915_QUERY_ENGINE_INFO

◆ DRM_I915_QUERY_GEOMETRY_SUBSLICES

◆ DRM_I915_QUERY_GUC_SUBMISSION_VERSION

◆ DRM_I915_QUERY_HWCONFIG_BLOB