#include <i915_drm.h>
Public Attributes | |
| struct i915_user_extension | base |
| __u16 | engine_index |
| __u16 | width |
| __u16 | num_siblings |
| __u16 | mbz16 |
| __u64 | flags |
| __u64 | mbz64 [3] |
| struct i915_engine_class_instance | engines [] |
Detailed Description
struct i915_context_engines_parallel_submit - Configure engine for parallel submission.
Setup a slot in the context engine map to allow multiple BBs to be submitted in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU in parallel. Multiple hardware contexts are created internally in the i915 to run these BBs. Once a slot is configured for N BBs only N BBs can be submitted in each execbuf IOCTL and this is implicit behavior e.g. The user doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how many BBs there are based on the slot's configuration. The N BBs are the last N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.
The default placement behavior is to create implicit bonds between each context if each context maps to more than 1 physical engine (e.g. context is a virtual engine). Also we only allow contexts of same engine class and these contexts must be in logically contiguous order. Examples of the placement behavior are described below. Lastly, the default is to not allow BBs to be preempted mid-batch. Rather insert coordinated preemption points on all hardware contexts between each set of BBs. Flags could be added in the future to change both of these default behaviors.
Returns -EINVAL if hardware context placement configuration is invalid or if the placement configuration isn't supported on the platform / submission interface. Returns -ENODEV if extension isn't supported on the platform / submission interface.
.. code-block:: none
Examples syntax: CS[X] = generic engine of same class, logical instance X INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
Example 1 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=1, engines=CS[0],CS[1])
Results in the following valid placement: CS[0], CS[1]
Example 2 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[2],CS[1],CS[3])
Results in the following valid placements: CS[0], CS[1] CS[2], CS[3]
This can be thought of as two virtual engines, each containing two engines thereby making a 2D array. However, there are bonds tying the entries together and placing restrictions on how they can be scheduled. Specifically, the scheduler can choose only vertical columns from the 2D array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the scheduler wants to submit to CS[0], it must also choose CS[1] and vice versa. Same for CS[2] requires also using CS[3]. VE[0] = CS[0], CS[2] VE[1] = CS[1], CS[3]
Example 3 pseudo code: set_engines(INVALID) set_parallel(engine_index=0, width=2, num_siblings=2, engines=CS[0],CS[1],CS[1],CS[3])
Results in the following valid and invalid placements: CS[0], CS[1] CS[1], CS[3] - Not logically contiguous, return -EINVAL
Member Data Documentation
◆ base
| struct i915_user_extension i915_context_engines_parallel_submit::base |
@base: base user extension.
◆ engine_index
| __u16 i915_context_engines_parallel_submit::engine_index |
@engine_index: slot for parallel engine
◆ engines
| struct i915_engine_class_instance i915_context_engines_parallel_submit::engines[] |
@engines: 2-d array of engine instances to configure parallel engine
length = width (i) * num_siblings (j) index = j + i * num_siblings
◆ flags
| __u64 i915_context_engines_parallel_submit::flags |
@flags: all undefined flags must be zero, currently not defined flags
◆ mbz16
| __u16 i915_context_engines_parallel_submit::mbz16 |
@mbz16: reserved for future use; must be zero
◆ mbz64
| __u64 i915_context_engines_parallel_submit::mbz64[3] |
@mbz64: reserved for future use; must be zero
◆ num_siblings
| __u16 i915_context_engines_parallel_submit::num_siblings |
@num_siblings: number of siblings per context or in other words the number of possible placements for each submission
◆ width
| __u16 i915_context_engines_parallel_submit::width |
@width: number of contexts per parallel engine or in other words the number of batches in each submission
The documentation for this struct was generated from the following file:
- XenevaOS/BaseHdr/uapi/drm/i915_drm.h
