PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL Union Reference

#include <PciExpress30.h>

Public Attributes
struct {
UINT16   DownstreamPortTransmitterPreset: 4
UINT16   DownstreamPortReceiverPresetHint: 3
UINT16   Reserved: 1
UINT16   UpstreamPortTransmitterPreset: 4
UINT16   UpstreamPortReceiverPresetHint: 3
UINT16   Reserved2: 1
}	Bits
UINT16	Uint16

Member Data Documentation

[struct]

struct { ... } PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL::Bits

DownstreamPortReceiverPresetHint

UINT16 PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL::DownstreamPortReceiverPresetHint

DownstreamPortTransmitterPreset

UINT16 PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL::DownstreamPortTransmitterPreset

Reserved

UINT16 PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL::Reserved

Reserved2

UINT16 PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL::Reserved2

Uint16

UINT16 PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL::Uint16

UpstreamPortReceiverPresetHint

UINT16 PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL::UpstreamPortReceiverPresetHint

UpstreamPortTransmitterPreset

UINT16 PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL::UpstreamPortTransmitterPreset

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The documentation for this union was generated from the following file:

• XenevaOS/Boot/include/IndustryStandard/PciExpress30.h