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Classes
struct	PCI_DEVICE_INDEPENDENT_REGION

struct	PCI_DEVICE_HEADER_TYPE_REGION

struct	PCI_TYPE00

struct	PCI_BRIDGE_CONTROL_REGISTER

struct	PCI_TYPE01

union	PCI_TYPE_GENERIC

struct	PCI_CARDBUS_CONTROL_REGISTER

union	PCI_CONFIG_ACCESS_CF8

struct	EFI_PCI_CAPABILITY_HDR

union	EFI_PCI_PMC

union	EFI_PCI_PMCSR

union	EFI_PCI_PMCSR_BSE

struct	EFI_PCI_CAPABILITY_PMI

struct	EFI_PCI_CAPABILITY_AGP

struct	EFI_PCI_CAPABILITY_VPD

struct	EFI_PCI_CAPABILITY_SLOTID

struct	EFI_PCI_CAPABILITY_MSI32

struct	EFI_PCI_CAPABILITY_MSI64

struct	EFI_PCI_CAPABILITY_HOTPLUG

struct	PCI_EXPANSION_ROM_HEADER

struct	EFI_LEGACY_EXPANSION_ROM_HEADER

struct	PCI_DATA_STRUCTURE

struct	EFI_PCI_EXPANSION_ROM_HEADER

union	EFI_PCI_ROM_HEADER

Macros
#define	PCI_MAX_BUS 255

#define	PCI_MAX_DEVICE 31

#define	PCI_MAX_FUNC 7

#define	PCI_CLASS_OLD 0x00

#define	PCI_CLASS_OLD_OTHER 0x00

#define	PCI_CLASS_OLD_VGA 0x01

#define	PCI_CLASS_MASS_STORAGE 0x01

#define	PCI_CLASS_MASS_STORAGE_SCSI 0x00

#define	PCI_CLASS_MASS_STORAGE_IDE 0x01

#define	PCI_CLASS_MASS_STORAGE_FLOPPY 0x02

#define	PCI_CLASS_MASS_STORAGE_IPI 0x03

#define	PCI_CLASS_MASS_STORAGE_RAID 0x04

#define	PCI_CLASS_MASS_STORAGE_OTHER 0x80

#define	PCI_CLASS_NETWORK 0x02

#define	PCI_CLASS_NETWORK_ETHERNET 0x00

#define	PCI_CLASS_NETWORK_TOKENRING 0x01

#define	PCI_CLASS_NETWORK_FDDI 0x02

#define	PCI_CLASS_NETWORK_ATM 0x03

#define	PCI_CLASS_NETWORK_ISDN 0x04

#define	PCI_CLASS_NETWORK_OTHER 0x80

#define	PCI_CLASS_DISPLAY 0x03

#define	PCI_CLASS_DISPLAY_VGA 0x00

#define	PCI_IF_VGA_VGA 0x00

#define	PCI_IF_VGA_8514 0x01

#define	PCI_CLASS_DISPLAY_XGA 0x01

#define	PCI_CLASS_DISPLAY_3D 0x02

#define	PCI_CLASS_DISPLAY_OTHER 0x80

#define	PCI_CLASS_MEDIA 0x04

#define	PCI_CLASS_MEDIA_VIDEO 0x00

#define	PCI_CLASS_MEDIA_AUDIO 0x01

#define	PCI_CLASS_MEDIA_TELEPHONE 0x02

#define	PCI_CLASS_MEDIA_OTHER 0x80

#define	PCI_CLASS_MEMORY_CONTROLLER 0x05

#define	PCI_CLASS_MEMORY_RAM 0x00

#define	PCI_CLASS_MEMORY_FLASH 0x01

#define	PCI_CLASS_MEMORY_OTHER 0x80

#define	PCI_CLASS_BRIDGE 0x06

#define	PCI_CLASS_BRIDGE_HOST 0x00

#define	PCI_CLASS_BRIDGE_ISA 0x01

#define	PCI_CLASS_BRIDGE_EISA 0x02

#define	PCI_CLASS_BRIDGE_MCA 0x03

#define	PCI_CLASS_BRIDGE_P2P 0x04

#define	PCI_IF_BRIDGE_P2P 0x00

#define	PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01

#define	PCI_CLASS_BRIDGE_PCMCIA 0x05

#define	PCI_CLASS_BRIDGE_NUBUS 0x06

#define	PCI_CLASS_BRIDGE_CARDBUS 0x07

#define	PCI_CLASS_BRIDGE_RACEWAY 0x08

#define	PCI_CLASS_BRIDGE_OTHER 0x80

#define	PCI_CLASS_BRIDGE_ISA_PDECODE 0x80

#define	PCI_CLASS_SCC 0x07
	Simple communications controllers.

#define	PCI_SUBCLASS_SERIAL 0x00

#define	PCI_IF_GENERIC_XT 0x00

#define	PCI_IF_16450 0x01

#define	PCI_IF_16550 0x02

#define	PCI_IF_16650 0x03

#define	PCI_IF_16750 0x04

#define	PCI_IF_16850 0x05

#define	PCI_IF_16950 0x06

#define	PCI_SUBCLASS_PARALLEL 0x01

#define	PCI_IF_PARALLEL_PORT 0x00

#define	PCI_IF_BI_DIR_PARALLEL_PORT 0x01

#define	PCI_IF_ECP_PARALLEL_PORT 0x02

#define	PCI_IF_1284_CONTROLLER 0x03

#define	PCI_IF_1284_DEVICE 0xFE

#define	PCI_SUBCLASS_MULTIPORT_SERIAL 0x02

#define	PCI_SUBCLASS_MODEM 0x03

#define	PCI_IF_GENERIC_MODEM 0x00

#define	PCI_IF_16450_MODEM 0x01

#define	PCI_IF_16550_MODEM 0x02

#define	PCI_IF_16650_MODEM 0x03

#define	PCI_IF_16750_MODEM 0x04

#define	PCI_SUBCLASS_SCC_OTHER 0x80

#define	PCI_CLASS_SYSTEM_PERIPHERAL 0x08

#define	PCI_SUBCLASS_PIC 0x00

#define	PCI_IF_8259_PIC 0x00

#define	PCI_IF_ISA_PIC 0x01

#define	PCI_IF_EISA_PIC 0x02

#define	PCI_IF_APIC_CONTROLLER 0x10
	I/O APIC interrupt controller , 32 bye none-prefectable memory.

#define	PCI_IF_APIC_CONTROLLER2 0x20

#define	PCI_SUBCLASS_DMA 0x01

#define	PCI_IF_8237_DMA 0x00

#define	PCI_IF_ISA_DMA 0x01

#define	PCI_IF_EISA_DMA 0x02

#define	PCI_SUBCLASS_TIMER 0x02

#define	PCI_IF_8254_TIMER 0x00

#define	PCI_IF_ISA_TIMER 0x01

#define	PCI_IF_EISA_TIMER 0x02

#define	PCI_SUBCLASS_RTC 0x03

#define	PCI_IF_GENERIC_RTC 0x00

#define	PCI_IF_ISA_RTC 0x01

#define	PCI_SUBCLASS_PNP_CONTROLLER 0x04
	HotPlug Controller.

#define	PCI_SUBCLASS_PERIPHERAL_OTHER 0x80

#define	PCI_CLASS_INPUT_DEVICE 0x09

#define	PCI_SUBCLASS_KEYBOARD 0x00

#define	PCI_SUBCLASS_PEN 0x01

#define	PCI_SUBCLASS_MOUSE_CONTROLLER 0x02

#define	PCI_SUBCLASS_SCAN_CONTROLLER 0x03

#define	PCI_SUBCLASS_GAMEPORT 0x04

#define	PCI_IF_GAMEPORT 0x00

#define	PCI_IF_GAMEPORT1 0x10

#define	PCI_SUBCLASS_INPUT_OTHER 0x80

#define	PCI_CLASS_DOCKING_STATION 0x0A

#define	PCI_SUBCLASS_DOCKING_GENERIC 0x00

#define	PCI_SUBCLASS_DOCKING_OTHER 0x80

#define	PCI_CLASS_PROCESSOR 0x0B

#define	PCI_SUBCLASS_PROC_386 0x00

#define	PCI_SUBCLASS_PROC_486 0x01

#define	PCI_SUBCLASS_PROC_PENTIUM 0x02

#define	PCI_SUBCLASS_PROC_ALPHA 0x10

#define	PCI_SUBCLASS_PROC_POWERPC 0x20

#define	PCI_SUBCLASS_PROC_MIPS 0x30

#define	PCI_SUBCLASS_PROC_CO_PORC 0x40
	Co-Processor.

#define	PCI_CLASS_SERIAL 0x0C

#define	PCI_CLASS_SERIAL_FIREWIRE 0x00

#define	PCI_IF_1394 0x00

#define	PCI_IF_1394_OPEN_HCI 0x10

#define	PCI_CLASS_SERIAL_ACCESS_BUS 0x01

#define	PCI_CLASS_SERIAL_SSA 0x02

#define	PCI_CLASS_SERIAL_USB 0x03

#define	PCI_IF_UHCI 0x00

#define	PCI_IF_OHCI 0x10

#define	PCI_IF_USB_OTHER 0x80

#define	PCI_IF_USB_DEVICE 0xFE

#define	PCI_CLASS_SERIAL_FIBRECHANNEL 0x04

#define	PCI_CLASS_SERIAL_SMB 0x05

#define	PCI_CLASS_WIRELESS 0x0D

#define	PCI_SUBCLASS_IRDA 0x00

#define	PCI_SUBCLASS_IR 0x01

#define	PCI_SUBCLASS_RF 0x10

#define	PCI_SUBCLASS_WIRELESS_OTHER 0x80

#define	PCI_CLASS_INTELLIGENT_IO 0x0E

#define	PCI_CLASS_SATELLITE 0x0F

#define	PCI_SUBCLASS_TV 0x01

#define	PCI_SUBCLASS_AUDIO 0x02

#define	PCI_SUBCLASS_VOICE 0x03

#define	PCI_SUBCLASS_DATA 0x04

#define	PCI_SECURITY_CONTROLLER 0x10
	Encryption and decryption controller.

#define	PCI_SUBCLASS_NET_COMPUT 0x00

#define	PCI_SUBCLASS_ENTERTAINMENT 0x10

#define	PCI_SUBCLASS_SECURITY_OTHER 0x80

#define	PCI_CLASS_DPIO 0x11

#define	PCI_SUBCLASS_DPIO 0x00

#define	PCI_SUBCLASS_DPIO_OTHER 0x80

#define	IS_CLASS1(_p, c) ((_p)->Hdr.ClassCode[2] == (c))

#define	IS_CLASS2(_p, c, s) (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))

#define	IS_CLASS3(_p, c, s, p) (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))

#define	IS_PCI_DISPLAY(_p) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)

#define	IS_PCI_VGA(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)

#define	IS_PCI_8514(_p) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)

#define	IS_PCI_OLD(_p) IS_CLASS1 (_p, PCI_CLASS_OLD)

#define	IS_PCI_OLD_VGA(_p) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)

#define	IS_PCI_IDE(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)

#define	IS_PCI_SCSI(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)

#define	IS_PCI_RAID(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)

#define	IS_PCI_LPC(_p) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)

#define	IS_PCI_P2P(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)

#define	IS_PCI_P2P_SUB(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)

#define	IS_PCI_16550_SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)

#define	IS_PCI_USB(_p) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)

#define	HEADER_TYPE_DEVICE 0x00

#define	HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01

#define	HEADER_TYPE_CARDBUS_BRIDGE 0x02

#define	HEADER_TYPE_MULTI_FUNCTION 0x80

#define	HEADER_LAYOUT_CODE 0x7f

#define	IS_PCI_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))

#define	IS_CARDBUS_BRIDGE(_p) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))

#define	IS_PCI_MULTI_FUNC(_p) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)

#define	PCI_BRIDGE_ROMBAR 0x38

#define	PCI_MAX_BAR 0x0006

#define	PCI_MAX_CONFIG_OFFSET 0x0100

#define	PCI_VENDOR_ID_OFFSET 0x00

#define	PCI_DEVICE_ID_OFFSET 0x02

#define	PCI_COMMAND_OFFSET 0x04

#define	PCI_PRIMARY_STATUS_OFFSET 0x06

#define	PCI_REVISION_ID_OFFSET 0x08

#define	PCI_CLASSCODE_OFFSET 0x09

#define	PCI_CACHELINE_SIZE_OFFSET 0x0C

#define	PCI_LATENCY_TIMER_OFFSET 0x0D

#define	PCI_HEADER_TYPE_OFFSET 0x0E

#define	PCI_BIST_OFFSET 0x0F

#define	PCI_BASE_ADDRESSREG_OFFSET 0x10

#define	PCI_CARDBUS_CIS_OFFSET 0x28

#define	PCI_SVID_OFFSET 0x2C
	SubSystem Vendor id.

#define	PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C

#define	PCI_SID_OFFSET 0x2E
	SubSystem ID.

#define	PCI_SUBSYSTEM_ID_OFFSET 0x2E

#define	PCI_EXPANSION_ROM_BASE 0x30

#define	PCI_CAPBILITY_POINTER_OFFSET 0x34

#define	PCI_INT_LINE_OFFSET 0x3C
	Interrupt Line Register.

#define	PCI_INT_PIN_OFFSET 0x3D
	Interrupt Pin Register.

#define	PCI_MAXGNT_OFFSET 0x3E
	Max Grant Register.

#define	PCI_MAXLAT_OFFSET 0x3F
	Max Latency Register.

#define	PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18

#define	PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19

#define	PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a

#define	PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b

#define	PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E

#define	PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E

#define	PCI_INT_LINE_UNKNOWN 0xFF

#define	EFI_PCI_COMMAND_IO_SPACE BIT0
	0x0001

#define	EFI_PCI_COMMAND_MEMORY_SPACE BIT1
	0x0002

#define	EFI_PCI_COMMAND_BUS_MASTER BIT2
	0x0004

#define	EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3
	0x0008

#define	EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4
	0x0010

#define	EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5
	0x0020

#define	EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6
	0x0040

#define	EFI_PCI_COMMAND_STEPPING_CONTROL BIT7
	0x0080

#define	EFI_PCI_COMMAND_SERR BIT8
	0x0100

#define	EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9
	0x0200

#define	EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0
	0x0001

#define	EFI_PCI_BRIDGE_CONTROL_SERR BIT1
	0x0002

#define	EFI_PCI_BRIDGE_CONTROL_ISA BIT2
	0x0004

#define	EFI_PCI_BRIDGE_CONTROL_VGA BIT3
	0x0008

#define	EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4
	0x0010

#define	EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5
	0x0020

#define	EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6
	0x0040

#define	EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7
	0x0080

#define	EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8
	0x0100

#define	EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9
	0x0200

#define	EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10
	0x0400

#define	EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11
	0x0800

#define	EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7
	0x0080

#define	EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8
	0x0100

#define	EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9
	0x0200

#define	EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10
	0x0400

#define	EFI_PCI_STATUS_CAPABILITY BIT4
	0x0010

#define	EFI_PCI_STATUS_66MZ_CAPABLE BIT5
	0x0020

#define	EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7
	0x0080

#define	EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8
	0x0100

#define	EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14

#define	EFI_PCI_CAPABILITY_ID_PMI 0x01

#define	EFI_PCI_CAPABILITY_ID_AGP 0x02

#define	EFI_PCI_CAPABILITY_ID_VPD 0x03

#define	EFI_PCI_CAPABILITY_ID_SLOTID 0x04

#define	EFI_PCI_CAPABILITY_ID_MSI 0x05

#define	EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06

#define	EFI_PCI_CAPABILITY_ID_SHPC 0x0C

#define	EFI_PCI_PMC_D3_COLD_MASK (BIT15)

#define	PCI_POWER_STATE_D0 0

#define	PCI_POWER_STATE_D1 1

#define	PCI_POWER_STATE_D2 2

#define	PCI_POWER_STATE_D3_HOT 3

#define	PCI_BAR_IDX0 0x00

#define	PCI_BAR_IDX1 0x01

#define	PCI_BAR_IDX2 0x02

#define	PCI_BAR_IDX3 0x03

#define	PCI_BAR_IDX4 0x04

#define	PCI_BAR_IDX5 0x05

#define	EFI_ROOT_BRIDGE_LIST 'eprb'

#define	EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1
	defined in UEFI Spec.

#define	PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55

#define	PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')

#define	PCI_CODE_TYPE_PCAT_IMAGE 0x00

#define	EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001
	defined in UEFI spec.

Detailed Description

Support for PCI 2.2 standard.

This file includes the definitions in the following specifications, PCI Local Bus Specification, 2.2 PCI-to-PCI Bridge Architecture Specification, Revision 1.2 PC Card Standard, 8.0 PCI Power Management Interface Specifiction, Revision 1.2

Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2014 - 2015, Hewlett-Packard Development Company, L.P.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Macro Definition Documentation

◆ EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR

#define EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR BIT11

0x0800

◆ EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK

#define EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK BIT7

0x0080

◆ EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE

#define EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE BIT7

0x0080

◆ EFI_PCI_BRIDGE_CONTROL_ISA

#define EFI_PCI_BRIDGE_CONTROL_ISA BIT2

0x0004

◆ EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT

#define EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT BIT5

0x0020

◆ EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE

#define EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE BIT0

0x0001

◆ EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER

#define EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER BIT8

0x0100

◆ EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE

#define EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE BIT8

0x0100

◆ EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE

#define EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE BIT9

0x0200

◆ EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS

#define EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS BIT6

0x0040

◆ EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER

#define EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER BIT9

0x0200

◆ EFI_PCI_BRIDGE_CONTROL_SERR

#define EFI_PCI_BRIDGE_CONTROL_SERR BIT1

0x0002

◆ EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS

#define EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS BIT10

0x0400

◆ EFI_PCI_BRIDGE_CONTROL_VGA

#define EFI_PCI_BRIDGE_CONTROL_VGA BIT3

0x0008

◆ EFI_PCI_BRIDGE_CONTROL_VGA_16

#define EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4

0x0010

◆ EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE

#define EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE BIT10

0x0400

◆ EFI_PCI_CAPABILITY_ID_AGP

#define EFI_PCI_CAPABILITY_ID_AGP 0x02

◆ EFI_PCI_CAPABILITY_ID_HOTPLUG

#define EFI_PCI_CAPABILITY_ID_HOTPLUG 0x06

◆ EFI_PCI_CAPABILITY_ID_MSI

#define EFI_PCI_CAPABILITY_ID_MSI 0x05

◆ EFI_PCI_CAPABILITY_ID_PMI

#define EFI_PCI_CAPABILITY_ID_PMI 0x01

◆ EFI_PCI_CAPABILITY_ID_SHPC

#define EFI_PCI_CAPABILITY_ID_SHPC 0x0C

◆ EFI_PCI_CAPABILITY_ID_SLOTID

#define EFI_PCI_CAPABILITY_ID_SLOTID 0x04

◆ EFI_PCI_CAPABILITY_ID_VPD

#define EFI_PCI_CAPABILITY_ID_VPD 0x03

◆ EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR

#define EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR 0x14

defined in PC Card Standard

◆ EFI_PCI_COMMAND_BUS_MASTER

#define EFI_PCI_COMMAND_BUS_MASTER BIT2

0x0004

◆ EFI_PCI_COMMAND_FAST_BACK_TO_BACK

#define EFI_PCI_COMMAND_FAST_BACK_TO_BACK BIT9

0x0200

◆ EFI_PCI_COMMAND_IO_SPACE

#define EFI_PCI_COMMAND_IO_SPACE BIT0

0x0001

◆ EFI_PCI_COMMAND_MEMORY_SPACE

#define EFI_PCI_COMMAND_MEMORY_SPACE BIT1

0x0002

◆ EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE

#define EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE BIT4

0x0010

◆ EFI_PCI_COMMAND_PARITY_ERROR_RESPOND

#define EFI_PCI_COMMAND_PARITY_ERROR_RESPOND BIT6

0x0040

◆ EFI_PCI_COMMAND_SERR

#define EFI_PCI_COMMAND_SERR BIT8

0x0100

◆ EFI_PCI_COMMAND_SPECIAL_CYCLE

#define EFI_PCI_COMMAND_SPECIAL_CYCLE BIT3

0x0008

◆ EFI_PCI_COMMAND_STEPPING_CONTROL

#define EFI_PCI_COMMAND_STEPPING_CONTROL BIT7

0x0080

◆ EFI_PCI_COMMAND_VGA_PALETTE_SNOOP

#define EFI_PCI_COMMAND_VGA_PALETTE_SNOOP BIT5

0x0020

◆ EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED

#define EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED 0x0001

defined in UEFI spec.

◆ EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE

#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1

defined in UEFI Spec.

◆ EFI_PCI_FAST_BACK_TO_BACK_CAPABLE

#define EFI_PCI_FAST_BACK_TO_BACK_CAPABLE BIT7

0x0080

◆ EFI_PCI_MASTER_DATA_PARITY_ERROR

#define EFI_PCI_MASTER_DATA_PARITY_ERROR BIT8

0x0100

◆ EFI_PCI_PMC_D3_COLD_MASK

#define EFI_PCI_PMC_D3_COLD_MASK (BIT15)

◆ EFI_PCI_STATUS_66MZ_CAPABLE

#define EFI_PCI_STATUS_66MZ_CAPABLE BIT5

0x0020

◆ EFI_PCI_STATUS_CAPABILITY

#define EFI_PCI_STATUS_CAPABILITY BIT4

0x0010

◆ EFI_ROOT_BRIDGE_LIST

#define EFI_ROOT_BRIDGE_LIST 'eprb'

EFI PCI Option ROM definitions

◆ HEADER_LAYOUT_CODE

#define HEADER_LAYOUT_CODE 0x7f

◆ HEADER_TYPE_CARDBUS_BRIDGE

#define HEADER_TYPE_CARDBUS_BRIDGE 0x02

◆ HEADER_TYPE_DEVICE

#define HEADER_TYPE_DEVICE 0x00

◆ HEADER_TYPE_MULTI_FUNCTION

#define HEADER_TYPE_MULTI_FUNCTION 0x80

◆ HEADER_TYPE_PCI_TO_PCI_BRIDGE

#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01

◆ IS_CARDBUS_BRIDGE

#define IS_CARDBUS_BRIDGE ( _p ) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_CARDBUS_BRIDGE))

Macro that checks whether device is a CardBus bridge.

Parameters

_p	Specified device.

Return values

TRUE	Device is a CardBus bridge.
FALSE	Device is not a CardBus bridge.

◆ IS_CLASS1

#define IS_CLASS1	(	_p,
		c
	)	((_p)->Hdr.ClassCode[2] == (c))

Macro that checks whether the Base Class code of device matched.

Parameters

_p	Specified device.
c	Base Class code needs matching.

Return values

TRUE	Base Class code matches the specified device.
FALSE	Base Class code doesn't match the specified device.

◆ IS_CLASS2

#define IS_CLASS2	(	_p,
		c,
		s
	)	(IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))

Macro that checks whether the Base Class code and Sub-Class code of device matched.

Parameters

_p	Specified device.
c	Base Class code needs matching.
s	Sub-Class code needs matching.

Return values

TRUE	Base Class code and Sub-Class code match the specified device.
FALSE	Base Class code and Sub-Class code don't match the specified device.

◆ IS_CLASS3

#define IS_CLASS3	(	_p,
		c,
		s,
		p
	)	(IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))

Macro that checks whether the Base Class code, Sub-Class code and Interface code of device matched.

Parameters

_p	Specified device.
c	Base Class code needs matching.
s	Sub-Class code needs matching.
p	Interface code needs matching.

Return values

TRUE	Base Class code, Sub-Class code and Interface code match the specified device.
FALSE	Base Class code, Sub-Class code and Interface code don't match the specified device.

◆ IS_PCI_16550_SERIAL

#define IS_PCI_16550_SERIAL ( _p ) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)

Macro that checks whether device is a 16550-compatible serial controller.

Parameters

_p	Specified device.

Return values

TRUE	Device is a 16550-compatible serial controller.
FALSE	Device is not a 16550-compatible serial controller.

◆ IS_PCI_8514

#define IS_PCI_8514 ( _p ) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_8514)

Macro that checks whether device is an 8514-compatible controller.

Parameters

_p	Specified device.

Return values

TRUE	Device is an 8514-compatible controller.
FALSE	Device is not an 8514-compatible controller.

◆ IS_PCI_BRIDGE

#define IS_PCI_BRIDGE ( _p ) (((_p)->Hdr.HeaderType & HEADER_LAYOUT_CODE) == (HEADER_TYPE_PCI_TO_PCI_BRIDGE))

Macro that checks whether device is a PCI-PCI bridge.

Parameters

_p	Specified device.

Return values

TRUE	Device is a PCI-PCI bridge.
FALSE	Device is not a PCI-PCI bridge.

◆ IS_PCI_DISPLAY

#define IS_PCI_DISPLAY ( _p ) IS_CLASS1 (_p, PCI_CLASS_DISPLAY)

Macro that checks whether device is a display controller.

Parameters

_p	Specified device.

Return values

TRUE	Device is a display controller.
FALSE	Device is not a display controller.

◆ IS_PCI_IDE

#define IS_PCI_IDE ( _p ) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_IDE)

Macro that checks whether device is an IDE controller.

Parameters

_p	Specified device.

Return values

TRUE	Device is an IDE controller.
FALSE	Device is not an IDE controller.

◆ IS_PCI_LPC

#define IS_PCI_LPC ( _p ) IS_CLASS2 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA)

Macro that checks whether device is an ISA bridge.

Parameters

_p	Specified device.

Return values

TRUE	Device is an ISA bridge.
FALSE	Device is not an ISA bridge.

◆ IS_PCI_MULTI_FUNC

#define IS_PCI_MULTI_FUNC ( _p ) ((_p)->Hdr.HeaderType & HEADER_TYPE_MULTI_FUNCTION)

Macro that checks whether device is a multiple functions device.

Parameters

_p	Specified device.

Return values

TRUE	Device is a multiple functions device.
FALSE	Device is not a multiple functions device.

◆ IS_PCI_OLD

#define IS_PCI_OLD ( _p ) IS_CLASS1 (_p, PCI_CLASS_OLD)

Macro that checks whether device is built before the Class Code field was defined.

Parameters

_p	Specified device.

Return values

TRUE	Device is an old device.
FALSE	Device is not an old device.

◆ IS_PCI_OLD_VGA

#define IS_PCI_OLD_VGA ( _p ) IS_CLASS2 (_p, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA)

Macro that checks whether device is a VGA-compatible device built before the Class Code field was defined.

Parameters

_p	Specified device.

Return values

TRUE	Device is an old VGA-compatible device.
FALSE	Device is not an old VGA-compatible device.

◆ IS_PCI_P2P

#define IS_PCI_P2P ( _p ) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P)

Macro that checks whether device is a PCI-to-PCI bridge.

Parameters

_p	Specified device.

Return values

TRUE	Device is a PCI-to-PCI bridge.
FALSE	Device is not a PCI-to-PCI bridge.

◆ IS_PCI_P2P_SUB

#define IS_PCI_P2P_SUB ( _p ) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_P2P, PCI_IF_BRIDGE_P2P_SUBTRACTIVE)

Macro that checks whether device is a Subtractive Decode PCI-to-PCI bridge.

Parameters

_p	Specified device.

Return values

TRUE	Device is a Subtractive Decode PCI-to-PCI bridge.
FALSE	Device is not a Subtractive Decode PCI-to-PCI bridge.

◆ IS_PCI_RAID

#define IS_PCI_RAID ( _p ) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_RAID)

Macro that checks whether device is a RAID controller.

Parameters

_p	Specified device.

Return values

TRUE	Device is a RAID controller.
FALSE	Device is not a RAID controller.

◆ IS_PCI_SCSI

#define IS_PCI_SCSI ( _p ) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SCSI)

Macro that checks whether device is a SCSI bus controller.

Parameters

_p	Specified device.

Return values

TRUE	Device is a SCSI bus controller.
FALSE	Device is not a SCSI bus controller.

◆ IS_PCI_USB

#define IS_PCI_USB ( _p ) IS_CLASS2 (_p, PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB)

Macro that checks whether device is a Universal Serial Bus controller.

Parameters

_p	Specified device.

Return values

TRUE	Device is a Universal Serial Bus controller.
FALSE	Device is not a Universal Serial Bus controller.

◆ IS_PCI_VGA

#define IS_PCI_VGA ( _p ) IS_CLASS3 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA, PCI_IF_VGA_VGA)

Macro that checks whether device is a VGA-compatible controller.

Parameters

_p	Specified device.

Return values

TRUE	Device is a VGA-compatible controller.
FALSE	Device is not a VGA-compatible controller.

◆ PCI_BAR_IDX0

#define PCI_BAR_IDX0 0x00

◆ PCI_BAR_IDX1

#define PCI_BAR_IDX1 0x01

◆ PCI_BAR_IDX2

#define PCI_BAR_IDX2 0x02

◆ PCI_BAR_IDX3

#define PCI_BAR_IDX3 0x03

◆ PCI_BAR_IDX4

#define PCI_BAR_IDX4 0x04

◆ PCI_BAR_IDX5

#define PCI_BAR_IDX5 0x05

◆ PCI_BASE_ADDRESSREG_OFFSET

#define PCI_BASE_ADDRESSREG_OFFSET 0x10

◆ PCI_BIST_OFFSET

#define PCI_BIST_OFFSET 0x0F

◆ PCI_BRIDGE_CONTROL_REGISTER_OFFSET

#define PCI_BRIDGE_CONTROL_REGISTER_OFFSET 0x3E

◆ PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET

#define PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET 0x18

◆ PCI_BRIDGE_ROMBAR

#define PCI_BRIDGE_ROMBAR 0x38

Rom Base Address in Bridge, defined in PCI-to-PCI Bridge Architecure Specification,

◆ PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET

#define PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET 0x19

◆ PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET

#define PCI_BRIDGE_SECONDARY_LATENCY_TIMER_OFFSET 0x1b

◆ PCI_BRIDGE_STATUS_REGISTER_OFFSET

#define PCI_BRIDGE_STATUS_REGISTER_OFFSET 0x1E

◆ PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET

#define PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET 0x1a

◆ PCI_CACHELINE_SIZE_OFFSET

#define PCI_CACHELINE_SIZE_OFFSET 0x0C

◆ PCI_CAPBILITY_POINTER_OFFSET

#define PCI_CAPBILITY_POINTER_OFFSET 0x34

◆ PCI_CARDBUS_CIS_OFFSET

#define PCI_CARDBUS_CIS_OFFSET 0x28

◆ PCI_CLASS_BRIDGE

#define PCI_CLASS_BRIDGE 0x06

◆ PCI_CLASS_BRIDGE_CARDBUS

#define PCI_CLASS_BRIDGE_CARDBUS 0x07

◆ PCI_CLASS_BRIDGE_EISA

#define PCI_CLASS_BRIDGE_EISA 0x02

◆ PCI_CLASS_BRIDGE_HOST

#define PCI_CLASS_BRIDGE_HOST 0x00

◆ PCI_CLASS_BRIDGE_ISA

#define PCI_CLASS_BRIDGE_ISA 0x01

◆ PCI_CLASS_BRIDGE_ISA_PDECODE

#define PCI_CLASS_BRIDGE_ISA_PDECODE 0x80

◆ PCI_CLASS_BRIDGE_MCA

#define PCI_CLASS_BRIDGE_MCA 0x03

◆ PCI_CLASS_BRIDGE_NUBUS

#define PCI_CLASS_BRIDGE_NUBUS 0x06

◆ PCI_CLASS_BRIDGE_OTHER

#define PCI_CLASS_BRIDGE_OTHER 0x80

◆ PCI_CLASS_BRIDGE_P2P

#define PCI_CLASS_BRIDGE_P2P 0x04

◆ PCI_CLASS_BRIDGE_PCMCIA

#define PCI_CLASS_BRIDGE_PCMCIA 0x05

◆ PCI_CLASS_BRIDGE_RACEWAY

#define PCI_CLASS_BRIDGE_RACEWAY 0x08

◆ PCI_CLASS_DISPLAY

#define PCI_CLASS_DISPLAY 0x03

◆ PCI_CLASS_DISPLAY_3D

#define PCI_CLASS_DISPLAY_3D 0x02

◆ PCI_CLASS_DISPLAY_OTHER

#define PCI_CLASS_DISPLAY_OTHER 0x80

◆ PCI_CLASS_DISPLAY_VGA

#define PCI_CLASS_DISPLAY_VGA 0x00

◆ PCI_CLASS_DISPLAY_XGA

#define PCI_CLASS_DISPLAY_XGA 0x01

◆ PCI_CLASS_DOCKING_STATION

#define PCI_CLASS_DOCKING_STATION 0x0A

◆ PCI_CLASS_DPIO

#define PCI_CLASS_DPIO 0x11

◆ PCI_CLASS_INPUT_DEVICE

#define PCI_CLASS_INPUT_DEVICE 0x09

◆ PCI_CLASS_INTELLIGENT_IO

#define PCI_CLASS_INTELLIGENT_IO 0x0E

◆ PCI_CLASS_MASS_STORAGE

#define PCI_CLASS_MASS_STORAGE 0x01

◆ PCI_CLASS_MASS_STORAGE_FLOPPY

#define PCI_CLASS_MASS_STORAGE_FLOPPY 0x02

◆ PCI_CLASS_MASS_STORAGE_IDE

#define PCI_CLASS_MASS_STORAGE_IDE 0x01

◆ PCI_CLASS_MASS_STORAGE_IPI

#define PCI_CLASS_MASS_STORAGE_IPI 0x03

◆ PCI_CLASS_MASS_STORAGE_OTHER

#define PCI_CLASS_MASS_STORAGE_OTHER 0x80

◆ PCI_CLASS_MASS_STORAGE_RAID

#define PCI_CLASS_MASS_STORAGE_RAID 0x04

◆ PCI_CLASS_MASS_STORAGE_SCSI

#define PCI_CLASS_MASS_STORAGE_SCSI 0x00

◆ PCI_CLASS_MEDIA

#define PCI_CLASS_MEDIA 0x04

◆ PCI_CLASS_MEDIA_AUDIO

#define PCI_CLASS_MEDIA_AUDIO 0x01

◆ PCI_CLASS_MEDIA_OTHER

#define PCI_CLASS_MEDIA_OTHER 0x80

◆ PCI_CLASS_MEDIA_TELEPHONE

#define PCI_CLASS_MEDIA_TELEPHONE 0x02

◆ PCI_CLASS_MEDIA_VIDEO

#define PCI_CLASS_MEDIA_VIDEO 0x00

◆ PCI_CLASS_MEMORY_CONTROLLER

#define PCI_CLASS_MEMORY_CONTROLLER 0x05

◆ PCI_CLASS_MEMORY_FLASH

#define PCI_CLASS_MEMORY_FLASH 0x01

◆ PCI_CLASS_MEMORY_OTHER

#define PCI_CLASS_MEMORY_OTHER 0x80

◆ PCI_CLASS_MEMORY_RAM

#define PCI_CLASS_MEMORY_RAM 0x00

◆ PCI_CLASS_NETWORK

#define PCI_CLASS_NETWORK 0x02

◆ PCI_CLASS_NETWORK_ATM

#define PCI_CLASS_NETWORK_ATM 0x03

◆ PCI_CLASS_NETWORK_ETHERNET

#define PCI_CLASS_NETWORK_ETHERNET 0x00

◆ PCI_CLASS_NETWORK_FDDI

#define PCI_CLASS_NETWORK_FDDI 0x02

◆ PCI_CLASS_NETWORK_ISDN

#define PCI_CLASS_NETWORK_ISDN 0x04

◆ PCI_CLASS_NETWORK_OTHER

#define PCI_CLASS_NETWORK_OTHER 0x80

◆ PCI_CLASS_NETWORK_TOKENRING

#define PCI_CLASS_NETWORK_TOKENRING 0x01

◆ PCI_CLASS_OLD

#define PCI_CLASS_OLD 0x00

◆ PCI_CLASS_OLD_OTHER

#define PCI_CLASS_OLD_OTHER 0x00

◆ PCI_CLASS_OLD_VGA

#define PCI_CLASS_OLD_VGA 0x01

◆ PCI_CLASS_PROCESSOR

#define PCI_CLASS_PROCESSOR 0x0B

◆ PCI_CLASS_SATELLITE

#define PCI_CLASS_SATELLITE 0x0F

◆ PCI_CLASS_SCC

#define PCI_CLASS_SCC 0x07

Simple communications controllers.

◆ PCI_CLASS_SERIAL

#define PCI_CLASS_SERIAL 0x0C

◆ PCI_CLASS_SERIAL_ACCESS_BUS

#define PCI_CLASS_SERIAL_ACCESS_BUS 0x01

◆ PCI_CLASS_SERIAL_FIBRECHANNEL

#define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04

◆ PCI_CLASS_SERIAL_FIREWIRE

#define PCI_CLASS_SERIAL_FIREWIRE 0x00

◆ PCI_CLASS_SERIAL_SMB

#define PCI_CLASS_SERIAL_SMB 0x05

◆ PCI_CLASS_SERIAL_SSA

#define PCI_CLASS_SERIAL_SSA 0x02

◆ PCI_CLASS_SERIAL_USB

#define PCI_CLASS_SERIAL_USB 0x03

◆ PCI_CLASS_SYSTEM_PERIPHERAL

#define PCI_CLASS_SYSTEM_PERIPHERAL 0x08

◆ PCI_CLASS_WIRELESS

#define PCI_CLASS_WIRELESS 0x0D

◆ PCI_CLASSCODE_OFFSET

#define PCI_CLASSCODE_OFFSET 0x09

◆ PCI_CODE_TYPE_PCAT_IMAGE

#define PCI_CODE_TYPE_PCAT_IMAGE 0x00

◆ PCI_COMMAND_OFFSET

#define PCI_COMMAND_OFFSET 0x04

◆ PCI_DATA_STRUCTURE_SIGNATURE

#define PCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R')

◆ PCI_DEVICE_ID_OFFSET

#define PCI_DEVICE_ID_OFFSET 0x02

◆ PCI_EXPANSION_ROM_BASE

#define PCI_EXPANSION_ROM_BASE 0x30

◆ PCI_EXPANSION_ROM_HEADER_SIGNATURE

#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55

◆ PCI_HEADER_TYPE_OFFSET

#define PCI_HEADER_TYPE_OFFSET 0x0E

◆ PCI_IF_1284_CONTROLLER

#define PCI_IF_1284_CONTROLLER 0x03

◆ PCI_IF_1284_DEVICE

#define PCI_IF_1284_DEVICE 0xFE

◆ PCI_IF_1394

#define PCI_IF_1394 0x00

◆ PCI_IF_1394_OPEN_HCI

#define PCI_IF_1394_OPEN_HCI 0x10

◆ PCI_IF_16450

#define PCI_IF_16450 0x01

◆ PCI_IF_16450_MODEM

#define PCI_IF_16450_MODEM 0x01

◆ PCI_IF_16550

#define PCI_IF_16550 0x02

◆ PCI_IF_16550_MODEM

#define PCI_IF_16550_MODEM 0x02

◆ PCI_IF_16650

#define PCI_IF_16650 0x03

◆ PCI_IF_16650_MODEM

#define PCI_IF_16650_MODEM 0x03

◆ PCI_IF_16750

#define PCI_IF_16750 0x04

◆ PCI_IF_16750_MODEM

#define PCI_IF_16750_MODEM 0x04

◆ PCI_IF_16850

#define PCI_IF_16850 0x05

◆ PCI_IF_16950

#define PCI_IF_16950 0x06

◆ PCI_IF_8237_DMA

#define PCI_IF_8237_DMA 0x00

◆ PCI_IF_8254_TIMER

#define PCI_IF_8254_TIMER 0x00

◆ PCI_IF_8259_PIC

#define PCI_IF_8259_PIC 0x00

◆ PCI_IF_APIC_CONTROLLER

#define PCI_IF_APIC_CONTROLLER 0x10

I/O APIC interrupt controller , 32 bye none-prefectable memory.

◆ PCI_IF_APIC_CONTROLLER2

#define PCI_IF_APIC_CONTROLLER2 0x20

◆ PCI_IF_BI_DIR_PARALLEL_PORT

#define PCI_IF_BI_DIR_PARALLEL_PORT 0x01

◆ PCI_IF_BRIDGE_P2P

#define PCI_IF_BRIDGE_P2P 0x00

◆ PCI_IF_BRIDGE_P2P_SUBTRACTIVE

#define PCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01

◆ PCI_IF_ECP_PARALLEL_PORT

#define PCI_IF_ECP_PARALLEL_PORT 0x02

◆ PCI_IF_EISA_DMA

#define PCI_IF_EISA_DMA 0x02

◆ PCI_IF_EISA_PIC

#define PCI_IF_EISA_PIC 0x02

◆ PCI_IF_EISA_TIMER

#define PCI_IF_EISA_TIMER 0x02

◆ PCI_IF_GAMEPORT

#define PCI_IF_GAMEPORT 0x00

◆ PCI_IF_GAMEPORT1

#define PCI_IF_GAMEPORT1 0x10

◆ PCI_IF_GENERIC_MODEM

#define PCI_IF_GENERIC_MODEM 0x00

◆ PCI_IF_GENERIC_RTC

#define PCI_IF_GENERIC_RTC 0x00

◆ PCI_IF_GENERIC_XT

#define PCI_IF_GENERIC_XT 0x00

◆ PCI_IF_ISA_DMA

#define PCI_IF_ISA_DMA 0x01

◆ PCI_IF_ISA_PIC

#define PCI_IF_ISA_PIC 0x01

◆ PCI_IF_ISA_RTC

#define PCI_IF_ISA_RTC 0x01

◆ PCI_IF_ISA_TIMER

#define PCI_IF_ISA_TIMER 0x01

◆ PCI_IF_OHCI

#define PCI_IF_OHCI 0x10

◆ PCI_IF_PARALLEL_PORT

#define PCI_IF_PARALLEL_PORT 0x00

◆ PCI_IF_UHCI

#define PCI_IF_UHCI 0x00

◆ PCI_IF_USB_DEVICE

#define PCI_IF_USB_DEVICE 0xFE

◆ PCI_IF_USB_OTHER

#define PCI_IF_USB_OTHER 0x80

◆ PCI_IF_VGA_8514

#define PCI_IF_VGA_8514 0x01

◆ PCI_IF_VGA_VGA

#define PCI_IF_VGA_VGA 0x00

◆ PCI_INT_LINE_OFFSET

#define PCI_INT_LINE_OFFSET 0x3C

Interrupt Line Register.

◆ PCI_INT_LINE_UNKNOWN

#define PCI_INT_LINE_UNKNOWN 0xFF

Interrupt Line "Unknown" or "No connection" value defined for x86 based system

◆ PCI_INT_PIN_OFFSET

#define PCI_INT_PIN_OFFSET 0x3D

Interrupt Pin Register.

◆ PCI_LATENCY_TIMER_OFFSET

#define PCI_LATENCY_TIMER_OFFSET 0x0D

◆ PCI_MAX_BAR

#define PCI_MAX_BAR 0x0006

◆ PCI_MAX_BUS

#define PCI_MAX_BUS 255

◆ PCI_MAX_CONFIG_OFFSET

#define PCI_MAX_CONFIG_OFFSET 0x0100

◆ PCI_MAX_DEVICE

#define PCI_MAX_DEVICE 31

◆ PCI_MAX_FUNC

#define PCI_MAX_FUNC 7

◆ PCI_MAXGNT_OFFSET

#define PCI_MAXGNT_OFFSET 0x3E

Max Grant Register.

◆ PCI_MAXLAT_OFFSET

#define PCI_MAXLAT_OFFSET 0x3F

Max Latency Register.

◆ PCI_POWER_STATE_D0

#define PCI_POWER_STATE_D0 0

◆ PCI_POWER_STATE_D1

#define PCI_POWER_STATE_D1 1

◆ PCI_POWER_STATE_D2

#define PCI_POWER_STATE_D2 2

◆ PCI_POWER_STATE_D3_HOT

#define PCI_POWER_STATE_D3_HOT 3

◆ PCI_PRIMARY_STATUS_OFFSET

#define PCI_PRIMARY_STATUS_OFFSET 0x06

◆ PCI_REVISION_ID_OFFSET

#define PCI_REVISION_ID_OFFSET 0x08

◆ PCI_SECURITY_CONTROLLER

#define PCI_SECURITY_CONTROLLER 0x10

Encryption and decryption controller.

◆ PCI_SID_OFFSET

#define PCI_SID_OFFSET 0x2E

SubSystem ID.

◆ PCI_SUBCLASS_AUDIO

#define PCI_SUBCLASS_AUDIO 0x02

◆ PCI_SUBCLASS_DATA

#define PCI_SUBCLASS_DATA 0x04

◆ PCI_SUBCLASS_DMA

#define PCI_SUBCLASS_DMA 0x01

◆ PCI_SUBCLASS_DOCKING_GENERIC

#define PCI_SUBCLASS_DOCKING_GENERIC 0x00

◆ PCI_SUBCLASS_DOCKING_OTHER

#define PCI_SUBCLASS_DOCKING_OTHER 0x80

◆ PCI_SUBCLASS_DPIO

#define PCI_SUBCLASS_DPIO 0x00

◆ PCI_SUBCLASS_DPIO_OTHER

#define PCI_SUBCLASS_DPIO_OTHER 0x80

◆ PCI_SUBCLASS_ENTERTAINMENT

#define PCI_SUBCLASS_ENTERTAINMENT 0x10

◆ PCI_SUBCLASS_GAMEPORT

#define PCI_SUBCLASS_GAMEPORT 0x04

◆ PCI_SUBCLASS_INPUT_OTHER

#define PCI_SUBCLASS_INPUT_OTHER 0x80

◆ PCI_SUBCLASS_IR

#define PCI_SUBCLASS_IR 0x01

◆ PCI_SUBCLASS_IRDA

#define PCI_SUBCLASS_IRDA 0x00

◆ PCI_SUBCLASS_KEYBOARD

#define PCI_SUBCLASS_KEYBOARD 0x00

◆ PCI_SUBCLASS_MODEM

#define PCI_SUBCLASS_MODEM 0x03

◆ PCI_SUBCLASS_MOUSE_CONTROLLER

#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02

◆ PCI_SUBCLASS_MULTIPORT_SERIAL

#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02

◆ PCI_SUBCLASS_NET_COMPUT

#define PCI_SUBCLASS_NET_COMPUT 0x00

◆ PCI_SUBCLASS_PARALLEL

#define PCI_SUBCLASS_PARALLEL 0x01

◆ PCI_SUBCLASS_PEN

#define PCI_SUBCLASS_PEN 0x01

◆ PCI_SUBCLASS_PERIPHERAL_OTHER

#define PCI_SUBCLASS_PERIPHERAL_OTHER 0x80

◆ PCI_SUBCLASS_PIC

#define PCI_SUBCLASS_PIC 0x00

◆ PCI_SUBCLASS_PNP_CONTROLLER

#define PCI_SUBCLASS_PNP_CONTROLLER 0x04

HotPlug Controller.

◆ PCI_SUBCLASS_PROC_386

#define PCI_SUBCLASS_PROC_386 0x00

◆ PCI_SUBCLASS_PROC_486

#define PCI_SUBCLASS_PROC_486 0x01

◆ PCI_SUBCLASS_PROC_ALPHA

#define PCI_SUBCLASS_PROC_ALPHA 0x10

◆ PCI_SUBCLASS_PROC_CO_PORC

#define PCI_SUBCLASS_PROC_CO_PORC 0x40

Co-Processor.

◆ PCI_SUBCLASS_PROC_MIPS

#define PCI_SUBCLASS_PROC_MIPS 0x30

◆ PCI_SUBCLASS_PROC_PENTIUM

#define PCI_SUBCLASS_PROC_PENTIUM 0x02

◆ PCI_SUBCLASS_PROC_POWERPC

#define PCI_SUBCLASS_PROC_POWERPC 0x20

◆ PCI_SUBCLASS_RF

#define PCI_SUBCLASS_RF 0x10

◆ PCI_SUBCLASS_RTC

#define PCI_SUBCLASS_RTC 0x03

◆ PCI_SUBCLASS_SCAN_CONTROLLER

#define PCI_SUBCLASS_SCAN_CONTROLLER 0x03

◆ PCI_SUBCLASS_SCC_OTHER

#define PCI_SUBCLASS_SCC_OTHER 0x80

◆ PCI_SUBCLASS_SECURITY_OTHER

#define PCI_SUBCLASS_SECURITY_OTHER 0x80

◆ PCI_SUBCLASS_SERIAL

#define PCI_SUBCLASS_SERIAL 0x00

◆ PCI_SUBCLASS_TIMER

#define PCI_SUBCLASS_TIMER 0x02

◆ PCI_SUBCLASS_TV

#define PCI_SUBCLASS_TV 0x01

◆ PCI_SUBCLASS_VOICE

#define PCI_SUBCLASS_VOICE 0x03

◆ PCI_SUBCLASS_WIRELESS_OTHER

#define PCI_SUBCLASS_WIRELESS_OTHER 0x80

◆ PCI_SUBSYSTEM_ID_OFFSET

#define PCI_SUBSYSTEM_ID_OFFSET 0x2E

◆ PCI_SUBSYSTEM_VENDOR_ID_OFFSET

#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C

◆ PCI_SVID_OFFSET

#define PCI_SVID_OFFSET 0x2C

SubSystem Vendor id.

◆ PCI_VENDOR_ID_OFFSET

#define PCI_VENDOR_ID_OFFSET 0x00

Classes

Macros

Detailed Description

Macro Definition Documentation

◆ EFI_PCI_BRIDGE_CONTROL_DISCARD_TIMER_SERR

◆ EFI_PCI_BRIDGE_CONTROL_FAST_BACK_TO_BACK

◆ EFI_PCI_BRIDGE_CONTROL_IREQINT_ENABLE

◆ EFI_PCI_BRIDGE_CONTROL_ISA

◆ EFI_PCI_BRIDGE_CONTROL_MASTER_ABORT

◆ EFI_PCI_BRIDGE_CONTROL_PARITY_ERROR_RESPONSE

◆ EFI_PCI_BRIDGE_CONTROL_PRIMARY_DISCARD_TIMER

◆ EFI_PCI_BRIDGE_CONTROL_RANGE0_MEMORY_TYPE

◆ EFI_PCI_BRIDGE_CONTROL_RANGE1_MEMORY_TYPE

◆ EFI_PCI_BRIDGE_CONTROL_RESET_SECONDARY_BUS

◆ EFI_PCI_BRIDGE_CONTROL_SECONDARY_DISCARD_TIMER

◆ EFI_PCI_BRIDGE_CONTROL_SERR

◆ EFI_PCI_BRIDGE_CONTROL_TIMER_STATUS

◆ EFI_PCI_BRIDGE_CONTROL_VGA

◆ EFI_PCI_BRIDGE_CONTROL_VGA_16

◆ EFI_PCI_BRIDGE_CONTROL_WRITE_POSTING_ENABLE

◆ EFI_PCI_CAPABILITY_ID_AGP

◆ EFI_PCI_CAPABILITY_ID_HOTPLUG

◆ EFI_PCI_CAPABILITY_ID_MSI

◆ EFI_PCI_CAPABILITY_ID_PMI

◆ EFI_PCI_CAPABILITY_ID_SHPC

◆ EFI_PCI_CAPABILITY_ID_SLOTID

◆ EFI_PCI_CAPABILITY_ID_VPD

◆ EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR

◆ EFI_PCI_COMMAND_BUS_MASTER

◆ EFI_PCI_COMMAND_FAST_BACK_TO_BACK

◆ EFI_PCI_COMMAND_IO_SPACE

◆ EFI_PCI_COMMAND_MEMORY_SPACE

◆ EFI_PCI_COMMAND_MEMORY_WRITE_AND_INVALIDATE

◆ EFI_PCI_COMMAND_PARITY_ERROR_RESPOND

◆ EFI_PCI_COMMAND_SERR

◆ EFI_PCI_COMMAND_SPECIAL_CYCLE

◆ EFI_PCI_COMMAND_STEPPING_CONTROL

◆ EFI_PCI_COMMAND_VGA_PALETTE_SNOOP

◆ EFI_PCI_EXPANSION_ROM_HEADER_COMPRESSED

◆ EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE

◆ EFI_PCI_FAST_BACK_TO_BACK_CAPABLE

◆ EFI_PCI_MASTER_DATA_PARITY_ERROR

◆ EFI_PCI_PMC_D3_COLD_MASK

◆ EFI_PCI_STATUS_66MZ_CAPABLE

◆ EFI_PCI_STATUS_CAPABILITY

◆ EFI_ROOT_BRIDGE_LIST

◆ HEADER_LAYOUT_CODE

◆ HEADER_TYPE_CARDBUS_BRIDGE

◆ HEADER_TYPE_DEVICE

◆ HEADER_TYPE_MULTI_FUNCTION

◆ HEADER_TYPE_PCI_TO_PCI_BRIDGE

◆ IS_CARDBUS_BRIDGE

◆ IS_CLASS1

◆ IS_CLASS2

◆ IS_CLASS3

◆ IS_PCI_16550_SERIAL

◆ IS_PCI_8514

◆ IS_PCI_BRIDGE

◆ IS_PCI_DISPLAY

◆ IS_PCI_IDE

◆ IS_PCI_LPC

◆ IS_PCI_MULTI_FUNC

◆ IS_PCI_OLD

◆ IS_PCI_OLD_VGA

◆ IS_PCI_P2P

◆ IS_PCI_P2P_SUB

◆ IS_PCI_RAID

◆ IS_PCI_SCSI

◆ IS_PCI_USB

◆ IS_PCI_VGA

◆ PCI_BAR_IDX0

◆ PCI_BAR_IDX1

◆ PCI_BAR_IDX2

◆ PCI_BAR_IDX3

◆ PCI_BAR_IDX4

◆ PCI_BAR_IDX5

◆ PCI_BASE_ADDRESSREG_OFFSET

◆ PCI_BIST_OFFSET

◆ PCI_BRIDGE_CONTROL_REGISTER_OFFSET

◆ PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET