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Classes | Macros | Typedefs
radeon_drm.h File Reference
#include "drm.h"
Include dependency graph for radeon_drm.h:

Go to the source code of this file.

Classes

union  drm_radeon_cmd_header_t
 
union  drm_r300_cmd_header_t
 
struct  radeon_color_regs_t
 
struct  drm_radeon_context_regs_t
 
struct  drm_radeon_context2_regs_t
 
struct  drm_radeon_texture_regs_t
 
struct  drm_radeon_prim_t
 
struct  drm_radeon_state_t
 
struct  drm_radeon_sarea_t
 
struct  drm_radeon_init
 
struct  drm_radeon_cp_stop
 
struct  drm_radeon_fullscreen
 
union  drm_radeon_clear_rect
 
struct  drm_radeon_clear
 
struct  drm_radeon_vertex
 
struct  drm_radeon_indices
 
struct  drm_radeon_vertex2
 
struct  drm_radeon_cmd_buffer
 
struct  drm_radeon_tex_image
 
struct  drm_radeon_texture
 
struct  drm_radeon_stipple
 
struct  drm_radeon_indirect
 
struct  drm_radeon_getparam
 
struct  drm_radeon_mem_alloc
 
struct  drm_radeon_mem_free
 
struct  drm_radeon_mem_init_heap
 
struct  drm_radeon_irq_emit
 
struct  drm_radeon_irq_wait
 
struct  drm_radeon_setparam
 
struct  drm_radeon_surface_alloc
 
struct  drm_radeon_surface_free
 
struct  drm_radeon_gem_info
 
struct  drm_radeon_gem_create
 
struct  drm_radeon_gem_userptr
 
struct  drm_radeon_gem_set_tiling
 
struct  drm_radeon_gem_get_tiling
 
struct  drm_radeon_gem_mmap
 
struct  drm_radeon_gem_set_domain
 
struct  drm_radeon_gem_wait_idle
 
struct  drm_radeon_gem_busy
 
struct  drm_radeon_gem_pread
 
struct  drm_radeon_gem_pwrite
 
struct  drm_radeon_gem_op
 
struct  drm_radeon_gem_va
 
struct  drm_radeon_cs_chunk
 
struct  drm_radeon_cs_reloc
 
struct  drm_radeon_cs
 
struct  drm_radeon_info
 

Macros

#define __RADEON_SAREA_DEFINES__
 
#define RADEON_UPLOAD_CONTEXT   0x00000001
 
#define RADEON_UPLOAD_VERTFMT   0x00000002
 
#define RADEON_UPLOAD_LINE   0x00000004
 
#define RADEON_UPLOAD_BUMPMAP   0x00000008
 
#define RADEON_UPLOAD_MASKS   0x00000010
 
#define RADEON_UPLOAD_VIEWPORT   0x00000020
 
#define RADEON_UPLOAD_SETUP   0x00000040
 
#define RADEON_UPLOAD_TCL   0x00000080
 
#define RADEON_UPLOAD_MISC   0x00000100
 
#define RADEON_UPLOAD_TEX0   0x00000200
 
#define RADEON_UPLOAD_TEX1   0x00000400
 
#define RADEON_UPLOAD_TEX2   0x00000800
 
#define RADEON_UPLOAD_TEX0IMAGES   0x00001000
 
#define RADEON_UPLOAD_TEX1IMAGES   0x00002000
 
#define RADEON_UPLOAD_TEX2IMAGES   0x00004000
 
#define RADEON_UPLOAD_CLIPRECTS   0x00008000 /* handled client-side */
 
#define RADEON_REQUIRE_QUIESCENCE   0x00010000
 
#define RADEON_UPLOAD_ZBIAS   0x00020000 /* version 1.2 and newer */
 
#define RADEON_UPLOAD_ALL   0x003effff
 
#define RADEON_UPLOAD_CONTEXT_ALL   0x003e01ff
 
#define RADEON_EMIT_PP_MISC   0 /* context/7 */
 
#define RADEON_EMIT_PP_CNTL   1 /* context/3 */
 
#define RADEON_EMIT_RB3D_COLORPITCH   2 /* context/1 */
 
#define RADEON_EMIT_RE_LINE_PATTERN   3 /* line/2 */
 
#define RADEON_EMIT_SE_LINE_WIDTH   4 /* line/1 */
 
#define RADEON_EMIT_PP_LUM_MATRIX   5 /* bumpmap/1 */
 
#define RADEON_EMIT_PP_ROT_MATRIX_0   6 /* bumpmap/2 */
 
#define RADEON_EMIT_RB3D_STENCILREFMASK   7 /* masks/3 */
 
#define RADEON_EMIT_SE_VPORT_XSCALE   8 /* viewport/6 */
 
#define RADEON_EMIT_SE_CNTL   9 /* setup/2 */
 
#define RADEON_EMIT_SE_CNTL_STATUS   10 /* setup/1 */
 
#define RADEON_EMIT_RE_MISC   11 /* misc/1 */
 
#define RADEON_EMIT_PP_TXFILTER_0   12 /* tex0/6 */
 
#define RADEON_EMIT_PP_BORDER_COLOR_0   13 /* tex0/1 */
 
#define RADEON_EMIT_PP_TXFILTER_1   14 /* tex1/6 */
 
#define RADEON_EMIT_PP_BORDER_COLOR_1   15 /* tex1/1 */
 
#define RADEON_EMIT_PP_TXFILTER_2   16 /* tex2/6 */
 
#define RADEON_EMIT_PP_BORDER_COLOR_2   17 /* tex2/1 */
 
#define RADEON_EMIT_SE_ZBIAS_FACTOR   18 /* zbias/2 */
 
#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT   19 /* tcl/11 */
 
#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED   20 /* material/17 */
 
#define R200_EMIT_PP_TXCBLEND_0   21 /* tex0/4 */
 
#define R200_EMIT_PP_TXCBLEND_1   22 /* tex1/4 */
 
#define R200_EMIT_PP_TXCBLEND_2   23 /* tex2/4 */
 
#define R200_EMIT_PP_TXCBLEND_3   24 /* tex3/4 */
 
#define R200_EMIT_PP_TXCBLEND_4   25 /* tex4/4 */
 
#define R200_EMIT_PP_TXCBLEND_5   26 /* tex5/4 */
 
#define R200_EMIT_PP_TXCBLEND_6   27 /* /4 */
 
#define R200_EMIT_PP_TXCBLEND_7   28 /* /4 */
 
#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0   29 /* tcl/7 */
 
#define R200_EMIT_TFACTOR_0   30 /* tf/7 */
 
#define R200_EMIT_VTX_FMT_0   31 /* vtx/5 */
 
#define R200_EMIT_VAP_CTL   32 /* vap/1 */
 
#define R200_EMIT_MATRIX_SELECT_0   33 /* msl/5 */
 
#define R200_EMIT_TEX_PROC_CTL_2   34 /* tcg/5 */
 
#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL   35 /* tcl/1 */
 
#define R200_EMIT_PP_TXFILTER_0   36 /* tex0/6 */
 
#define R200_EMIT_PP_TXFILTER_1   37 /* tex1/6 */
 
#define R200_EMIT_PP_TXFILTER_2   38 /* tex2/6 */
 
#define R200_EMIT_PP_TXFILTER_3   39 /* tex3/6 */
 
#define R200_EMIT_PP_TXFILTER_4   40 /* tex4/6 */
 
#define R200_EMIT_PP_TXFILTER_5   41 /* tex5/6 */
 
#define R200_EMIT_PP_TXOFFSET_0   42 /* tex0/1 */
 
#define R200_EMIT_PP_TXOFFSET_1   43 /* tex1/1 */
 
#define R200_EMIT_PP_TXOFFSET_2   44 /* tex2/1 */
 
#define R200_EMIT_PP_TXOFFSET_3   45 /* tex3/1 */
 
#define R200_EMIT_PP_TXOFFSET_4   46 /* tex4/1 */
 
#define R200_EMIT_PP_TXOFFSET_5   47 /* tex5/1 */
 
#define R200_EMIT_VTE_CNTL   48 /* vte/1 */
 
#define R200_EMIT_OUTPUT_VTX_COMP_SEL   49 /* vtx/1 */
 
#define R200_EMIT_PP_TAM_DEBUG3   50 /* tam/1 */
 
#define R200_EMIT_PP_CNTL_X   51 /* cst/1 */
 
#define R200_EMIT_RB3D_DEPTHXY_OFFSET   52 /* cst/1 */
 
#define R200_EMIT_RE_AUX_SCISSOR_CNTL   53 /* cst/1 */
 
#define R200_EMIT_RE_SCISSOR_TL_0   54 /* cst/2 */
 
#define R200_EMIT_RE_SCISSOR_TL_1   55 /* cst/2 */
 
#define R200_EMIT_RE_SCISSOR_TL_2   56 /* cst/2 */
 
#define R200_EMIT_SE_VAP_CNTL_STATUS   57 /* cst/1 */
 
#define R200_EMIT_SE_VTX_STATE_CNTL   58 /* cst/1 */
 
#define R200_EMIT_RE_POINTSIZE   59 /* cst/1 */
 
#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0   60 /* cst/4 */
 
#define R200_EMIT_PP_CUBIC_FACES_0   61
 
#define R200_EMIT_PP_CUBIC_OFFSETS_0   62
 
#define R200_EMIT_PP_CUBIC_FACES_1   63
 
#define R200_EMIT_PP_CUBIC_OFFSETS_1   64
 
#define R200_EMIT_PP_CUBIC_FACES_2   65
 
#define R200_EMIT_PP_CUBIC_OFFSETS_2   66
 
#define R200_EMIT_PP_CUBIC_FACES_3   67
 
#define R200_EMIT_PP_CUBIC_OFFSETS_3   68
 
#define R200_EMIT_PP_CUBIC_FACES_4   69
 
#define R200_EMIT_PP_CUBIC_OFFSETS_4   70
 
#define R200_EMIT_PP_CUBIC_FACES_5   71
 
#define R200_EMIT_PP_CUBIC_OFFSETS_5   72
 
#define RADEON_EMIT_PP_TEX_SIZE_0   73
 
#define RADEON_EMIT_PP_TEX_SIZE_1   74
 
#define RADEON_EMIT_PP_TEX_SIZE_2   75
 
#define R200_EMIT_RB3D_BLENDCOLOR   76
 
#define R200_EMIT_TCL_POINT_SPRITE_CNTL   77
 
#define RADEON_EMIT_PP_CUBIC_FACES_0   78
 
#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0   79
 
#define RADEON_EMIT_PP_CUBIC_FACES_1   80
 
#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1   81
 
#define RADEON_EMIT_PP_CUBIC_FACES_2   82
 
#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2   83
 
#define R200_EMIT_PP_TRI_PERF_CNTL   84
 
#define R200_EMIT_PP_AFS_0   85
 
#define R200_EMIT_PP_AFS_1   86
 
#define R200_EMIT_ATF_TFACTOR   87
 
#define R200_EMIT_PP_TXCTLALL_0   88
 
#define R200_EMIT_PP_TXCTLALL_1   89
 
#define R200_EMIT_PP_TXCTLALL_2   90
 
#define R200_EMIT_PP_TXCTLALL_3   91
 
#define R200_EMIT_PP_TXCTLALL_4   92
 
#define R200_EMIT_PP_TXCTLALL_5   93
 
#define R200_EMIT_VAP_PVS_CNTL   94
 
#define RADEON_MAX_STATE_PACKETS   95
 
#define RADEON_CMD_PACKET   1 /* emit one of the register packets above */
 
#define RADEON_CMD_SCALARS   2 /* emit scalar data */
 
#define RADEON_CMD_VECTORS   3 /* emit vector data */
 
#define RADEON_CMD_DMA_DISCARD   4 /* discard current dma buf */
 
#define RADEON_CMD_PACKET3   5 /* emit hw packet */
 
#define RADEON_CMD_PACKET3_CLIP   6 /* emit hw packet wrapped in cliprects */
 
#define RADEON_CMD_SCALARS2   7 /* r200 stopgap */
 
#define RADEON_CMD_WAIT
 
#define RADEON_CMD_VECLINEAR   9 /* another r200 stopgap */
 
#define RADEON_WAIT_2D   0x1
 
#define RADEON_WAIT_3D   0x2
 
#define R300_CMD_PACKET3_CLEAR   0
 
#define R300_CMD_PACKET3_RAW   1
 
#define R300_CMD_PACKET0   1
 
#define R300_CMD_VPU   2 /* emit vertex program upload */
 
#define R300_CMD_PACKET3   3 /* emit a packet3 */
 
#define R300_CMD_END3D   4 /* emit sequence ending 3d rendering */
 
#define R300_CMD_CP_DELAY   5
 
#define R300_CMD_DMA_DISCARD   6
 
#define R300_CMD_WAIT   7
 
#define R300_WAIT_2D   0x1
 
#define R300_WAIT_3D   0x2
 
#define R300_WAIT_2D_CLEAN   0x3
 
#define R300_WAIT_3D_CLEAN   0x4
 
#define R300_NEW_WAIT_2D_3D   0x3
 
#define R300_NEW_WAIT_2D_2D_CLEAN   0x4
 
#define R300_NEW_WAIT_3D_3D_CLEAN   0x6
 
#define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN   0x8
 
#define R300_CMD_SCRATCH   8
 
#define R300_CMD_R500FP   9
 
#define RADEON_FRONT   0x1
 
#define RADEON_BACK   0x2
 
#define RADEON_DEPTH   0x4
 
#define RADEON_STENCIL   0x8
 
#define RADEON_CLEAR_FASTZ   0x80000000
 
#define RADEON_USE_HIERZ   0x40000000
 
#define RADEON_USE_COMP_ZBUF   0x20000000
 
#define R500FP_CONSTANT_TYPE   (1 << 1)
 
#define R500FP_CONSTANT_CLAMP   (1 << 2)
 
#define RADEON_POINTS   0x1
 
#define RADEON_LINES   0x2
 
#define RADEON_LINE_STRIP   0x3
 
#define RADEON_TRIANGLES   0x4
 
#define RADEON_TRIANGLE_FAN   0x5
 
#define RADEON_TRIANGLE_STRIP   0x6
 
#define RADEON_BUFFER_SIZE   65536
 
#define RADEON_INDEX_PRIM_OFFSET   20
 
#define RADEON_SCRATCH_REG_OFFSET   32
 
#define R600_SCRATCH_REG_OFFSET   256
 
#define RADEON_NR_SAREA_CLIPRECTS   12
 
#define RADEON_LOCAL_TEX_HEAP   0
 
#define RADEON_GART_TEX_HEAP   1
 
#define RADEON_NR_TEX_HEAPS   2
 
#define RADEON_NR_TEX_REGIONS   64
 
#define RADEON_LOG_TEX_GRANULARITY   16
 
#define RADEON_MAX_TEXTURE_LEVELS   12
 
#define RADEON_MAX_TEXTURE_UNITS   3
 
#define RADEON_MAX_SURFACES   8
 
#define RADEON_OFFSET_SHIFT   10
 
#define RADEON_OFFSET_ALIGN   (1 << RADEON_OFFSET_SHIFT)
 
#define RADEON_OFFSET_MASK   (RADEON_OFFSET_ALIGN - 1)
 
#define DRM_RADEON_CP_INIT   0x00
 
#define DRM_RADEON_CP_START   0x01
 
#define DRM_RADEON_CP_STOP   0x02
 
#define DRM_RADEON_CP_RESET   0x03
 
#define DRM_RADEON_CP_IDLE   0x04
 
#define DRM_RADEON_RESET   0x05
 
#define DRM_RADEON_FULLSCREEN   0x06
 
#define DRM_RADEON_SWAP   0x07
 
#define DRM_RADEON_CLEAR   0x08
 
#define DRM_RADEON_VERTEX   0x09
 
#define DRM_RADEON_INDICES   0x0A
 
#define DRM_RADEON_NOT_USED
 
#define DRM_RADEON_STIPPLE   0x0C
 
#define DRM_RADEON_INDIRECT   0x0D
 
#define DRM_RADEON_TEXTURE   0x0E
 
#define DRM_RADEON_VERTEX2   0x0F
 
#define DRM_RADEON_CMDBUF   0x10
 
#define DRM_RADEON_GETPARAM   0x11
 
#define DRM_RADEON_FLIP   0x12
 
#define DRM_RADEON_ALLOC   0x13
 
#define DRM_RADEON_FREE   0x14
 
#define DRM_RADEON_INIT_HEAP   0x15
 
#define DRM_RADEON_IRQ_EMIT   0x16
 
#define DRM_RADEON_IRQ_WAIT   0x17
 
#define DRM_RADEON_CP_RESUME   0x18
 
#define DRM_RADEON_SETPARAM   0x19
 
#define DRM_RADEON_SURF_ALLOC   0x1a
 
#define DRM_RADEON_SURF_FREE   0x1b
 
#define DRM_RADEON_GEM_INFO   0x1c
 
#define DRM_RADEON_GEM_CREATE   0x1d
 
#define DRM_RADEON_GEM_MMAP   0x1e
 
#define DRM_RADEON_GEM_PREAD   0x21
 
#define DRM_RADEON_GEM_PWRITE   0x22
 
#define DRM_RADEON_GEM_SET_DOMAIN   0x23
 
#define DRM_RADEON_GEM_WAIT_IDLE   0x24
 
#define DRM_RADEON_CS   0x26
 
#define DRM_RADEON_INFO   0x27
 
#define DRM_RADEON_GEM_SET_TILING   0x28
 
#define DRM_RADEON_GEM_GET_TILING   0x29
 
#define DRM_RADEON_GEM_BUSY   0x2a
 
#define DRM_RADEON_GEM_VA   0x2b
 
#define DRM_RADEON_GEM_OP   0x2c
 
#define DRM_RADEON_GEM_USERPTR   0x2d
 
#define DRM_IOCTL_RADEON_CP_INIT   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
 
#define DRM_IOCTL_RADEON_CP_START   DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
 
#define DRM_IOCTL_RADEON_CP_STOP   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
 
#define DRM_IOCTL_RADEON_CP_RESET   DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
 
#define DRM_IOCTL_RADEON_CP_IDLE   DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
 
#define DRM_IOCTL_RADEON_RESET   DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
 
#define DRM_IOCTL_RADEON_FULLSCREEN   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
 
#define DRM_IOCTL_RADEON_SWAP   DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
 
#define DRM_IOCTL_RADEON_CLEAR   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
 
#define DRM_IOCTL_RADEON_VERTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
 
#define DRM_IOCTL_RADEON_INDICES   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
 
#define DRM_IOCTL_RADEON_STIPPLE   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
 
#define DRM_IOCTL_RADEON_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
 
#define DRM_IOCTL_RADEON_TEXTURE   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
 
#define DRM_IOCTL_RADEON_VERTEX2   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
 
#define DRM_IOCTL_RADEON_CMDBUF   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
 
#define DRM_IOCTL_RADEON_GETPARAM   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
 
#define DRM_IOCTL_RADEON_FLIP   DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
 
#define DRM_IOCTL_RADEON_ALLOC   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
 
#define DRM_IOCTL_RADEON_FREE   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
 
#define DRM_IOCTL_RADEON_INIT_HEAP   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
 
#define DRM_IOCTL_RADEON_IRQ_EMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
 
#define DRM_IOCTL_RADEON_IRQ_WAIT   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
 
#define DRM_IOCTL_RADEON_CP_RESUME   DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
 
#define DRM_IOCTL_RADEON_SETPARAM   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
 
#define DRM_IOCTL_RADEON_SURF_ALLOC   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
 
#define DRM_IOCTL_RADEON_SURF_FREE   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
 
#define DRM_IOCTL_RADEON_GEM_INFO   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
 
#define DRM_IOCTL_RADEON_GEM_CREATE   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
 
#define DRM_IOCTL_RADEON_GEM_MMAP   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
 
#define DRM_IOCTL_RADEON_GEM_PREAD   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
 
#define DRM_IOCTL_RADEON_GEM_PWRITE   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
 
#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
 
#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE   DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
 
#define DRM_IOCTL_RADEON_CS   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
 
#define DRM_IOCTL_RADEON_INFO   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
 
#define DRM_IOCTL_RADEON_GEM_SET_TILING   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
 
#define DRM_IOCTL_RADEON_GEM_GET_TILING   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
 
#define DRM_IOCTL_RADEON_GEM_BUSY   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
 
#define DRM_IOCTL_RADEON_GEM_VA   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
 
#define DRM_IOCTL_RADEON_GEM_OP   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)
 
#define DRM_IOCTL_RADEON_GEM_USERPTR   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr)
 
#define CLEAR_X1   0
 
#define CLEAR_Y1   1
 
#define CLEAR_X2   2
 
#define CLEAR_Y2   3
 
#define CLEAR_DEPTH   4
 
#define RADEON_CARD_PCI   0
 
#define RADEON_CARD_AGP   1
 
#define RADEON_CARD_PCIE   2
 
#define RADEON_PARAM_GART_BUFFER_OFFSET   1 /* card offset of 1st GART buffer */
 
#define RADEON_PARAM_LAST_FRAME   2
 
#define RADEON_PARAM_LAST_DISPATCH   3
 
#define RADEON_PARAM_LAST_CLEAR   4
 
#define RADEON_PARAM_IRQ_NR   5
 
#define RADEON_PARAM_GART_BASE   6 /* card offset of GART base */
 
#define RADEON_PARAM_REGISTER_HANDLE   7 /* for drmMap() */
 
#define RADEON_PARAM_STATUS_HANDLE   8
 
#define RADEON_PARAM_SAREA_HANDLE   9
 
#define RADEON_PARAM_GART_TEX_HANDLE   10
 
#define RADEON_PARAM_SCRATCH_OFFSET   11
 
#define RADEON_PARAM_CARD_TYPE   12
 
#define RADEON_PARAM_VBLANK_CRTC   13 /* VBLANK CRTC */
 
#define RADEON_PARAM_FB_LOCATION   14 /* FB location */
 
#define RADEON_PARAM_NUM_GB_PIPES   15 /* num GB pipes */
 
#define RADEON_PARAM_DEVICE_ID   16
 
#define RADEON_PARAM_NUM_Z_PIPES   17 /* num Z pipes */
 
#define RADEON_MEM_REGION_GART   1
 
#define RADEON_MEM_REGION_FB   2
 
#define RADEON_SETPARAM_FB_LOCATION   1 /* determined framebuffer location */
 
#define RADEON_SETPARAM_SWITCH_TILING   2 /* enable/disable color tiling */
 
#define RADEON_SETPARAM_PCIGART_LOCATION   3 /* PCI Gart Location */
 
#define RADEON_SETPARAM_NEW_MEMMAP   4 /* Use new memory map */
 
#define RADEON_SETPARAM_PCIGART_TABLE_SIZE   5 /* PCI GART Table Size */
 
#define RADEON_SETPARAM_VBLANK_CRTC   6 /* VBLANK CRTC */
 
#define DRM_RADEON_VBLANK_CRTC1   1
 
#define DRM_RADEON_VBLANK_CRTC2   2
 
#define RADEON_GEM_DOMAIN_CPU   0x1
 
#define RADEON_GEM_DOMAIN_GTT   0x2
 
#define RADEON_GEM_DOMAIN_VRAM   0x4
 
#define RADEON_GEM_NO_BACKING_STORE   (1 << 0)
 
#define RADEON_GEM_GTT_UC   (1 << 1)
 
#define RADEON_GEM_GTT_WC   (1 << 2)
 
#define RADEON_GEM_CPU_ACCESS   (1 << 3)
 
#define RADEON_GEM_NO_CPU_ACCESS   (1 << 4)
 
#define RADEON_GEM_USERPTR_READONLY   (1 << 0)
 
#define RADEON_GEM_USERPTR_ANONONLY   (1 << 1)
 
#define RADEON_GEM_USERPTR_VALIDATE   (1 << 2)
 
#define RADEON_GEM_USERPTR_REGISTER   (1 << 3)
 
#define RADEON_TILING_MACRO   0x1
 
#define RADEON_TILING_MICRO   0x2
 
#define RADEON_TILING_SWAP_16BIT   0x4
 
#define RADEON_TILING_SWAP_32BIT   0x8
 
#define RADEON_TILING_SURFACE   0x10
 
#define RADEON_TILING_MICRO_SQUARE   0x20
 
#define RADEON_TILING_EG_BANKW_SHIFT   8
 
#define RADEON_TILING_EG_BANKW_MASK   0xf
 
#define RADEON_TILING_EG_BANKH_SHIFT   12
 
#define RADEON_TILING_EG_BANKH_MASK   0xf
 
#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT   16
 
#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK   0xf
 
#define RADEON_TILING_EG_TILE_SPLIT_SHIFT   24
 
#define RADEON_TILING_EG_TILE_SPLIT_MASK   0xf
 
#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT   28
 
#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK   0xf
 
#define RADEON_GEM_OP_GET_INITIAL_DOMAIN   0
 
#define RADEON_GEM_OP_SET_INITIAL_DOMAIN   1
 
#define RADEON_VA_MAP   1
 
#define RADEON_VA_UNMAP   2
 
#define RADEON_VA_RESULT_OK   0
 
#define RADEON_VA_RESULT_ERROR   1
 
#define RADEON_VA_RESULT_VA_EXIST   2
 
#define RADEON_VM_PAGE_VALID   (1 << 0)
 
#define RADEON_VM_PAGE_READABLE   (1 << 1)
 
#define RADEON_VM_PAGE_WRITEABLE   (1 << 2)
 
#define RADEON_VM_PAGE_SYSTEM   (1 << 3)
 
#define RADEON_VM_PAGE_SNOOPED   (1 << 4)
 
#define RADEON_CHUNK_ID_RELOCS   0x01
 
#define RADEON_CHUNK_ID_IB   0x02
 
#define RADEON_CHUNK_ID_FLAGS   0x03
 
#define RADEON_CHUNK_ID_CONST_IB   0x04
 
#define RADEON_CS_KEEP_TILING_FLAGS   0x01
 
#define RADEON_CS_USE_VM   0x02
 
#define RADEON_CS_END_OF_FRAME   0x04 /* a hint from userspace which CS is the last one */
 
#define RADEON_CS_RING_GFX   0
 
#define RADEON_CS_RING_COMPUTE   1
 
#define RADEON_CS_RING_DMA   2
 
#define RADEON_CS_RING_UVD   3
 
#define RADEON_CS_RING_VCE   4
 
#define RADEON_RELOC_PRIO_MASK   (0xf << 0)
 
#define RADEON_INFO_DEVICE_ID   0x00
 
#define RADEON_INFO_NUM_GB_PIPES   0x01
 
#define RADEON_INFO_NUM_Z_PIPES   0x02
 
#define RADEON_INFO_ACCEL_WORKING   0x03
 
#define RADEON_INFO_CRTC_FROM_ID   0x04
 
#define RADEON_INFO_ACCEL_WORKING2   0x05
 
#define RADEON_INFO_TILING_CONFIG   0x06
 
#define RADEON_INFO_WANT_HYPERZ   0x07
 
#define RADEON_INFO_WANT_CMASK   0x08 /* get access to CMASK on r300 */
 
#define RADEON_INFO_CLOCK_CRYSTAL_FREQ   0x09 /* clock crystal frequency */
 
#define RADEON_INFO_NUM_BACKENDS   0x0a /* DB/backends for r600+ - need for OQ */
 
#define RADEON_INFO_NUM_TILE_PIPES   0x0b /* tile pipes for r600+ */
 
#define RADEON_INFO_FUSION_GART_WORKING   0x0c /* fusion writes to GTT were broken before this */
 
#define RADEON_INFO_BACKEND_MAP   0x0d /* pipe to backend map, needed by mesa */
 
#define RADEON_INFO_VA_START   0x0e
 
#define RADEON_INFO_IB_VM_MAX_SIZE   0x0f
 
#define RADEON_INFO_MAX_PIPES   0x10
 
#define RADEON_INFO_TIMESTAMP   0x11
 
#define RADEON_INFO_MAX_SE   0x12
 
#define RADEON_INFO_MAX_SH_PER_SE   0x13
 
#define RADEON_INFO_FASTFB_WORKING   0x14
 
#define RADEON_INFO_RING_WORKING   0x15
 
#define RADEON_INFO_SI_TILE_MODE_ARRAY   0x16
 
#define RADEON_INFO_SI_CP_DMA_COMPUTE   0x17
 
#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY   0x18
 
#define RADEON_INFO_SI_BACKEND_ENABLED_MASK   0x19
 
#define RADEON_INFO_MAX_SCLK   0x1a
 
#define RADEON_INFO_VCE_FW_VERSION   0x1b
 
#define RADEON_INFO_VCE_FB_VERSION   0x1c
 
#define RADEON_INFO_NUM_BYTES_MOVED   0x1d
 
#define RADEON_INFO_VRAM_USAGE   0x1e
 
#define RADEON_INFO_GTT_USAGE   0x1f
 
#define RADEON_INFO_ACTIVE_CU_COUNT   0x20
 
#define RADEON_INFO_CURRENT_GPU_TEMP   0x21
 
#define RADEON_INFO_CURRENT_GPU_SCLK   0x22
 
#define RADEON_INFO_CURRENT_GPU_MCLK   0x23
 
#define RADEON_INFO_READ_REG   0x24
 
#define RADEON_INFO_VA_UNMAP_WORKING   0x25
 
#define RADEON_INFO_GPU_RESET_COUNTER   0x26
 
#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED   8
 
#define SI_TILE_MODE_COLOR_1D   13
 
#define SI_TILE_MODE_COLOR_1D_SCANOUT   9
 
#define SI_TILE_MODE_COLOR_2D_8BPP   14
 
#define SI_TILE_MODE_COLOR_2D_16BPP   15
 
#define SI_TILE_MODE_COLOR_2D_32BPP   16
 
#define SI_TILE_MODE_COLOR_2D_64BPP   17
 
#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP   11
 
#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP   12
 
#define SI_TILE_MODE_DEPTH_STENCIL_1D   4
 
#define SI_TILE_MODE_DEPTH_STENCIL_2D   0
 
#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA   3
 
#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA   3
 
#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA   2
 
#define CIK_TILE_MODE_DEPTH_STENCIL_1D   5
 

Typedefs

typedef struct drm_radeon_init drm_radeon_init_t
 
typedef struct drm_radeon_cp_stop drm_radeon_cp_stop_t
 
typedef struct drm_radeon_fullscreen drm_radeon_fullscreen_t
 
typedef union drm_radeon_clear_rect drm_radeon_clear_rect_t
 
typedef struct drm_radeon_clear drm_radeon_clear_t
 
typedef struct drm_radeon_vertex drm_radeon_vertex_t
 
typedef struct drm_radeon_indices drm_radeon_indices_t
 
typedef struct drm_radeon_vertex2 drm_radeon_vertex2_t
 
typedef struct drm_radeon_cmd_buffer drm_radeon_cmd_buffer_t
 
typedef struct drm_radeon_tex_image drm_radeon_tex_image_t
 
typedef struct drm_radeon_texture drm_radeon_texture_t
 
typedef struct drm_radeon_stipple drm_radeon_stipple_t
 
typedef struct drm_radeon_indirect drm_radeon_indirect_t
 
typedef struct drm_radeon_getparam drm_radeon_getparam_t
 
typedef struct drm_radeon_mem_alloc drm_radeon_mem_alloc_t
 
typedef struct drm_radeon_mem_free drm_radeon_mem_free_t
 
typedef struct drm_radeon_mem_init_heap drm_radeon_mem_init_heap_t
 
typedef struct drm_radeon_irq_emit drm_radeon_irq_emit_t
 
typedef struct drm_radeon_irq_wait drm_radeon_irq_wait_t
 
typedef struct drm_radeon_setparam drm_radeon_setparam_t
 
typedef struct drm_radeon_surface_alloc drm_radeon_surface_alloc_t
 
typedef struct drm_radeon_surface_free drm_radeon_surface_free_t
 

Macro Definition Documentation

◆ __RADEON_SAREA_DEFINES__

#define __RADEON_SAREA_DEFINES__

◆ CIK_TILE_MODE_DEPTH_STENCIL_1D

#define CIK_TILE_MODE_DEPTH_STENCIL_1D   5

◆ CLEAR_DEPTH

#define CLEAR_DEPTH   4

◆ CLEAR_X1

#define CLEAR_X1   0

◆ CLEAR_X2

#define CLEAR_X2   2

◆ CLEAR_Y1

#define CLEAR_Y1   1

◆ CLEAR_Y2

#define CLEAR_Y2   3

◆ DRM_IOCTL_RADEON_ALLOC

#define DRM_IOCTL_RADEON_ALLOC   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)

◆ DRM_IOCTL_RADEON_CLEAR

#define DRM_IOCTL_RADEON_CLEAR   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)

◆ DRM_IOCTL_RADEON_CMDBUF

#define DRM_IOCTL_RADEON_CMDBUF   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)

◆ DRM_IOCTL_RADEON_CP_IDLE

#define DRM_IOCTL_RADEON_CP_IDLE   DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)

◆ DRM_IOCTL_RADEON_CP_INIT

#define DRM_IOCTL_RADEON_CP_INIT   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)

◆ DRM_IOCTL_RADEON_CP_RESET

#define DRM_IOCTL_RADEON_CP_RESET   DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)

◆ DRM_IOCTL_RADEON_CP_RESUME

#define DRM_IOCTL_RADEON_CP_RESUME   DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)

◆ DRM_IOCTL_RADEON_CP_START

#define DRM_IOCTL_RADEON_CP_START   DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)

◆ DRM_IOCTL_RADEON_CP_STOP

#define DRM_IOCTL_RADEON_CP_STOP   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)

◆ DRM_IOCTL_RADEON_CS

#define DRM_IOCTL_RADEON_CS   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)

◆ DRM_IOCTL_RADEON_FLIP

#define DRM_IOCTL_RADEON_FLIP   DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)

◆ DRM_IOCTL_RADEON_FREE

#define DRM_IOCTL_RADEON_FREE   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)

◆ DRM_IOCTL_RADEON_FULLSCREEN

#define DRM_IOCTL_RADEON_FULLSCREEN   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)

◆ DRM_IOCTL_RADEON_GEM_BUSY

#define DRM_IOCTL_RADEON_GEM_BUSY   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)

◆ DRM_IOCTL_RADEON_GEM_CREATE

#define DRM_IOCTL_RADEON_GEM_CREATE   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)

◆ DRM_IOCTL_RADEON_GEM_GET_TILING

#define DRM_IOCTL_RADEON_GEM_GET_TILING   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)

◆ DRM_IOCTL_RADEON_GEM_INFO

#define DRM_IOCTL_RADEON_GEM_INFO   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)

◆ DRM_IOCTL_RADEON_GEM_MMAP

#define DRM_IOCTL_RADEON_GEM_MMAP   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)

◆ DRM_IOCTL_RADEON_GEM_OP

#define DRM_IOCTL_RADEON_GEM_OP   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)

◆ DRM_IOCTL_RADEON_GEM_PREAD

#define DRM_IOCTL_RADEON_GEM_PREAD   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)

◆ DRM_IOCTL_RADEON_GEM_PWRITE

#define DRM_IOCTL_RADEON_GEM_PWRITE   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)

◆ DRM_IOCTL_RADEON_GEM_SET_DOMAIN

#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)

◆ DRM_IOCTL_RADEON_GEM_SET_TILING

#define DRM_IOCTL_RADEON_GEM_SET_TILING   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)

◆ DRM_IOCTL_RADEON_GEM_USERPTR

#define DRM_IOCTL_RADEON_GEM_USERPTR   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr)

◆ DRM_IOCTL_RADEON_GEM_VA

#define DRM_IOCTL_RADEON_GEM_VA   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)

◆ DRM_IOCTL_RADEON_GEM_WAIT_IDLE

#define DRM_IOCTL_RADEON_GEM_WAIT_IDLE   DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)

◆ DRM_IOCTL_RADEON_GETPARAM

#define DRM_IOCTL_RADEON_GETPARAM   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)

◆ DRM_IOCTL_RADEON_INDICES

#define DRM_IOCTL_RADEON_INDICES   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)

◆ DRM_IOCTL_RADEON_INDIRECT

#define DRM_IOCTL_RADEON_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)

◆ DRM_IOCTL_RADEON_INFO

#define DRM_IOCTL_RADEON_INFO   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)

◆ DRM_IOCTL_RADEON_INIT_HEAP

#define DRM_IOCTL_RADEON_INIT_HEAP   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)

◆ DRM_IOCTL_RADEON_IRQ_EMIT

#define DRM_IOCTL_RADEON_IRQ_EMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)

◆ DRM_IOCTL_RADEON_IRQ_WAIT

#define DRM_IOCTL_RADEON_IRQ_WAIT   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)

◆ DRM_IOCTL_RADEON_RESET

#define DRM_IOCTL_RADEON_RESET   DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)

◆ DRM_IOCTL_RADEON_SETPARAM

#define DRM_IOCTL_RADEON_SETPARAM   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)

◆ DRM_IOCTL_RADEON_STIPPLE

#define DRM_IOCTL_RADEON_STIPPLE   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)

◆ DRM_IOCTL_RADEON_SURF_ALLOC

#define DRM_IOCTL_RADEON_SURF_ALLOC   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)

◆ DRM_IOCTL_RADEON_SURF_FREE

#define DRM_IOCTL_RADEON_SURF_FREE   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)

◆ DRM_IOCTL_RADEON_SWAP

#define DRM_IOCTL_RADEON_SWAP   DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)

◆ DRM_IOCTL_RADEON_TEXTURE

#define DRM_IOCTL_RADEON_TEXTURE   DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)

◆ DRM_IOCTL_RADEON_VERTEX

#define DRM_IOCTL_RADEON_VERTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)

◆ DRM_IOCTL_RADEON_VERTEX2

#define DRM_IOCTL_RADEON_VERTEX2   DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)

◆ DRM_RADEON_ALLOC

#define DRM_RADEON_ALLOC   0x13

◆ DRM_RADEON_CLEAR

#define DRM_RADEON_CLEAR   0x08

◆ DRM_RADEON_CMDBUF

#define DRM_RADEON_CMDBUF   0x10

◆ DRM_RADEON_CP_IDLE

#define DRM_RADEON_CP_IDLE   0x04

◆ DRM_RADEON_CP_INIT

#define DRM_RADEON_CP_INIT   0x00

◆ DRM_RADEON_CP_RESET

#define DRM_RADEON_CP_RESET   0x03

◆ DRM_RADEON_CP_RESUME

#define DRM_RADEON_CP_RESUME   0x18

◆ DRM_RADEON_CP_START

#define DRM_RADEON_CP_START   0x01

◆ DRM_RADEON_CP_STOP

#define DRM_RADEON_CP_STOP   0x02

◆ DRM_RADEON_CS

#define DRM_RADEON_CS   0x26

◆ DRM_RADEON_FLIP

#define DRM_RADEON_FLIP   0x12

◆ DRM_RADEON_FREE

#define DRM_RADEON_FREE   0x14

◆ DRM_RADEON_FULLSCREEN

#define DRM_RADEON_FULLSCREEN   0x06

◆ DRM_RADEON_GEM_BUSY

#define DRM_RADEON_GEM_BUSY   0x2a

◆ DRM_RADEON_GEM_CREATE

#define DRM_RADEON_GEM_CREATE   0x1d

◆ DRM_RADEON_GEM_GET_TILING

#define DRM_RADEON_GEM_GET_TILING   0x29

◆ DRM_RADEON_GEM_INFO

#define DRM_RADEON_GEM_INFO   0x1c

◆ DRM_RADEON_GEM_MMAP

#define DRM_RADEON_GEM_MMAP   0x1e

◆ DRM_RADEON_GEM_OP

#define DRM_RADEON_GEM_OP   0x2c

◆ DRM_RADEON_GEM_PREAD

#define DRM_RADEON_GEM_PREAD   0x21

◆ DRM_RADEON_GEM_PWRITE

#define DRM_RADEON_GEM_PWRITE   0x22

◆ DRM_RADEON_GEM_SET_DOMAIN

#define DRM_RADEON_GEM_SET_DOMAIN   0x23

◆ DRM_RADEON_GEM_SET_TILING

#define DRM_RADEON_GEM_SET_TILING   0x28

◆ DRM_RADEON_GEM_USERPTR

#define DRM_RADEON_GEM_USERPTR   0x2d

◆ DRM_RADEON_GEM_VA

#define DRM_RADEON_GEM_VA   0x2b

◆ DRM_RADEON_GEM_WAIT_IDLE

#define DRM_RADEON_GEM_WAIT_IDLE   0x24

◆ DRM_RADEON_GETPARAM

#define DRM_RADEON_GETPARAM   0x11

◆ DRM_RADEON_INDICES

#define DRM_RADEON_INDICES   0x0A

◆ DRM_RADEON_INDIRECT

#define DRM_RADEON_INDIRECT   0x0D

◆ DRM_RADEON_INFO

#define DRM_RADEON_INFO   0x27

◆ DRM_RADEON_INIT_HEAP

#define DRM_RADEON_INIT_HEAP   0x15

◆ DRM_RADEON_IRQ_EMIT

#define DRM_RADEON_IRQ_EMIT   0x16

◆ DRM_RADEON_IRQ_WAIT

#define DRM_RADEON_IRQ_WAIT   0x17

◆ DRM_RADEON_NOT_USED

#define DRM_RADEON_NOT_USED

◆ DRM_RADEON_RESET

#define DRM_RADEON_RESET   0x05

◆ DRM_RADEON_SETPARAM

#define DRM_RADEON_SETPARAM   0x19

◆ DRM_RADEON_STIPPLE

#define DRM_RADEON_STIPPLE   0x0C

◆ DRM_RADEON_SURF_ALLOC

#define DRM_RADEON_SURF_ALLOC   0x1a

◆ DRM_RADEON_SURF_FREE

#define DRM_RADEON_SURF_FREE   0x1b

◆ DRM_RADEON_SWAP

#define DRM_RADEON_SWAP   0x07

◆ DRM_RADEON_TEXTURE

#define DRM_RADEON_TEXTURE   0x0E

◆ DRM_RADEON_VBLANK_CRTC1

#define DRM_RADEON_VBLANK_CRTC1   1

◆ DRM_RADEON_VBLANK_CRTC2

#define DRM_RADEON_VBLANK_CRTC2   2

◆ DRM_RADEON_VERTEX

#define DRM_RADEON_VERTEX   0x09

◆ DRM_RADEON_VERTEX2

#define DRM_RADEON_VERTEX2   0x0F

◆ R200_EMIT_ATF_TFACTOR

#define R200_EMIT_ATF_TFACTOR   87

◆ R200_EMIT_MATRIX_SELECT_0

#define R200_EMIT_MATRIX_SELECT_0   33 /* msl/5 */

◆ R200_EMIT_OUTPUT_VTX_COMP_SEL

#define R200_EMIT_OUTPUT_VTX_COMP_SEL   49 /* vtx/1 */

◆ R200_EMIT_PP_AFS_0

#define R200_EMIT_PP_AFS_0   85

◆ R200_EMIT_PP_AFS_1

#define R200_EMIT_PP_AFS_1   86

◆ R200_EMIT_PP_CNTL_X

#define R200_EMIT_PP_CNTL_X   51 /* cst/1 */

◆ R200_EMIT_PP_CUBIC_FACES_0

#define R200_EMIT_PP_CUBIC_FACES_0   61

◆ R200_EMIT_PP_CUBIC_FACES_1

#define R200_EMIT_PP_CUBIC_FACES_1   63

◆ R200_EMIT_PP_CUBIC_FACES_2

#define R200_EMIT_PP_CUBIC_FACES_2   65

◆ R200_EMIT_PP_CUBIC_FACES_3

#define R200_EMIT_PP_CUBIC_FACES_3   67

◆ R200_EMIT_PP_CUBIC_FACES_4

#define R200_EMIT_PP_CUBIC_FACES_4   69

◆ R200_EMIT_PP_CUBIC_FACES_5

#define R200_EMIT_PP_CUBIC_FACES_5   71

◆ R200_EMIT_PP_CUBIC_OFFSETS_0

#define R200_EMIT_PP_CUBIC_OFFSETS_0   62

◆ R200_EMIT_PP_CUBIC_OFFSETS_1

#define R200_EMIT_PP_CUBIC_OFFSETS_1   64

◆ R200_EMIT_PP_CUBIC_OFFSETS_2

#define R200_EMIT_PP_CUBIC_OFFSETS_2   66

◆ R200_EMIT_PP_CUBIC_OFFSETS_3

#define R200_EMIT_PP_CUBIC_OFFSETS_3   68

◆ R200_EMIT_PP_CUBIC_OFFSETS_4

#define R200_EMIT_PP_CUBIC_OFFSETS_4   70

◆ R200_EMIT_PP_CUBIC_OFFSETS_5

#define R200_EMIT_PP_CUBIC_OFFSETS_5   72

◆ R200_EMIT_PP_TAM_DEBUG3

#define R200_EMIT_PP_TAM_DEBUG3   50 /* tam/1 */

◆ R200_EMIT_PP_TRI_PERF_CNTL

#define R200_EMIT_PP_TRI_PERF_CNTL   84

◆ R200_EMIT_PP_TXCBLEND_0

#define R200_EMIT_PP_TXCBLEND_0   21 /* tex0/4 */

◆ R200_EMIT_PP_TXCBLEND_1

#define R200_EMIT_PP_TXCBLEND_1   22 /* tex1/4 */

◆ R200_EMIT_PP_TXCBLEND_2

#define R200_EMIT_PP_TXCBLEND_2   23 /* tex2/4 */

◆ R200_EMIT_PP_TXCBLEND_3

#define R200_EMIT_PP_TXCBLEND_3   24 /* tex3/4 */

◆ R200_EMIT_PP_TXCBLEND_4

#define R200_EMIT_PP_TXCBLEND_4   25 /* tex4/4 */

◆ R200_EMIT_PP_TXCBLEND_5

#define R200_EMIT_PP_TXCBLEND_5   26 /* tex5/4 */

◆ R200_EMIT_PP_TXCBLEND_6

#define R200_EMIT_PP_TXCBLEND_6   27 /* /4 */

◆ R200_EMIT_PP_TXCBLEND_7

#define R200_EMIT_PP_TXCBLEND_7   28 /* /4 */

◆ R200_EMIT_PP_TXCTLALL_0

#define R200_EMIT_PP_TXCTLALL_0   88

◆ R200_EMIT_PP_TXCTLALL_1

#define R200_EMIT_PP_TXCTLALL_1   89

◆ R200_EMIT_PP_TXCTLALL_2

#define R200_EMIT_PP_TXCTLALL_2   90

◆ R200_EMIT_PP_TXCTLALL_3

#define R200_EMIT_PP_TXCTLALL_3   91

◆ R200_EMIT_PP_TXCTLALL_4

#define R200_EMIT_PP_TXCTLALL_4   92

◆ R200_EMIT_PP_TXCTLALL_5

#define R200_EMIT_PP_TXCTLALL_5   93

◆ R200_EMIT_PP_TXFILTER_0

#define R200_EMIT_PP_TXFILTER_0   36 /* tex0/6 */

◆ R200_EMIT_PP_TXFILTER_1

#define R200_EMIT_PP_TXFILTER_1   37 /* tex1/6 */

◆ R200_EMIT_PP_TXFILTER_2

#define R200_EMIT_PP_TXFILTER_2   38 /* tex2/6 */

◆ R200_EMIT_PP_TXFILTER_3

#define R200_EMIT_PP_TXFILTER_3   39 /* tex3/6 */

◆ R200_EMIT_PP_TXFILTER_4

#define R200_EMIT_PP_TXFILTER_4   40 /* tex4/6 */

◆ R200_EMIT_PP_TXFILTER_5

#define R200_EMIT_PP_TXFILTER_5   41 /* tex5/6 */

◆ R200_EMIT_PP_TXOFFSET_0

#define R200_EMIT_PP_TXOFFSET_0   42 /* tex0/1 */

◆ R200_EMIT_PP_TXOFFSET_1

#define R200_EMIT_PP_TXOFFSET_1   43 /* tex1/1 */

◆ R200_EMIT_PP_TXOFFSET_2

#define R200_EMIT_PP_TXOFFSET_2   44 /* tex2/1 */

◆ R200_EMIT_PP_TXOFFSET_3

#define R200_EMIT_PP_TXOFFSET_3   45 /* tex3/1 */

◆ R200_EMIT_PP_TXOFFSET_4

#define R200_EMIT_PP_TXOFFSET_4   46 /* tex4/1 */

◆ R200_EMIT_PP_TXOFFSET_5

#define R200_EMIT_PP_TXOFFSET_5   47 /* tex5/1 */

◆ R200_EMIT_RB3D_BLENDCOLOR

#define R200_EMIT_RB3D_BLENDCOLOR   76

◆ R200_EMIT_RB3D_DEPTHXY_OFFSET

#define R200_EMIT_RB3D_DEPTHXY_OFFSET   52 /* cst/1 */

◆ R200_EMIT_RE_AUX_SCISSOR_CNTL

#define R200_EMIT_RE_AUX_SCISSOR_CNTL   53 /* cst/1 */

◆ R200_EMIT_RE_POINTSIZE

#define R200_EMIT_RE_POINTSIZE   59 /* cst/1 */

◆ R200_EMIT_RE_SCISSOR_TL_0

#define R200_EMIT_RE_SCISSOR_TL_0   54 /* cst/2 */

◆ R200_EMIT_RE_SCISSOR_TL_1

#define R200_EMIT_RE_SCISSOR_TL_1   55 /* cst/2 */

◆ R200_EMIT_RE_SCISSOR_TL_2

#define R200_EMIT_RE_SCISSOR_TL_2   56 /* cst/2 */

◆ R200_EMIT_SE_VAP_CNTL_STATUS

#define R200_EMIT_SE_VAP_CNTL_STATUS   57 /* cst/1 */

◆ R200_EMIT_SE_VTX_STATE_CNTL

#define R200_EMIT_SE_VTX_STATE_CNTL   58 /* cst/1 */

◆ R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0

#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0   60 /* cst/4 */

◆ R200_EMIT_TCL_LIGHT_MODEL_CTL_0

#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0   29 /* tcl/7 */

◆ R200_EMIT_TCL_POINT_SPRITE_CNTL

#define R200_EMIT_TCL_POINT_SPRITE_CNTL   77

◆ R200_EMIT_TCL_UCP_VERT_BLEND_CTL

#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL   35 /* tcl/1 */

◆ R200_EMIT_TEX_PROC_CTL_2

#define R200_EMIT_TEX_PROC_CTL_2   34 /* tcg/5 */

◆ R200_EMIT_TFACTOR_0

#define R200_EMIT_TFACTOR_0   30 /* tf/7 */

◆ R200_EMIT_VAP_CTL

#define R200_EMIT_VAP_CTL   32 /* vap/1 */

◆ R200_EMIT_VAP_PVS_CNTL

#define R200_EMIT_VAP_PVS_CNTL   94

◆ R200_EMIT_VTE_CNTL

#define R200_EMIT_VTE_CNTL   48 /* vte/1 */

◆ R200_EMIT_VTX_FMT_0

#define R200_EMIT_VTX_FMT_0   31 /* vtx/5 */

◆ R300_CMD_CP_DELAY

#define R300_CMD_CP_DELAY   5

◆ R300_CMD_DMA_DISCARD

#define R300_CMD_DMA_DISCARD   6

◆ R300_CMD_END3D

#define R300_CMD_END3D   4 /* emit sequence ending 3d rendering */

◆ R300_CMD_PACKET0

#define R300_CMD_PACKET0   1

◆ R300_CMD_PACKET3

#define R300_CMD_PACKET3   3 /* emit a packet3 */

◆ R300_CMD_PACKET3_CLEAR

#define R300_CMD_PACKET3_CLEAR   0

◆ R300_CMD_PACKET3_RAW

#define R300_CMD_PACKET3_RAW   1

◆ R300_CMD_R500FP

#define R300_CMD_R500FP   9

◆ R300_CMD_SCRATCH

#define R300_CMD_SCRATCH   8

◆ R300_CMD_VPU

#define R300_CMD_VPU   2 /* emit vertex program upload */

◆ R300_CMD_WAIT

#define R300_CMD_WAIT   7

◆ R300_NEW_WAIT_2D_2D_CLEAN

#define R300_NEW_WAIT_2D_2D_CLEAN   0x4

◆ R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN

#define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN   0x8

◆ R300_NEW_WAIT_2D_3D

#define R300_NEW_WAIT_2D_3D   0x3

◆ R300_NEW_WAIT_3D_3D_CLEAN

#define R300_NEW_WAIT_3D_3D_CLEAN   0x6

◆ R300_WAIT_2D

#define R300_WAIT_2D   0x1

◆ R300_WAIT_2D_CLEAN

#define R300_WAIT_2D_CLEAN   0x3

◆ R300_WAIT_3D

#define R300_WAIT_3D   0x2

◆ R300_WAIT_3D_CLEAN

#define R300_WAIT_3D_CLEAN   0x4

◆ R500FP_CONSTANT_CLAMP

#define R500FP_CONSTANT_CLAMP   (1 << 2)

◆ R500FP_CONSTANT_TYPE

#define R500FP_CONSTANT_TYPE   (1 << 1)

◆ R600_SCRATCH_REG_OFFSET

#define R600_SCRATCH_REG_OFFSET   256

◆ RADEON_BACK

#define RADEON_BACK   0x2

◆ RADEON_BUFFER_SIZE

#define RADEON_BUFFER_SIZE   65536

◆ RADEON_CARD_AGP

#define RADEON_CARD_AGP   1

◆ RADEON_CARD_PCI

#define RADEON_CARD_PCI   0

◆ RADEON_CARD_PCIE

#define RADEON_CARD_PCIE   2

◆ RADEON_CHUNK_ID_CONST_IB

#define RADEON_CHUNK_ID_CONST_IB   0x04

◆ RADEON_CHUNK_ID_FLAGS

#define RADEON_CHUNK_ID_FLAGS   0x03

◆ RADEON_CHUNK_ID_IB

#define RADEON_CHUNK_ID_IB   0x02

◆ RADEON_CHUNK_ID_RELOCS

#define RADEON_CHUNK_ID_RELOCS   0x01

◆ RADEON_CLEAR_FASTZ

#define RADEON_CLEAR_FASTZ   0x80000000

◆ RADEON_CMD_DMA_DISCARD

#define RADEON_CMD_DMA_DISCARD   4 /* discard current dma buf */

◆ RADEON_CMD_PACKET

#define RADEON_CMD_PACKET   1 /* emit one of the register packets above */

◆ RADEON_CMD_PACKET3

#define RADEON_CMD_PACKET3   5 /* emit hw packet */

◆ RADEON_CMD_PACKET3_CLIP

#define RADEON_CMD_PACKET3_CLIP   6 /* emit hw packet wrapped in cliprects */

◆ RADEON_CMD_SCALARS

#define RADEON_CMD_SCALARS   2 /* emit scalar data */

◆ RADEON_CMD_SCALARS2

#define RADEON_CMD_SCALARS2   7 /* r200 stopgap */

◆ RADEON_CMD_VECLINEAR

#define RADEON_CMD_VECLINEAR   9 /* another r200 stopgap */

◆ RADEON_CMD_VECTORS

#define RADEON_CMD_VECTORS   3 /* emit vector data */

◆ RADEON_CMD_WAIT

#define RADEON_CMD_WAIT
Value:
8 /* emit hw wait commands -- note:
* doesn't make the cpu wait, just
* the graphics hardware */

◆ RADEON_CS_END_OF_FRAME

#define RADEON_CS_END_OF_FRAME   0x04 /* a hint from userspace which CS is the last one */

◆ RADEON_CS_KEEP_TILING_FLAGS

#define RADEON_CS_KEEP_TILING_FLAGS   0x01

◆ RADEON_CS_RING_COMPUTE

#define RADEON_CS_RING_COMPUTE   1

◆ RADEON_CS_RING_DMA

#define RADEON_CS_RING_DMA   2

◆ RADEON_CS_RING_GFX

#define RADEON_CS_RING_GFX   0

◆ RADEON_CS_RING_UVD

#define RADEON_CS_RING_UVD   3

◆ RADEON_CS_RING_VCE

#define RADEON_CS_RING_VCE   4

◆ RADEON_CS_USE_VM

#define RADEON_CS_USE_VM   0x02

◆ RADEON_DEPTH

#define RADEON_DEPTH   0x4

◆ RADEON_EMIT_PP_BORDER_COLOR_0

#define RADEON_EMIT_PP_BORDER_COLOR_0   13 /* tex0/1 */

◆ RADEON_EMIT_PP_BORDER_COLOR_1

#define RADEON_EMIT_PP_BORDER_COLOR_1   15 /* tex1/1 */

◆ RADEON_EMIT_PP_BORDER_COLOR_2

#define RADEON_EMIT_PP_BORDER_COLOR_2   17 /* tex2/1 */

◆ RADEON_EMIT_PP_CNTL

#define RADEON_EMIT_PP_CNTL   1 /* context/3 */

◆ RADEON_EMIT_PP_CUBIC_FACES_0

#define RADEON_EMIT_PP_CUBIC_FACES_0   78

◆ RADEON_EMIT_PP_CUBIC_FACES_1

#define RADEON_EMIT_PP_CUBIC_FACES_1   80

◆ RADEON_EMIT_PP_CUBIC_FACES_2

#define RADEON_EMIT_PP_CUBIC_FACES_2   82

◆ RADEON_EMIT_PP_CUBIC_OFFSETS_T0

#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0   79

◆ RADEON_EMIT_PP_CUBIC_OFFSETS_T1

#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1   81

◆ RADEON_EMIT_PP_CUBIC_OFFSETS_T2

#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2   83

◆ RADEON_EMIT_PP_LUM_MATRIX

#define RADEON_EMIT_PP_LUM_MATRIX   5 /* bumpmap/1 */

◆ RADEON_EMIT_PP_MISC

#define RADEON_EMIT_PP_MISC   0 /* context/7 */

◆ RADEON_EMIT_PP_ROT_MATRIX_0

#define RADEON_EMIT_PP_ROT_MATRIX_0   6 /* bumpmap/2 */

◆ RADEON_EMIT_PP_TEX_SIZE_0

#define RADEON_EMIT_PP_TEX_SIZE_0   73

◆ RADEON_EMIT_PP_TEX_SIZE_1

#define RADEON_EMIT_PP_TEX_SIZE_1   74

◆ RADEON_EMIT_PP_TEX_SIZE_2

#define RADEON_EMIT_PP_TEX_SIZE_2   75

◆ RADEON_EMIT_PP_TXFILTER_0

#define RADEON_EMIT_PP_TXFILTER_0   12 /* tex0/6 */

◆ RADEON_EMIT_PP_TXFILTER_1

#define RADEON_EMIT_PP_TXFILTER_1   14 /* tex1/6 */

◆ RADEON_EMIT_PP_TXFILTER_2

#define RADEON_EMIT_PP_TXFILTER_2   16 /* tex2/6 */

◆ RADEON_EMIT_RB3D_COLORPITCH

#define RADEON_EMIT_RB3D_COLORPITCH   2 /* context/1 */

◆ RADEON_EMIT_RB3D_STENCILREFMASK

#define RADEON_EMIT_RB3D_STENCILREFMASK   7 /* masks/3 */

◆ RADEON_EMIT_RE_LINE_PATTERN

#define RADEON_EMIT_RE_LINE_PATTERN   3 /* line/2 */

◆ RADEON_EMIT_RE_MISC

#define RADEON_EMIT_RE_MISC   11 /* misc/1 */

◆ RADEON_EMIT_SE_CNTL

#define RADEON_EMIT_SE_CNTL   9 /* setup/2 */

◆ RADEON_EMIT_SE_CNTL_STATUS

#define RADEON_EMIT_SE_CNTL_STATUS   10 /* setup/1 */

◆ RADEON_EMIT_SE_LINE_WIDTH

#define RADEON_EMIT_SE_LINE_WIDTH   4 /* line/1 */

◆ RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED

#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED   20 /* material/17 */

◆ RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT

#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT   19 /* tcl/11 */

◆ RADEON_EMIT_SE_VPORT_XSCALE

#define RADEON_EMIT_SE_VPORT_XSCALE   8 /* viewport/6 */

◆ RADEON_EMIT_SE_ZBIAS_FACTOR

#define RADEON_EMIT_SE_ZBIAS_FACTOR   18 /* zbias/2 */

◆ RADEON_FRONT

#define RADEON_FRONT   0x1

◆ RADEON_GART_TEX_HEAP

#define RADEON_GART_TEX_HEAP   1

◆ RADEON_GEM_CPU_ACCESS

#define RADEON_GEM_CPU_ACCESS   (1 << 3)

◆ RADEON_GEM_DOMAIN_CPU

#define RADEON_GEM_DOMAIN_CPU   0x1

◆ RADEON_GEM_DOMAIN_GTT

#define RADEON_GEM_DOMAIN_GTT   0x2

◆ RADEON_GEM_DOMAIN_VRAM

#define RADEON_GEM_DOMAIN_VRAM   0x4

◆ RADEON_GEM_GTT_UC

#define RADEON_GEM_GTT_UC   (1 << 1)

◆ RADEON_GEM_GTT_WC

#define RADEON_GEM_GTT_WC   (1 << 2)

◆ RADEON_GEM_NO_BACKING_STORE

#define RADEON_GEM_NO_BACKING_STORE   (1 << 0)

◆ RADEON_GEM_NO_CPU_ACCESS

#define RADEON_GEM_NO_CPU_ACCESS   (1 << 4)

◆ RADEON_GEM_OP_GET_INITIAL_DOMAIN

#define RADEON_GEM_OP_GET_INITIAL_DOMAIN   0

◆ RADEON_GEM_OP_SET_INITIAL_DOMAIN

#define RADEON_GEM_OP_SET_INITIAL_DOMAIN   1

◆ RADEON_GEM_USERPTR_ANONONLY

#define RADEON_GEM_USERPTR_ANONONLY   (1 << 1)

◆ RADEON_GEM_USERPTR_READONLY

#define RADEON_GEM_USERPTR_READONLY   (1 << 0)

◆ RADEON_GEM_USERPTR_REGISTER

#define RADEON_GEM_USERPTR_REGISTER   (1 << 3)

◆ RADEON_GEM_USERPTR_VALIDATE

#define RADEON_GEM_USERPTR_VALIDATE   (1 << 2)

◆ RADEON_INDEX_PRIM_OFFSET

#define RADEON_INDEX_PRIM_OFFSET   20

◆ RADEON_INFO_ACCEL_WORKING

#define RADEON_INFO_ACCEL_WORKING   0x03

◆ RADEON_INFO_ACCEL_WORKING2

#define RADEON_INFO_ACCEL_WORKING2   0x05

◆ RADEON_INFO_ACTIVE_CU_COUNT

#define RADEON_INFO_ACTIVE_CU_COUNT   0x20

◆ RADEON_INFO_BACKEND_MAP

#define RADEON_INFO_BACKEND_MAP   0x0d /* pipe to backend map, needed by mesa */

◆ RADEON_INFO_CIK_MACROTILE_MODE_ARRAY

#define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY   0x18

◆ RADEON_INFO_CLOCK_CRYSTAL_FREQ

#define RADEON_INFO_CLOCK_CRYSTAL_FREQ   0x09 /* clock crystal frequency */

◆ RADEON_INFO_CRTC_FROM_ID

#define RADEON_INFO_CRTC_FROM_ID   0x04

◆ RADEON_INFO_CURRENT_GPU_MCLK

#define RADEON_INFO_CURRENT_GPU_MCLK   0x23

◆ RADEON_INFO_CURRENT_GPU_SCLK

#define RADEON_INFO_CURRENT_GPU_SCLK   0x22

◆ RADEON_INFO_CURRENT_GPU_TEMP

#define RADEON_INFO_CURRENT_GPU_TEMP   0x21

◆ RADEON_INFO_DEVICE_ID

#define RADEON_INFO_DEVICE_ID   0x00

◆ RADEON_INFO_FASTFB_WORKING

#define RADEON_INFO_FASTFB_WORKING   0x14

◆ RADEON_INFO_FUSION_GART_WORKING

#define RADEON_INFO_FUSION_GART_WORKING   0x0c /* fusion writes to GTT were broken before this */

◆ RADEON_INFO_GPU_RESET_COUNTER

#define RADEON_INFO_GPU_RESET_COUNTER   0x26

◆ RADEON_INFO_GTT_USAGE

#define RADEON_INFO_GTT_USAGE   0x1f

◆ RADEON_INFO_IB_VM_MAX_SIZE

#define RADEON_INFO_IB_VM_MAX_SIZE   0x0f

◆ RADEON_INFO_MAX_PIPES

#define RADEON_INFO_MAX_PIPES   0x10

◆ RADEON_INFO_MAX_SCLK

#define RADEON_INFO_MAX_SCLK   0x1a

◆ RADEON_INFO_MAX_SE

#define RADEON_INFO_MAX_SE   0x12

◆ RADEON_INFO_MAX_SH_PER_SE

#define RADEON_INFO_MAX_SH_PER_SE   0x13

◆ RADEON_INFO_NUM_BACKENDS

#define RADEON_INFO_NUM_BACKENDS   0x0a /* DB/backends for r600+ - need for OQ */

◆ RADEON_INFO_NUM_BYTES_MOVED

#define RADEON_INFO_NUM_BYTES_MOVED   0x1d

◆ RADEON_INFO_NUM_GB_PIPES

#define RADEON_INFO_NUM_GB_PIPES   0x01

◆ RADEON_INFO_NUM_TILE_PIPES

#define RADEON_INFO_NUM_TILE_PIPES   0x0b /* tile pipes for r600+ */

◆ RADEON_INFO_NUM_Z_PIPES

#define RADEON_INFO_NUM_Z_PIPES   0x02

◆ RADEON_INFO_READ_REG

#define RADEON_INFO_READ_REG   0x24

◆ RADEON_INFO_RING_WORKING

#define RADEON_INFO_RING_WORKING   0x15

◆ RADEON_INFO_SI_BACKEND_ENABLED_MASK

#define RADEON_INFO_SI_BACKEND_ENABLED_MASK   0x19

◆ RADEON_INFO_SI_CP_DMA_COMPUTE

#define RADEON_INFO_SI_CP_DMA_COMPUTE   0x17

◆ RADEON_INFO_SI_TILE_MODE_ARRAY

#define RADEON_INFO_SI_TILE_MODE_ARRAY   0x16

◆ RADEON_INFO_TILING_CONFIG

#define RADEON_INFO_TILING_CONFIG   0x06

◆ RADEON_INFO_TIMESTAMP

#define RADEON_INFO_TIMESTAMP   0x11

◆ RADEON_INFO_VA_START

#define RADEON_INFO_VA_START   0x0e

◆ RADEON_INFO_VA_UNMAP_WORKING

#define RADEON_INFO_VA_UNMAP_WORKING   0x25

◆ RADEON_INFO_VCE_FB_VERSION

#define RADEON_INFO_VCE_FB_VERSION   0x1c

◆ RADEON_INFO_VCE_FW_VERSION

#define RADEON_INFO_VCE_FW_VERSION   0x1b

◆ RADEON_INFO_VRAM_USAGE

#define RADEON_INFO_VRAM_USAGE   0x1e

◆ RADEON_INFO_WANT_CMASK

#define RADEON_INFO_WANT_CMASK   0x08 /* get access to CMASK on r300 */

◆ RADEON_INFO_WANT_HYPERZ

#define RADEON_INFO_WANT_HYPERZ   0x07

◆ RADEON_LINE_STRIP

#define RADEON_LINE_STRIP   0x3

◆ RADEON_LINES

#define RADEON_LINES   0x2

◆ RADEON_LOCAL_TEX_HEAP

#define RADEON_LOCAL_TEX_HEAP   0

◆ RADEON_LOG_TEX_GRANULARITY

#define RADEON_LOG_TEX_GRANULARITY   16

◆ RADEON_MAX_STATE_PACKETS

#define RADEON_MAX_STATE_PACKETS   95

◆ RADEON_MAX_SURFACES

#define RADEON_MAX_SURFACES   8

◆ RADEON_MAX_TEXTURE_LEVELS

#define RADEON_MAX_TEXTURE_LEVELS   12

◆ RADEON_MAX_TEXTURE_UNITS

#define RADEON_MAX_TEXTURE_UNITS   3

◆ RADEON_MEM_REGION_FB

#define RADEON_MEM_REGION_FB   2

◆ RADEON_MEM_REGION_GART

#define RADEON_MEM_REGION_GART   1

◆ RADEON_NR_SAREA_CLIPRECTS

#define RADEON_NR_SAREA_CLIPRECTS   12

◆ RADEON_NR_TEX_HEAPS

#define RADEON_NR_TEX_HEAPS   2

◆ RADEON_NR_TEX_REGIONS

#define RADEON_NR_TEX_REGIONS   64

◆ RADEON_OFFSET_ALIGN

#define RADEON_OFFSET_ALIGN   (1 << RADEON_OFFSET_SHIFT)

◆ RADEON_OFFSET_MASK

#define RADEON_OFFSET_MASK   (RADEON_OFFSET_ALIGN - 1)

◆ RADEON_OFFSET_SHIFT

#define RADEON_OFFSET_SHIFT   10

◆ RADEON_PARAM_CARD_TYPE

#define RADEON_PARAM_CARD_TYPE   12

◆ RADEON_PARAM_DEVICE_ID

#define RADEON_PARAM_DEVICE_ID   16

◆ RADEON_PARAM_FB_LOCATION

#define RADEON_PARAM_FB_LOCATION   14 /* FB location */

◆ RADEON_PARAM_GART_BASE

#define RADEON_PARAM_GART_BASE   6 /* card offset of GART base */

◆ RADEON_PARAM_GART_BUFFER_OFFSET

#define RADEON_PARAM_GART_BUFFER_OFFSET   1 /* card offset of 1st GART buffer */

◆ RADEON_PARAM_GART_TEX_HANDLE

#define RADEON_PARAM_GART_TEX_HANDLE   10

◆ RADEON_PARAM_IRQ_NR

#define RADEON_PARAM_IRQ_NR   5

◆ RADEON_PARAM_LAST_CLEAR

#define RADEON_PARAM_LAST_CLEAR   4

◆ RADEON_PARAM_LAST_DISPATCH

#define RADEON_PARAM_LAST_DISPATCH   3

◆ RADEON_PARAM_LAST_FRAME

#define RADEON_PARAM_LAST_FRAME   2

◆ RADEON_PARAM_NUM_GB_PIPES

#define RADEON_PARAM_NUM_GB_PIPES   15 /* num GB pipes */

◆ RADEON_PARAM_NUM_Z_PIPES

#define RADEON_PARAM_NUM_Z_PIPES   17 /* num Z pipes */

◆ RADEON_PARAM_REGISTER_HANDLE

#define RADEON_PARAM_REGISTER_HANDLE   7 /* for drmMap() */

◆ RADEON_PARAM_SAREA_HANDLE

#define RADEON_PARAM_SAREA_HANDLE   9

◆ RADEON_PARAM_SCRATCH_OFFSET

#define RADEON_PARAM_SCRATCH_OFFSET   11

◆ RADEON_PARAM_STATUS_HANDLE

#define RADEON_PARAM_STATUS_HANDLE   8

◆ RADEON_PARAM_VBLANK_CRTC

#define RADEON_PARAM_VBLANK_CRTC   13 /* VBLANK CRTC */

◆ RADEON_POINTS

#define RADEON_POINTS   0x1

◆ RADEON_RELOC_PRIO_MASK

#define RADEON_RELOC_PRIO_MASK   (0xf << 0)

◆ RADEON_REQUIRE_QUIESCENCE

#define RADEON_REQUIRE_QUIESCENCE   0x00010000

◆ RADEON_SCRATCH_REG_OFFSET

#define RADEON_SCRATCH_REG_OFFSET   32

◆ RADEON_SETPARAM_FB_LOCATION

#define RADEON_SETPARAM_FB_LOCATION   1 /* determined framebuffer location */

◆ RADEON_SETPARAM_NEW_MEMMAP

#define RADEON_SETPARAM_NEW_MEMMAP   4 /* Use new memory map */

◆ RADEON_SETPARAM_PCIGART_LOCATION

#define RADEON_SETPARAM_PCIGART_LOCATION   3 /* PCI Gart Location */

◆ RADEON_SETPARAM_PCIGART_TABLE_SIZE

#define RADEON_SETPARAM_PCIGART_TABLE_SIZE   5 /* PCI GART Table Size */

◆ RADEON_SETPARAM_SWITCH_TILING

#define RADEON_SETPARAM_SWITCH_TILING   2 /* enable/disable color tiling */

◆ RADEON_SETPARAM_VBLANK_CRTC

#define RADEON_SETPARAM_VBLANK_CRTC   6 /* VBLANK CRTC */

◆ RADEON_STENCIL

#define RADEON_STENCIL   0x8

◆ RADEON_TILING_EG_BANKH_MASK

#define RADEON_TILING_EG_BANKH_MASK   0xf

◆ RADEON_TILING_EG_BANKH_SHIFT

#define RADEON_TILING_EG_BANKH_SHIFT   12

◆ RADEON_TILING_EG_BANKW_MASK

#define RADEON_TILING_EG_BANKW_MASK   0xf

◆ RADEON_TILING_EG_BANKW_SHIFT

#define RADEON_TILING_EG_BANKW_SHIFT   8

◆ RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK

#define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK   0xf

◆ RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT

#define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT   16

◆ RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK

#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK   0xf

◆ RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT

#define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT   28

◆ RADEON_TILING_EG_TILE_SPLIT_MASK

#define RADEON_TILING_EG_TILE_SPLIT_MASK   0xf

◆ RADEON_TILING_EG_TILE_SPLIT_SHIFT

#define RADEON_TILING_EG_TILE_SPLIT_SHIFT   24

◆ RADEON_TILING_MACRO

#define RADEON_TILING_MACRO   0x1

◆ RADEON_TILING_MICRO

#define RADEON_TILING_MICRO   0x2

◆ RADEON_TILING_MICRO_SQUARE

#define RADEON_TILING_MICRO_SQUARE   0x20

◆ RADEON_TILING_SURFACE

#define RADEON_TILING_SURFACE   0x10

◆ RADEON_TILING_SWAP_16BIT

#define RADEON_TILING_SWAP_16BIT   0x4

◆ RADEON_TILING_SWAP_32BIT

#define RADEON_TILING_SWAP_32BIT   0x8

◆ RADEON_TRIANGLE_FAN

#define RADEON_TRIANGLE_FAN   0x5

◆ RADEON_TRIANGLE_STRIP

#define RADEON_TRIANGLE_STRIP   0x6

◆ RADEON_TRIANGLES

#define RADEON_TRIANGLES   0x4

◆ RADEON_UPLOAD_ALL

#define RADEON_UPLOAD_ALL   0x003effff

◆ RADEON_UPLOAD_BUMPMAP

#define RADEON_UPLOAD_BUMPMAP   0x00000008

◆ RADEON_UPLOAD_CLIPRECTS

#define RADEON_UPLOAD_CLIPRECTS   0x00008000 /* handled client-side */

◆ RADEON_UPLOAD_CONTEXT

#define RADEON_UPLOAD_CONTEXT   0x00000001

◆ RADEON_UPLOAD_CONTEXT_ALL

#define RADEON_UPLOAD_CONTEXT_ALL   0x003e01ff

◆ RADEON_UPLOAD_LINE

#define RADEON_UPLOAD_LINE   0x00000004

◆ RADEON_UPLOAD_MASKS

#define RADEON_UPLOAD_MASKS   0x00000010

◆ RADEON_UPLOAD_MISC

#define RADEON_UPLOAD_MISC   0x00000100

◆ RADEON_UPLOAD_SETUP

#define RADEON_UPLOAD_SETUP   0x00000040

◆ RADEON_UPLOAD_TCL

#define RADEON_UPLOAD_TCL   0x00000080

◆ RADEON_UPLOAD_TEX0

#define RADEON_UPLOAD_TEX0   0x00000200

◆ RADEON_UPLOAD_TEX0IMAGES

#define RADEON_UPLOAD_TEX0IMAGES   0x00001000

◆ RADEON_UPLOAD_TEX1

#define RADEON_UPLOAD_TEX1   0x00000400

◆ RADEON_UPLOAD_TEX1IMAGES

#define RADEON_UPLOAD_TEX1IMAGES   0x00002000

◆ RADEON_UPLOAD_TEX2

#define RADEON_UPLOAD_TEX2   0x00000800

◆ RADEON_UPLOAD_TEX2IMAGES

#define RADEON_UPLOAD_TEX2IMAGES   0x00004000

◆ RADEON_UPLOAD_VERTFMT

#define RADEON_UPLOAD_VERTFMT   0x00000002

◆ RADEON_UPLOAD_VIEWPORT

#define RADEON_UPLOAD_VIEWPORT   0x00000020

◆ RADEON_UPLOAD_ZBIAS

#define RADEON_UPLOAD_ZBIAS   0x00020000 /* version 1.2 and newer */

◆ RADEON_USE_COMP_ZBUF

#define RADEON_USE_COMP_ZBUF   0x20000000

◆ RADEON_USE_HIERZ

#define RADEON_USE_HIERZ   0x40000000

◆ RADEON_VA_MAP

#define RADEON_VA_MAP   1

◆ RADEON_VA_RESULT_ERROR

#define RADEON_VA_RESULT_ERROR   1

◆ RADEON_VA_RESULT_OK

#define RADEON_VA_RESULT_OK   0

◆ RADEON_VA_RESULT_VA_EXIST

#define RADEON_VA_RESULT_VA_EXIST   2

◆ RADEON_VA_UNMAP

#define RADEON_VA_UNMAP   2

◆ RADEON_VM_PAGE_READABLE

#define RADEON_VM_PAGE_READABLE   (1 << 1)

◆ RADEON_VM_PAGE_SNOOPED

#define RADEON_VM_PAGE_SNOOPED   (1 << 4)

◆ RADEON_VM_PAGE_SYSTEM

#define RADEON_VM_PAGE_SYSTEM   (1 << 3)

◆ RADEON_VM_PAGE_VALID

#define RADEON_VM_PAGE_VALID   (1 << 0)

◆ RADEON_VM_PAGE_WRITEABLE

#define RADEON_VM_PAGE_WRITEABLE   (1 << 2)

◆ RADEON_WAIT_2D

#define RADEON_WAIT_2D   0x1

◆ RADEON_WAIT_3D

#define RADEON_WAIT_3D   0x2

◆ SI_TILE_MODE_COLOR_1D

#define SI_TILE_MODE_COLOR_1D   13

◆ SI_TILE_MODE_COLOR_1D_SCANOUT

#define SI_TILE_MODE_COLOR_1D_SCANOUT   9

◆ SI_TILE_MODE_COLOR_2D_16BPP

#define SI_TILE_MODE_COLOR_2D_16BPP   15

◆ SI_TILE_MODE_COLOR_2D_32BPP

#define SI_TILE_MODE_COLOR_2D_32BPP   16

◆ SI_TILE_MODE_COLOR_2D_64BPP

#define SI_TILE_MODE_COLOR_2D_64BPP   17

◆ SI_TILE_MODE_COLOR_2D_8BPP

#define SI_TILE_MODE_COLOR_2D_8BPP   14

◆ SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP

#define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP   11

◆ SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP

#define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP   12

◆ SI_TILE_MODE_COLOR_LINEAR_ALIGNED

#define SI_TILE_MODE_COLOR_LINEAR_ALIGNED   8

◆ SI_TILE_MODE_DEPTH_STENCIL_1D

#define SI_TILE_MODE_DEPTH_STENCIL_1D   4

◆ SI_TILE_MODE_DEPTH_STENCIL_2D

#define SI_TILE_MODE_DEPTH_STENCIL_2D   0

◆ SI_TILE_MODE_DEPTH_STENCIL_2D_2AA

#define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA   3

◆ SI_TILE_MODE_DEPTH_STENCIL_2D_4AA

#define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA   3

◆ SI_TILE_MODE_DEPTH_STENCIL_2D_8AA

#define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA   2

Typedef Documentation

◆ drm_radeon_clear_rect_t

typedef union drm_radeon_clear_rect drm_radeon_clear_rect_t

◆ drm_radeon_clear_t

typedef struct drm_radeon_clear drm_radeon_clear_t

◆ drm_radeon_cmd_buffer_t

typedef struct drm_radeon_cmd_buffer drm_radeon_cmd_buffer_t

◆ drm_radeon_cp_stop_t

typedef struct drm_radeon_cp_stop drm_radeon_cp_stop_t

◆ drm_radeon_fullscreen_t

typedef struct drm_radeon_fullscreen drm_radeon_fullscreen_t

◆ drm_radeon_getparam_t

typedef struct drm_radeon_getparam drm_radeon_getparam_t

◆ drm_radeon_indices_t

typedef struct drm_radeon_indices drm_radeon_indices_t

◆ drm_radeon_indirect_t

typedef struct drm_radeon_indirect drm_radeon_indirect_t

◆ drm_radeon_init_t

typedef struct drm_radeon_init drm_radeon_init_t

◆ drm_radeon_irq_emit_t

typedef struct drm_radeon_irq_emit drm_radeon_irq_emit_t

◆ drm_radeon_irq_wait_t

typedef struct drm_radeon_irq_wait drm_radeon_irq_wait_t

◆ drm_radeon_mem_alloc_t

typedef struct drm_radeon_mem_alloc drm_radeon_mem_alloc_t

◆ drm_radeon_mem_free_t

typedef struct drm_radeon_mem_free drm_radeon_mem_free_t

◆ drm_radeon_mem_init_heap_t

typedef struct drm_radeon_mem_init_heap drm_radeon_mem_init_heap_t

◆ drm_radeon_setparam_t

typedef struct drm_radeon_setparam drm_radeon_setparam_t

◆ drm_radeon_stipple_t

typedef struct drm_radeon_stipple drm_radeon_stipple_t

◆ drm_radeon_surface_alloc_t

typedef struct drm_radeon_surface_alloc drm_radeon_surface_alloc_t

◆ drm_radeon_surface_free_t

typedef struct drm_radeon_surface_free drm_radeon_surface_free_t

◆ drm_radeon_tex_image_t

typedef struct drm_radeon_tex_image drm_radeon_tex_image_t

◆ drm_radeon_texture_t

typedef struct drm_radeon_texture drm_radeon_texture_t

◆ drm_radeon_vertex2_t

typedef struct drm_radeon_vertex2 drm_radeon_vertex2_t

◆ drm_radeon_vertex_t

typedef struct drm_radeon_vertex drm_radeon_vertex_t
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