SPD_LPDDR_BASE_SECTION Struct Reference

#include <SdramSpdLpDdr.h>

Collaboration diagram for SPD_LPDDR_BASE_SECTION:

Public Attributes
SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT	Description
	0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
SPD_LPDDR_REVISION_STRUCT	Revision
	1 SPD Revision
SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT	DramDeviceType
	2 DRAM Device Type
SPD_LPDDR_MODULE_TYPE_STRUCT	ModuleType
	3 Module Type
SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT	SdramDensityAndBanks
	4 SDRAM Density and Banks
SPD_LPDDR_SDRAM_ADDRESSING_STRUCT	SdramAddressing
	5 SDRAM Addressing
SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT	SdramPackageType
	6 SDRAM Package Type
SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT	SdramOptionalFeatures
	7 SDRAM Optional Features
SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT	ThermalAndRefreshOptions
	8 SDRAM Thermal and Refresh Options
SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT	OtherOptionalFeatures
	9 Other SDRAM Optional Features
UINT8	Reserved0
	10 Reserved
SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT	ModuleNominalVoltage
	11 Module Nominal Voltage, VDD
SPD_LPDDR_MODULE_ORGANIZATION_STRUCT	ModuleOrganization
	12 Module Organization
SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT	ModuleMemoryBusWidth
	13 Module Memory Bus Width
SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT	ModuleThermalSensor
	14 Module Thermal Sensor
SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT	ExtendedModuleType
	15 Extended Module Type
SPD_LPDDR_SIGNAL_LOADING_STRUCT	SignalLoading
	16 Signal Loading
SPD_LPDDR_TIMEBASE_STRUCT	Timebase
	17 Timebases
SPD_LPDDR_TCK_MIN_MTB_STRUCT	tCKmin
	18 SDRAM Minimum Cycle Time (tCKmin)
SPD_LPDDR_TCK_MAX_MTB_STRUCT	tCKmax
	19 SDRAM Maximum Cycle Time (tCKmax)
SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT	CasLatencies
	20-23 CAS Latencies Supported
SPD_LPDDR_TAA_MIN_MTB_STRUCT	tAAmin
	24 Minimum CAS Latency Time (tAAmin)
SPD_LPDDR_RW_LATENCY_OPTION_STRUCT	LatencySetOptions
	25 Read and Write Latency Set Options
SPD_LPDDR_TRCD_MIN_MTB_STRUCT	tRCDmin
	26 Minimum RAS# to CAS# Delay Time (tRCDmin)
SPD_LPDDR_TRP_AB_MTB_STRUCT	tRPab
	27 Minimum Row Precharge Delay Time (tRPab), all banks
SPD_LPDDR_TRP_PB_MTB_STRUCT	tRPpb
	28 Minimum Row Precharge Delay Time (tRPpb), per bank
SPD_LPDDR_TRFC_AB_MTB_STRUCT	tRFCab
	29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks
SPD_LPDDR_TRFC_PB_MTB_STRUCT	tRFCpb
	31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank
UINT8	Reserved1 [59 - 33+1]
	33-59 Reserved
SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT	BitMapping [77 - 60+1]
	60-77 Connector to SDRAM Bit Mapping
UINT8	Reserved2 [119 - 78+1]
	78-119 Reserved
SPD_LPDDR_TRP_PB_FTB_STRUCT	tRPpbFine
	120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank
SPD_LPDDR_TRP_AB_FTB_STRUCT	tRPabFine
	121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks
SPD_LPDDR_TRCD_MIN_FTB_STRUCT	tRCDminFine
	122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
SPD_LPDDR_TAA_MIN_FTB_STRUCT	tAAminFine
	123 Fine Offset for Minimum CAS Latency Time (tAAmin)
SPD_LPDDR_TCK_MAX_FTB_STRUCT	tCKmaxFine
	124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax)
SPD_LPDDR_TCK_MIN_FTB_STRUCT	tCKminFine
	125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)
SPD_LPDDR_CYCLIC_REDUNDANCY_CODE	Crc
	126-127 Cyclical Redundancy Code (CRC)

Member Data Documentation

BitMapping

SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT SPD_LPDDR_BASE_SECTION::BitMapping[77 - 60+1]

60-77 Connector to SDRAM Bit Mapping

CasLatencies

SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT SPD_LPDDR_BASE_SECTION::CasLatencies

20-23 CAS Latencies Supported

Crc

SPD_LPDDR_CYCLIC_REDUNDANCY_CODE SPD_LPDDR_BASE_SECTION::Crc

126-127 Cyclical Redundancy Code (CRC)

Description

SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT SPD_LPDDR_BASE_SECTION::Description

0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2

DramDeviceType

SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT SPD_LPDDR_BASE_SECTION::DramDeviceType

2 DRAM Device Type

ExtendedModuleType

SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT SPD_LPDDR_BASE_SECTION::ExtendedModuleType

15 Extended Module Type

LatencySetOptions

SPD_LPDDR_RW_LATENCY_OPTION_STRUCT SPD_LPDDR_BASE_SECTION::LatencySetOptions

25 Read and Write Latency Set Options

ModuleMemoryBusWidth

SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT SPD_LPDDR_BASE_SECTION::ModuleMemoryBusWidth

13 Module Memory Bus Width

ModuleNominalVoltage

SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT SPD_LPDDR_BASE_SECTION::ModuleNominalVoltage

11 Module Nominal Voltage, VDD

ModuleOrganization

SPD_LPDDR_MODULE_ORGANIZATION_STRUCT SPD_LPDDR_BASE_SECTION::ModuleOrganization

12 Module Organization

ModuleThermalSensor

SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT SPD_LPDDR_BASE_SECTION::ModuleThermalSensor

14 Module Thermal Sensor

ModuleType

SPD_LPDDR_MODULE_TYPE_STRUCT SPD_LPDDR_BASE_SECTION::ModuleType

3 Module Type

OtherOptionalFeatures

SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT SPD_LPDDR_BASE_SECTION::OtherOptionalFeatures

9 Other SDRAM Optional Features

Reserved0

UINT8 SPD_LPDDR_BASE_SECTION::Reserved0

10 Reserved

Reserved1

UINT8 SPD_LPDDR_BASE_SECTION::Reserved1[59 - 33+1]

33-59 Reserved

Reserved2

UINT8 SPD_LPDDR_BASE_SECTION::Reserved2[119 - 78+1]

78-119 Reserved

Revision

SPD_LPDDR_REVISION_STRUCT SPD_LPDDR_BASE_SECTION::Revision

1 SPD Revision

SdramAddressing

SPD_LPDDR_SDRAM_ADDRESSING_STRUCT SPD_LPDDR_BASE_SECTION::SdramAddressing

5 SDRAM Addressing

SdramDensityAndBanks

SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SPD_LPDDR_BASE_SECTION::SdramDensityAndBanks

4 SDRAM Density and Banks

SdramOptionalFeatures

SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SPD_LPDDR_BASE_SECTION::SdramOptionalFeatures

7 SDRAM Optional Features

SdramPackageType

SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SPD_LPDDR_BASE_SECTION::SdramPackageType

6 SDRAM Package Type

SignalLoading

SPD_LPDDR_SIGNAL_LOADING_STRUCT SPD_LPDDR_BASE_SECTION::SignalLoading

16 Signal Loading

tAAmin

SPD_LPDDR_TAA_MIN_MTB_STRUCT SPD_LPDDR_BASE_SECTION::tAAmin

24 Minimum CAS Latency Time (tAAmin)

tAAminFine

SPD_LPDDR_TAA_MIN_FTB_STRUCT SPD_LPDDR_BASE_SECTION::tAAminFine

123 Fine Offset for Minimum CAS Latency Time (tAAmin)

tCKmax

SPD_LPDDR_TCK_MAX_MTB_STRUCT SPD_LPDDR_BASE_SECTION::tCKmax

19 SDRAM Maximum Cycle Time (tCKmax)

tCKmaxFine

SPD_LPDDR_TCK_MAX_FTB_STRUCT SPD_LPDDR_BASE_SECTION::tCKmaxFine

124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax)

tCKmin

SPD_LPDDR_TCK_MIN_MTB_STRUCT SPD_LPDDR_BASE_SECTION::tCKmin

18 SDRAM Minimum Cycle Time (tCKmin)

tCKminFine

SPD_LPDDR_TCK_MIN_FTB_STRUCT SPD_LPDDR_BASE_SECTION::tCKminFine

125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)

ThermalAndRefreshOptions

SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT SPD_LPDDR_BASE_SECTION::ThermalAndRefreshOptions

8 SDRAM Thermal and Refresh Options

Timebase

SPD_LPDDR_TIMEBASE_STRUCT SPD_LPDDR_BASE_SECTION::Timebase

17 Timebases

tRCDmin

SPD_LPDDR_TRCD_MIN_MTB_STRUCT SPD_LPDDR_BASE_SECTION::tRCDmin

26 Minimum RAS# to CAS# Delay Time (tRCDmin)

tRCDminFine

SPD_LPDDR_TRCD_MIN_FTB_STRUCT SPD_LPDDR_BASE_SECTION::tRCDminFine

122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)

tRFCab

SPD_LPDDR_TRFC_AB_MTB_STRUCT SPD_LPDDR_BASE_SECTION::tRFCab

29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks

tRFCpb

SPD_LPDDR_TRFC_PB_MTB_STRUCT SPD_LPDDR_BASE_SECTION::tRFCpb

31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank

tRPab

SPD_LPDDR_TRP_AB_MTB_STRUCT SPD_LPDDR_BASE_SECTION::tRPab

27 Minimum Row Precharge Delay Time (tRPab), all banks

tRPabFine

SPD_LPDDR_TRP_AB_FTB_STRUCT SPD_LPDDR_BASE_SECTION::tRPabFine

121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks

tRPpb

SPD_LPDDR_TRP_PB_MTB_STRUCT SPD_LPDDR_BASE_SECTION::tRPpb

28 Minimum Row Precharge Delay Time (tRPpb), per bank

tRPpbFine

SPD_LPDDR_TRP_PB_FTB_STRUCT SPD_LPDDR_BASE_SECTION::tRPpbFine

120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank

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The documentation for this struct was generated from the following file:

• XenevaOS/Boot/include/IndustryStandard/SdramSpdLpDdr.h