#include "drm.h"

Include dependency graph for vmwgfx_drm.h:

Classes
struct	drm_vmw_getparam_arg

struct	drm_vmw_context_arg

struct	drm_vmw_surface_create_req

struct	drm_vmw_surface_arg

struct	drm_vmw_size

union	drm_vmw_surface_create_arg

union	drm_vmw_surface_reference_arg

struct	drm_vmw_execbuf_arg

struct	drm_vmw_fence_rep

struct	drm_vmw_alloc_bo_req

struct	drm_vmw_bo_rep

union	drm_vmw_alloc_bo_arg

struct	drm_vmw_rect

struct	drm_vmw_control_stream_arg

struct	drm_vmw_cursor_bypass_arg

struct	drm_vmw_stream_arg

struct	drm_vmw_get_3d_cap_arg

struct	drm_vmw_fence_wait_arg

struct	drm_vmw_fence_signaled_arg

struct	drm_vmw_fence_arg

struct	drm_vmw_event_fence

struct	drm_vmw_fence_event_arg

struct	drm_vmw_present_arg

struct	drm_vmw_present_readback_arg

struct	drm_vmw_update_layout_arg

struct	drm_vmw_shader_create_arg

struct	drm_vmw_shader_arg

struct	drm_vmw_gb_surface_create_req

struct	drm_vmw_gb_surface_create_rep

union	drm_vmw_gb_surface_create_arg

struct	drm_vmw_gb_surface_ref_rep

union	drm_vmw_gb_surface_reference_arg

struct	drm_vmw_synccpu_arg

union	drm_vmw_extended_context_arg

struct	drm_vmw_handle_close_arg

struct	drm_vmw_gb_surface_create_ext_req

union	drm_vmw_gb_surface_create_ext_arg

struct	drm_vmw_gb_surface_ref_ext_rep

union	drm_vmw_gb_surface_reference_ext_arg

struct	drm_vmw_msg_arg

struct	drm_vmw_mksstat_add_arg

struct	drm_vmw_mksstat_remove_arg

Macros
#define	DRM_VMW_MAX_SURFACE_FACES 6

#define	DRM_VMW_MAX_MIP_LEVELS 24

#define	DRM_VMW_GET_PARAM 0

#define	DRM_VMW_ALLOC_DMABUF 1

#define	DRM_VMW_ALLOC_BO 1

#define	DRM_VMW_UNREF_DMABUF 2

#define	DRM_VMW_HANDLE_CLOSE 2

#define	DRM_VMW_CURSOR_BYPASS 3

#define	DRM_VMW_CONTROL_STREAM 4

#define	DRM_VMW_CLAIM_STREAM 5

#define	DRM_VMW_UNREF_STREAM 6

#define	DRM_VMW_CREATE_CONTEXT 7

#define	DRM_VMW_UNREF_CONTEXT 8

#define	DRM_VMW_CREATE_SURFACE 9

#define	DRM_VMW_UNREF_SURFACE 10

#define	DRM_VMW_REF_SURFACE 11

#define	DRM_VMW_EXECBUF 12

#define	DRM_VMW_GET_3D_CAP 13

#define	DRM_VMW_FENCE_WAIT 14

#define	DRM_VMW_FENCE_SIGNALED 15

#define	DRM_VMW_FENCE_UNREF 16

#define	DRM_VMW_FENCE_EVENT 17

#define	DRM_VMW_PRESENT 18

#define	DRM_VMW_PRESENT_READBACK 19

#define	DRM_VMW_UPDATE_LAYOUT 20

#define	DRM_VMW_CREATE_SHADER 21

#define	DRM_VMW_UNREF_SHADER 22

#define	DRM_VMW_GB_SURFACE_CREATE 23

#define	DRM_VMW_GB_SURFACE_REF 24

#define	DRM_VMW_SYNCCPU 25

#define	DRM_VMW_CREATE_EXTENDED_CONTEXT 26

#define	DRM_VMW_GB_SURFACE_CREATE_EXT 27

#define	DRM_VMW_GB_SURFACE_REF_EXT 28

#define	DRM_VMW_MSG 29

#define	DRM_VMW_MKSSTAT_RESET 30

#define	DRM_VMW_MKSSTAT_ADD 31

#define	DRM_VMW_MKSSTAT_REMOVE 32

#define	DRM_VMW_PARAM_NUM_STREAMS 0

#define	DRM_VMW_PARAM_NUM_FREE_STREAMS 1

#define	DRM_VMW_PARAM_3D 2

#define	DRM_VMW_PARAM_HW_CAPS 3

#define	DRM_VMW_PARAM_FIFO_CAPS 4

#define	DRM_VMW_PARAM_MAX_FB_SIZE 5

#define	DRM_VMW_PARAM_FIFO_HW_VERSION 6

#define	DRM_VMW_PARAM_MAX_SURF_MEMORY 7

#define	DRM_VMW_PARAM_3D_CAPS_SIZE 8

#define	DRM_VMW_PARAM_MAX_MOB_MEMORY 9

#define	DRM_VMW_PARAM_MAX_MOB_SIZE 10

#define	DRM_VMW_PARAM_SCREEN_TARGET 11

#define	DRM_VMW_PARAM_DX 12

#define	DRM_VMW_PARAM_HW_CAPS2 13

#define	DRM_VMW_PARAM_SM4_1 14

#define	DRM_VMW_PARAM_SM5 15

#define	DRM_VMW_PARAM_GL43 16

#define	DRM_VMW_PARAM_DEVICE_ID 17

#define	DRM_VMW_EXECBUF_VERSION 2

#define	DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0)

#define	DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1)

#define	drm_vmw_alloc_dmabuf_req drm_vmw_alloc_bo_req

#define	drm_vmw_dmabuf_rep drm_vmw_bo_rep

#define	drm_vmw_alloc_dmabuf_arg drm_vmw_alloc_bo_arg

#define	DRM_VMW_CURSOR_BYPASS_ALL (1 << 0)

#define	DRM_VMW_CURSOR_BYPASS_FLAGS (1)

#define	DRM_VMW_FENCE_FLAG_EXEC (1 << 0)

#define	DRM_VMW_FENCE_FLAG_QUERY (1 << 1)

#define	DRM_VMW_WAIT_OPTION_UNREF (1 << 0)

#define	DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000

#define	DRM_VMW_FE_FLAG_REQ_TIME (1 << 0)

#define	drm_vmw_unref_dmabuf_arg drm_vmw_handle_close_arg

Enumerations
enum	drm_vmw_handle_type { DRM_VMW_HANDLE_LEGACY = 0 , DRM_VMW_HANDLE_PRIME = 1 }

enum	drm_vmw_shader_type { drm_vmw_shader_type_vs = 0 , drm_vmw_shader_type_ps }

enum	drm_vmw_surface_flags { drm_vmw_surface_flag_shareable = (1 << 0) , drm_vmw_surface_flag_scanout = (1 << 1) , drm_vmw_surface_flag_create_buffer = (1 << 2) , drm_vmw_surface_flag_coherent = (1 << 3) }

enum	drm_vmw_synccpu_flags { drm_vmw_synccpu_read = (1 << 0) , drm_vmw_synccpu_write = (1 << 1) , drm_vmw_synccpu_dontblock = (1 << 2) , drm_vmw_synccpu_allow_cs = (1 << 3) }

enum	drm_vmw_synccpu_op { drm_vmw_synccpu_grab , drm_vmw_synccpu_release }

enum	drm_vmw_extended_context { drm_vmw_context_legacy , drm_vmw_context_dx }

enum	drm_vmw_surface_version { drm_vmw_gb_surface_v1 }

Macro Definition Documentation

◆ DRM_VMW_ALLOC_BO

#define DRM_VMW_ALLOC_BO 1

◆ DRM_VMW_ALLOC_DMABUF

#define DRM_VMW_ALLOC_DMABUF 1

◆ drm_vmw_alloc_dmabuf_arg

#define drm_vmw_alloc_dmabuf_arg drm_vmw_alloc_bo_arg

◆ drm_vmw_alloc_dmabuf_req

#define drm_vmw_alloc_dmabuf_req drm_vmw_alloc_bo_req

◆ DRM_VMW_CLAIM_STREAM

#define DRM_VMW_CLAIM_STREAM 5

◆ DRM_VMW_CONTROL_STREAM

#define DRM_VMW_CONTROL_STREAM 4

◆ DRM_VMW_CREATE_CONTEXT

#define DRM_VMW_CREATE_CONTEXT 7

◆ DRM_VMW_CREATE_EXTENDED_CONTEXT

#define DRM_VMW_CREATE_EXTENDED_CONTEXT 26

◆ DRM_VMW_CREATE_SHADER

#define DRM_VMW_CREATE_SHADER 21

◆ DRM_VMW_CREATE_SURFACE

#define DRM_VMW_CREATE_SURFACE 9

◆ DRM_VMW_CURSOR_BYPASS

#define DRM_VMW_CURSOR_BYPASS 3

◆ DRM_VMW_CURSOR_BYPASS_ALL

#define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0)

DRM_VMW_CURSOR_BYPASS - Give extra information about cursor bypass.

◆ DRM_VMW_CURSOR_BYPASS_FLAGS

#define DRM_VMW_CURSOR_BYPASS_FLAGS (1)

◆ drm_vmw_dmabuf_rep

#define drm_vmw_dmabuf_rep drm_vmw_bo_rep

◆ DRM_VMW_EVENT_FENCE_SIGNALED

#define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000

DRM_VMW_FENCE_EVENT

Queues an event on a fence to be delivered on the drm character device when the fence has signaled the DRM_VMW_FENCE_FLAG_EXEC flag. Optionally the approximate time when the fence signaled is given by the event.

◆ DRM_VMW_EXECBUF

#define DRM_VMW_EXECBUF 12

◆ DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD

#define DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1)

◆ DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD

#define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0)

◆ DRM_VMW_EXECBUF_VERSION

#define DRM_VMW_EXECBUF_VERSION 2

DRM_VMW_UNREF_SURFACE - Unreference a host surface.

Clear a reference previously put on a host surface. When all references are gone, including the one implicitly placed on creation, a destroy surface command will be queued for the host. Does not wait for completion. DRM_VMW_EXECBUF

Submit a command buffer for execution on the host, and return a fence seqno that when signaled, indicates that the command buffer has executed. struct drm_vmw_execbuf_arg

@commands: User-space address of a command buffer cast to an __u64. @command-size: Size in bytes of the command buffer. @throttle-us: Sleep until software is less than @throttle_us microseconds ahead of hardware. The driver may round this value to the nearest kernel tick. @fence_rep: User-space address of a struct drm_vmw_fence_rep cast to an __u64.

Version: : Allows expanding the execbuf ioctl parameters without breaking backwards compatibility, since user-space will always tell the kernel which version it uses. @flags: Execbuf flags. @imported_fence_fd: FD for a fence imported from another device

Argument to the DRM_VMW_EXECBUF Ioctl.

◆ DRM_VMW_FE_FLAG_REQ_TIME

#define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0)

◆ DRM_VMW_FENCE_EVENT

#define DRM_VMW_FENCE_EVENT 17

◆ DRM_VMW_FENCE_FLAG_EXEC

#define DRM_VMW_FENCE_FLAG_EXEC (1 << 0)

DRM_VMW_FENCE_WAIT

Waits for a fence object to signal. The wait is interruptible, so that signals may be delivered during the interrupt. The wait may timeout, in which case the calls returns -EBUSY. If the wait is restarted, that is restarting without resetting @cookie_valid to zero, the timeout is computed from the first call.

The flags argument to the DRM_VMW_FENCE_WAIT ioctl indicates what to wait on: DRM_VMW_FENCE_FLAG_EXEC: All commands ahead of the fence in the command stream have executed. DRM_VMW_FENCE_FLAG_QUERY: All query results resulting from query finish commands in the buffer given to the EXECBUF ioctl returning the fence object handle are available to user-space.

DRM_VMW_WAIT_OPTION_UNREF: If this wait option is given, and the fenc wait ioctl returns 0, the fence object has been unreferenced after the wait.

◆ DRM_VMW_FENCE_FLAG_QUERY

#define DRM_VMW_FENCE_FLAG_QUERY (1 << 1)

◆ DRM_VMW_FENCE_SIGNALED

#define DRM_VMW_FENCE_SIGNALED 15

◆ DRM_VMW_FENCE_UNREF

#define DRM_VMW_FENCE_UNREF 16

◆ DRM_VMW_FENCE_WAIT

#define DRM_VMW_FENCE_WAIT 14

◆ DRM_VMW_GB_SURFACE_CREATE

#define DRM_VMW_GB_SURFACE_CREATE 23

◆ DRM_VMW_GB_SURFACE_CREATE_EXT

#define DRM_VMW_GB_SURFACE_CREATE_EXT 27

◆ DRM_VMW_GB_SURFACE_REF

#define DRM_VMW_GB_SURFACE_REF 24

◆ DRM_VMW_GB_SURFACE_REF_EXT

#define DRM_VMW_GB_SURFACE_REF_EXT 28

◆ DRM_VMW_GET_3D_CAP

#define DRM_VMW_GET_3D_CAP 13

◆ DRM_VMW_GET_PARAM

#define DRM_VMW_GET_PARAM 0

◆ DRM_VMW_HANDLE_CLOSE

#define DRM_VMW_HANDLE_CLOSE 2

◆ DRM_VMW_MAX_MIP_LEVELS

#define DRM_VMW_MAX_MIP_LEVELS 24

◆ DRM_VMW_MAX_SURFACE_FACES

#define DRM_VMW_MAX_SURFACE_FACES 6

◆ DRM_VMW_MKSSTAT_ADD

#define DRM_VMW_MKSSTAT_ADD 31

◆ DRM_VMW_MKSSTAT_REMOVE

#define DRM_VMW_MKSSTAT_REMOVE 32

◆ DRM_VMW_MKSSTAT_RESET

#define DRM_VMW_MKSSTAT_RESET 30

◆ DRM_VMW_MSG

#define DRM_VMW_MSG 29

◆ DRM_VMW_PARAM_3D

#define DRM_VMW_PARAM_3D 2

◆ DRM_VMW_PARAM_3D_CAPS_SIZE

#define DRM_VMW_PARAM_3D_CAPS_SIZE 8

◆ DRM_VMW_PARAM_DEVICE_ID

#define DRM_VMW_PARAM_DEVICE_ID 17

◆ DRM_VMW_PARAM_DX

#define DRM_VMW_PARAM_DX 12

◆ DRM_VMW_PARAM_FIFO_CAPS

#define DRM_VMW_PARAM_FIFO_CAPS 4

◆ DRM_VMW_PARAM_FIFO_HW_VERSION

#define DRM_VMW_PARAM_FIFO_HW_VERSION 6

◆ DRM_VMW_PARAM_GL43

#define DRM_VMW_PARAM_GL43 16

◆ DRM_VMW_PARAM_HW_CAPS

#define DRM_VMW_PARAM_HW_CAPS 3

◆ DRM_VMW_PARAM_HW_CAPS2

#define DRM_VMW_PARAM_HW_CAPS2 13

◆ DRM_VMW_PARAM_MAX_FB_SIZE

#define DRM_VMW_PARAM_MAX_FB_SIZE 5

◆ DRM_VMW_PARAM_MAX_MOB_MEMORY

#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9

◆ DRM_VMW_PARAM_MAX_MOB_SIZE

#define DRM_VMW_PARAM_MAX_MOB_SIZE 10

◆ DRM_VMW_PARAM_MAX_SURF_MEMORY

#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7

◆ DRM_VMW_PARAM_NUM_FREE_STREAMS

#define DRM_VMW_PARAM_NUM_FREE_STREAMS 1

◆ DRM_VMW_PARAM_NUM_STREAMS

#define DRM_VMW_PARAM_NUM_STREAMS 0

DRM_VMW_GET_PARAM - get device information.

DRM_VMW_PARAM_FIFO_OFFSET: Offset to use to map the first page of the FIFO read-only. The fifo is mapped using the mmap() system call on the drm device.

DRM_VMW_PARAM_OVERLAY_IOCTL: Does the driver support the overlay ioctl.

DRM_VMW_PARAM_SM4_1 SM4_1 support is enabled.

DRM_VMW_PARAM_SM5 SM5 support is enabled.

DRM_VMW_PARAM_GL43 SM5.1+GL4.3 support is enabled.

DRM_VMW_PARAM_DEVICE_ID PCI ID of the underlying SVGA device.

◆ DRM_VMW_PARAM_SCREEN_TARGET

#define DRM_VMW_PARAM_SCREEN_TARGET 11

◆ DRM_VMW_PARAM_SM4_1

#define DRM_VMW_PARAM_SM4_1 14

◆ DRM_VMW_PARAM_SM5

#define DRM_VMW_PARAM_SM5 15

◆ DRM_VMW_PRESENT

#define DRM_VMW_PRESENT 18

◆ DRM_VMW_PRESENT_READBACK

#define DRM_VMW_PRESENT_READBACK 19

◆ DRM_VMW_REF_SURFACE

#define DRM_VMW_REF_SURFACE 11

◆ DRM_VMW_SYNCCPU

#define DRM_VMW_SYNCCPU 25

◆ DRM_VMW_UNREF_CONTEXT

#define DRM_VMW_UNREF_CONTEXT 8

◆ DRM_VMW_UNREF_DMABUF

#define DRM_VMW_UNREF_DMABUF 2

◆ drm_vmw_unref_dmabuf_arg

#define drm_vmw_unref_dmabuf_arg drm_vmw_handle_close_arg

◆ DRM_VMW_UNREF_SHADER

#define DRM_VMW_UNREF_SHADER 22

◆ DRM_VMW_UNREF_STREAM

#define DRM_VMW_UNREF_STREAM 6

◆ DRM_VMW_UNREF_SURFACE

#define DRM_VMW_UNREF_SURFACE 10

◆ DRM_VMW_UPDATE_LAYOUT

#define DRM_VMW_UPDATE_LAYOUT 20

◆ DRM_VMW_WAIT_OPTION_UNREF

#define DRM_VMW_WAIT_OPTION_UNREF (1 << 0)

Enumeration Type Documentation

◆ drm_vmw_extended_context

enum drm_vmw_extended_context

DRM_VMW_CREATE_EXTENDED_CONTEXT - Create a host context.

Allocates a device unique context id, and queues a create context command for the host. Does not wait for host completion.

Enumerator
drm_vmw_context_legacy
drm_vmw_context_dx

◆ drm_vmw_handle_type

enum drm_vmw_handle_type

enum drm_vmw_handle_type - handle type for ref ioctls

Enumerator
DRM_VMW_HANDLE_LEGACY
DRM_VMW_HANDLE_PRIME

◆ drm_vmw_shader_type

enum drm_vmw_shader_type

DRM_VMW_CREATE_SHADER - Create shader

Creates a shader and optionally binds it to a dma buffer containing the shader byte-code. enum drm_vmw_shader_type - Shader types

Enumerator
drm_vmw_shader_type_vs
drm_vmw_shader_type_ps

◆ drm_vmw_surface_flags

enum drm_vmw_surface_flags

DRM_VMW_GB_SURFACE_CREATE - Create a host guest-backed surface.

Allocates a surface handle and queues a create surface command for the host on the first use of the surface. The surface ID can be used as the surface ID in commands referencing the surface. enum drm_vmw_surface_flags

@drm_vmw_surface_flag_shareable: Deprecated - all userspace surfaces are shareable. @drm_vmw_surface_flag_scanout: Whether the surface is a scanout surface. @drm_vmw_surface_flag_create_buffer: Create a backup buffer if none is given. @drm_vmw_surface_flag_coherent: Back surface with coherent memory.

Enumerator
drm_vmw_surface_flag_shareable
drm_vmw_surface_flag_scanout
drm_vmw_surface_flag_create_buffer
drm_vmw_surface_flag_coherent

◆ drm_vmw_surface_version

enum drm_vmw_surface_version

DRM_VMW_GB_SURFACE_CREATE_EXT - Create a host guest-backed surface.

Allocates a surface handle and queues a create surface command for the host on the first use of the surface. The surface ID can be used as the surface ID in commands referencing the surface.

This new command extends DRM_VMW_GB_SURFACE_CREATE by adding version parameter and 64 bit svga flag. enum drm_vmw_surface_version

@drm_vmw_surface_gb_v1: Corresponds to current gb surface format with svga3d surface flags split into 2, upper half and lower half.

Enumerator
drm_vmw_gb_surface_v1

◆ drm_vmw_synccpu_flags

enum drm_vmw_synccpu_flags

DRM_VMW_SYNCCPU - Sync a DMA buffer / MOB for CPU access.

Idles any previously submitted GPU operations on the buffer and by default blocks command submissions that reference the buffer. If the file descriptor used to grab a blocking CPU sync is closed, the cpu sync is released. The flags argument indicates how the grab / release operation should be performed: enum drm_vmw_synccpu_flags - Synccpu flags:

@drm_vmw_synccpu_read: Sync for read. If sync is done for read only, it's a hint to the kernel to allow command submissions that references the buffer for read-only. @drm_vmw_synccpu_write: Sync for write. Block all command submissions referencing this buffer. @drm_vmw_synccpu_dontblock: Dont wait for GPU idle, but rather return -EBUSY should the buffer be busy. @drm_vmw_synccpu_allow_cs: Allow command submission that touches the buffer while the buffer is synced for CPU. This is similar to the GEM bo idle behavior.

Enumerator
drm_vmw_synccpu_read
drm_vmw_synccpu_write
drm_vmw_synccpu_dontblock
drm_vmw_synccpu_allow_cs

◆ drm_vmw_synccpu_op

enum drm_vmw_synccpu_op

enum drm_vmw_synccpu_op - Synccpu operations:

@drm_vmw_synccpu_grab: Grab the buffer for CPU operations @drm_vmw_synccpu_release: Release a previous grab.

Enumerator
drm_vmw_synccpu_grab
drm_vmw_synccpu_release

Classes

Macros

Enumerations