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| #define | _UAPILINUX_SERIAL_CORE_H |
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| #define | PORT_NS16550A 14 |
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| #define | PORT_XSCALE 15 |
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| #define | PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */ |
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| #define | PORT_OCTEON 17 /* Cavium OCTEON internal UART */ |
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| #define | PORT_AR7 18 /* Texas Instruments AR7 internal UART */ |
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| #define | PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */ |
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| #define | PORT_TEGRA 20 /* NVIDIA Tegra internal UART */ |
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| #define | PORT_XR17D15X 21 /* Exar XR17D15x UART */ |
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| #define | PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */ |
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| #define | PORT_8250_CIR 23 /* CIR infrared port, has its own driver */ |
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| #define | PORT_XR17V35X 24 /* Exar XR17V35x UARTs */ |
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| #define | PORT_BRCM_TRUMANAGE 25 |
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| #define | PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */ |
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| #define | PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */ |
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| #define | PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */ |
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| #define | PORT_RT2880 29 /* Ralink RT2880 internal UART */ |
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| #define | PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */ |
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| #define | PORT_PXA 31 |
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| #define | PORT_AMBA 32 |
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| #define | PORT_CLPS711X 33 |
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| #define | PORT_SA1100 34 |
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| #define | PORT_UART00 35 |
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| #define | PORT_OWL 36 |
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| #define | PORT_21285 37 |
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| #define | PORT_SUNZILOG 38 |
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| #define | PORT_SUNSAB 39 |
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| #define | PORT_NPCM 40 |
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| #define | PORT_TEGRA_TCU 41 |
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| #define | PORT_ASPEED_VUART 42 |
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| #define | PORT_PCH_8LINE 44 |
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| #define | PORT_PCH_2LINE 45 |
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| #define | PORT_DZ 46 |
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| #define | PORT_ZS 47 |
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| #define | PORT_MUX 48 |
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| #define | PORT_ATMEL 49 |
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| #define | PORT_MAC_ZILOG 50 /* m68k : not yet implemented */ |
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| #define | PORT_PMAC_ZILOG 51 |
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| #define | PORT_SCI 52 |
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| #define | PORT_SCIF 53 |
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| #define | PORT_IRDA 54 |
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| #define | PORT_IP22ZILOG 56 |
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| #define | PORT_CPM 58 |
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| #define | PORT_MPC52xx 59 |
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| #define | PORT_ICOM 60 |
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| #define | PORT_IMX 62 |
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| #define | PORT_TXX9 64 |
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| #define | PORT_JSM 69 |
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| #define | PORT_SUNHV 72 |
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| #define | PORT_UARTLITE 74 |
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| #define | PORT_BCM7271 76 |
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| #define | PORT_SB1250_DUART 77 |
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| #define | PORT_MCF 78 |
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| #define | PORT_SC26XX 82 |
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| #define | PORT_SCIFA 83 |
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| #define | PORT_S3C6400 84 |
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| #define | PORT_MAX3100 86 |
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| #define | PORT_TIMBUART 87 |
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| #define | PORT_MSM 88 |
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| #define | PORT_BCM63XX 89 |
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| #define | PORT_APBUART 90 |
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| #define | PORT_ALTERA_JTAGUART 91 |
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| #define | PORT_ALTERA_UART 92 |
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| #define | PORT_SCIFB 93 |
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| #define | PORT_MAX310X 94 |
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| #define | PORT_DA830 95 |
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| #define | PORT_OMAP 96 |
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| #define | PORT_VT8500 97 |
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| #define | PORT_XUARTPS 98 |
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| #define | PORT_AR933X 99 |
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| #define | PORT_MCHP16550A 100 |
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| #define | PORT_ARC 101 |
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| #define | PORT_RP2 102 |
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| #define | PORT_LPUART 103 |
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| #define | PORT_HSCIF 104 |
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| #define | PORT_ASC 105 |
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| #define | PORT_MEN_Z135 107 |
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| #define | PORT_SC16IS7XX 108 |
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| #define | PORT_MESON 109 |
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| #define | PORT_DIGICOLOR 110 |
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| #define | PORT_SPRD 111 |
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| #define | PORT_STM32 113 |
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| #define | PORT_MVEBU 114 |
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| #define | PORT_PIC32 115 |
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| #define | PORT_MPS2UART 116 |
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| #define | PORT_MTK_BTIF 117 |
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| #define | PORT_RDA 118 |
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| #define | PORT_MLB_USIO 119 |
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| #define | PORT_SIFIVE_V0 120 |
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| #define | PORT_SUNIX 121 |
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| #define | PORT_LINFLEXUART 122 |
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| #define | PORT_SUNPLUS 123 |
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| #define | PORT_GENERIC (-1) |
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| #define | uart_console(port) ({ (void)port; 0; }) |
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| #define | NO_POLL_CHAR 0x00ff0000 |
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| #define | UART_CONFIG_TYPE (1 << 0) |
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| #define | UART_CONFIG_IRQ (1 << 1) |
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| #define | UPQ_NO_TXEN_TEST BIT(0) |
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| #define | UPF_FOURPORT 0 |
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| #define | UPF_SAK ((__force upf_t) ASYNC_SAK /* 2 */ ) |
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| #define | UPF_SPD_HI ((__force upf_t) ASYNC_SPD_HI /* 4 */ ) |
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| #define | UPF_SPD_VHI ((__force upf_t) ASYNC_SPD_VHI /* 5 */ ) |
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| #define | UPF_SPD_CUST ((__force upf_t) ASYNC_SPD_CUST /* 0x0030 */ ) |
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| #define | UPF_SPD_WARP ((__force upf_t) ASYNC_SPD_WARP /* 0x1010 */ ) |
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| #define | UPF_SPD_MASK ((__force upf_t) ASYNC_SPD_MASK /* 0x1030 */ ) |
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| #define | UPF_SKIP_TEST ((__force upf_t) ASYNC_SKIP_TEST /* 6 */ ) |
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| #define | UPF_AUTO_IRQ ((__force upf_t) ASYNC_AUTO_IRQ /* 7 */ ) |
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| #define | UPF_HARDPPS_CD ((__force upf_t) ASYNC_HARDPPS_CD /* 11 */ ) |
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| #define | UPF_SPD_SHI ((__force upf_t) ASYNC_SPD_SHI /* 12 */ ) |
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| #define | UPF_LOW_LATENCY ((__force upf_t) ASYNC_LOW_LATENCY /* 13 */ ) |
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| #define | UPF_BUGGY_UART ((__force upf_t) ASYNC_BUGGY_UART /* 14 */ ) |
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| #define | UPF_MAGIC_MULTIPLIER ((__force upf_t) ASYNC_MAGIC_MULTIPLIER /* 16 */ ) |
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| #define | UPF_NO_THRE_TEST ((__force upf_t) BIT_ULL(19)) |
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| #define | UPF_AUTO_CTS ((__force upf_t) BIT_ULL(20)) |
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| #define | UPF_AUTO_RTS ((__force upf_t) BIT_ULL(21)) |
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| #define | UPF_HARD_FLOW ((__force upf_t) (UPF_AUTO_CTS | UPF_AUTO_RTS)) |
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| #define | UPF_SOFT_FLOW ((__force upf_t) BIT_ULL(22)) |
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| #define | UPF_CONS_FLOW ((__force upf_t) BIT_ULL(23)) |
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| #define | UPF_SHARE_IRQ ((__force upf_t) BIT_ULL(24)) |
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| #define | UPF_EXAR_EFR ((__force upf_t) BIT_ULL(25)) |
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| #define | UPF_BUG_THRE ((__force upf_t) BIT_ULL(26)) |
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| #define | UPF_FIXED_TYPE ((__force upf_t) BIT_ULL(27)) |
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| #define | UPF_BOOT_AUTOCONF ((__force upf_t) BIT_ULL(28)) |
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| #define | UPF_FIXED_PORT ((__force upf_t) BIT_ULL(29)) |
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| #define | UPF_DEAD ((__force upf_t) BIT_ULL(30)) |
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| #define | UPF_IOREMAP ((__force upf_t) BIT_ULL(31)) |
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| #define | UPF_FULL_PROBE ((__force upf_t) BIT_ULL(32)) |
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| #define | __UPF_CHANGE_MASK 0x17fff |
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| #define | UPF_CHANGE_MASK ((__force upf_t) __UPF_CHANGE_MASK) |
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| #define | UPF_USR_MASK ((__force upf_t) (UPF_SPD_MASK|UPF_LOW_LATENCY)) |
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| #define | UPSTAT_CTS_ENABLE ((__force upstat_t) (1 << 0)) |
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| #define | UPSTAT_DCD_ENABLE ((__force upstat_t) (1 << 1)) |
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| #define | UPSTAT_AUTORTS ((__force upstat_t) (1 << 2)) |
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| #define | UPSTAT_AUTOCTS ((__force upstat_t) (1 << 3)) |
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| #define | UPSTAT_AUTOXOFF ((__force upstat_t) (1 << 4)) |
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| #define | UPSTAT_SYNC_FIFO ((__force upstat_t) (1 << 5)) |
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| #define | UART_XMIT_SIZE PAGE_SIZE |
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| #define | WAKEUP_CHARS 256 |
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| #define | __uart_port_tx(uport, ch, flags, tx_ready, put_char, tx_done, for_test, for_post) |
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| #define | uart_port_tx_limited(port, ch, count, tx_ready, put_char, tx_done) |
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| #define | uart_port_tx_limited_flags(port, ch, flags, count, tx_ready, put_char, tx_done) |
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| #define | uart_port_tx(port, ch, tx_ready, put_char) __uart_port_tx(port, ch, 0, tx_ready, put_char, ({}), true, ({})) |
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| #define | uart_port_tx_flags(port, ch, flags, tx_ready, put_char) __uart_port_tx(port, ch, flags, tx_ready, put_char, ({}), true, ({})) |
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| #define | EARLYCON_USED_OR_UNUSED __maybe_unused |
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| #define | OF_EARLYCON_DECLARE(_name, compat, fn) |
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| #define | EARLYCON_DECLARE(_name, fn) OF_EARLYCON_DECLARE(_name, "", fn) |
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| #define | UART_ENABLE_MS(port, cflag) |
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| | DEFINE_GUARD (uart_port_lock, struct uart_port *, uart_port_lock(_T), uart_port_unlock(_T)) |
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| | DEFINE_GUARD (uart_port_lock_irq, struct uart_port *, uart_port_lock_irq(_T), uart_port_unlock_irq(_T)) |
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| | DEFINE_LOCK_GUARD_1 (uart_port_lock_irqsave, struct uart_port, uart_port_lock_irqsave(_T->lock, &_T->flags), uart_port_unlock_irqrestore(_T->lock, _T->flags), unsigned long flags) |
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| void | uart_write_wakeup (struct uart_port *port) |
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| void | uart_update_timeout (struct uart_port *port, unsigned int cflag, unsigned int baud) |
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| unsigned int | uart_get_baud_rate (struct uart_port *port, struct ktermios *termios, const struct ktermios *old, unsigned int min, unsigned int max) |
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| unsigned int | uart_get_divisor (struct uart_port *port, unsigned int baud) |
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| int | of_setup_earlycon (const struct earlycon_id *match, unsigned long node, const char *options) |
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| int | uart_parse_earlycon (char *p, enum uart_iotype *iotype, resource_size_t *addr, char **options) |
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| void | uart_parse_options (const char *options, int *baud, int *parity, int *bits, int *flow) |
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| int | uart_set_options (struct uart_port *port, struct console *co, int baud, int parity, int bits, int flow) |
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| struct tty_driver * | uart_console_device (struct console *co, int *index) |
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| void | uart_console_write (struct uart_port *port, const char *s, unsigned int count, void(*putchar)(struct uart_port *, unsigned char)) |
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| int | uart_register_driver (struct uart_driver *uart) |
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| void | uart_unregister_driver (struct uart_driver *uart) |
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| int | uart_add_one_port (struct uart_driver *reg, struct uart_port *port) |
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| void | uart_remove_one_port (struct uart_driver *reg, struct uart_port *port) |
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| int | uart_read_port_properties (struct uart_port *port) |
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| int | uart_read_and_validate_port_properties (struct uart_port *port) |
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| bool | uart_match_port (const struct uart_port *port1, const struct uart_port *port2) |
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| int | uart_suspend_port (struct uart_driver *reg, struct uart_port *port) |
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| int | uart_resume_port (struct uart_driver *reg, struct uart_port *port) |
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| void | uart_handle_dcd_change (struct uart_port *uport, bool active) |
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| void | uart_handle_cts_change (struct uart_port *uport, bool active) |
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| void | uart_insert_char (struct uart_port *port, unsigned int status, unsigned int overrun, u8 ch, u8 flag) |
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| void | uart_xchar_out (struct uart_port *uport, int offset) |
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| | DEFINE_LOCK_GUARD_1 (uart_port_lock_check_sysrq_irqsave, struct uart_port, uart_port_lock_irqsave(_T->lock, &_T->flags), uart_unlock_and_check_sysrq_irqrestore(_T->lock, _T->flags), unsigned long flags) |
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| int | uart_get_rs485_mode (struct uart_port *port) |
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| #define uart_port_tx_limited |
( |
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port, |
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ch, |
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count, |
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tx_ready, |
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put_char, |
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tx_done |
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) |
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Value: ({ \
unsigned int __count = (count); \
__uart_port_tx(port, ch, 0, tx_ready, put_char, tx_done, __count, \
__count--); \
})
uart_port_tx_limited – transmit helper for uart_port with count limiting @port: uart port @ch: variable to store a character to be written to the HW @count: a limit of characters to send @tx_ready: can HW accept more data function @put_char: function to write a character @tx_done: function to call after the loop is done
This helper transmits characters from the xmit buffer to the hardware using @put_char(). It does so until @count characters are sent and while @tx_ready evaluates to true.
Returns: the number of characters in the xmit buffer when done.
The expression in macro parameters shall be designed as follows:
- tx_ready: should evaluate to true if the HW can accept more data to be sent. This parameter can be true, which means the HW is always ready.
- put_char: shall write @ch to the device of @port.
- tx_done: when the write loop is done, this can perform arbitrary action before potential invocation of ops->stop_tx() happens. If the driver does not need to do anything, use e.g. ({}).
For all of them, @port->lock is held, interrupts are locally disabled and the expressions must not sleep.