#include "drm.h"

Include dependency graph for amdgpu_drm.h:

Classes
struct	drm_amdgpu_gem_create_in

struct	drm_amdgpu_gem_create_out

union	drm_amdgpu_gem_create

struct	drm_amdgpu_bo_list_in

struct	drm_amdgpu_bo_list_entry

struct	drm_amdgpu_bo_list_out

union	drm_amdgpu_bo_list

struct	drm_amdgpu_ctx_in

union	drm_amdgpu_ctx_out

union	drm_amdgpu_ctx

struct	drm_amdgpu_userq_in

struct	drm_amdgpu_userq_out

union	drm_amdgpu_userq

struct	drm_amdgpu_userq_mqd_gfx11

struct	drm_amdgpu_userq_mqd_sdma_gfx11

struct	drm_amdgpu_userq_mqd_compute_gfx11

struct	drm_amdgpu_userq_signal

struct	drm_amdgpu_userq_fence_info

struct	drm_amdgpu_userq_wait

struct	drm_amdgpu_vm_in

struct	drm_amdgpu_vm_out

union	drm_amdgpu_vm

struct	drm_amdgpu_sched_in

union	drm_amdgpu_sched

struct	drm_amdgpu_gem_userptr

struct	drm_amdgpu_gem_metadata

struct	drm_amdgpu_gem_mmap_in

struct	drm_amdgpu_gem_mmap_out

union	drm_amdgpu_gem_mmap

struct	drm_amdgpu_gem_wait_idle_in

struct	drm_amdgpu_gem_wait_idle_out

union	drm_amdgpu_gem_wait_idle

struct	drm_amdgpu_wait_cs_in

struct	drm_amdgpu_wait_cs_out

union	drm_amdgpu_wait_cs

struct	drm_amdgpu_fence

struct	drm_amdgpu_wait_fences_in

struct	drm_amdgpu_wait_fences_out

union	drm_amdgpu_wait_fences

struct	drm_amdgpu_gem_vm_entry

struct	drm_amdgpu_gem_op

struct	drm_amdgpu_gem_list_handles

struct	drm_amdgpu_gem_list_handles_entry

struct	drm_amdgpu_gem_va

struct	drm_amdgpu_cs_chunk

struct	drm_amdgpu_cs_in

struct	drm_amdgpu_cs_out

union	drm_amdgpu_cs

struct	drm_amdgpu_cs_chunk_ib

struct	drm_amdgpu_cs_chunk_dep

struct	drm_amdgpu_cs_chunk_fence

struct	drm_amdgpu_cs_chunk_sem

struct	drm_amdgpu_cs_chunk_syncobj

union	drm_amdgpu_fence_to_handle

struct	drm_amdgpu_cs_chunk_data

struct	drm_amdgpu_cs_chunk_cp_gfx_shadow

struct	drm_amdgpu_query_fw

struct	drm_amdgpu_info

struct	drm_amdgpu_info_gds

struct	drm_amdgpu_info_vram_gtt

struct	drm_amdgpu_heap_info

struct	drm_amdgpu_memory_info

struct	drm_amdgpu_info_firmware

struct	drm_amdgpu_info_vbios

struct	drm_amdgpu_info_device

struct	drm_amdgpu_info_hw_ip

struct	drm_amdgpu_info_num_handles

struct	drm_amdgpu_info_vce_clock_table_entry

struct	drm_amdgpu_info_vce_clock_table

struct	drm_amdgpu_info_video_codec_info

struct	drm_amdgpu_info_video_caps

struct	drm_amdgpu_info_gpuvm_fault

struct	drm_amdgpu_info_uq_metadata_gfx

struct	drm_amdgpu_info_uq_metadata_compute

struct	drm_amdgpu_info_uq_metadata_sdma

struct	drm_amdgpu_info_uq_metadata

Macros
#define	DRM_AMDGPU_GEM_CREATE 0x00

#define	DRM_AMDGPU_GEM_MMAP 0x01

#define	DRM_AMDGPU_CTX 0x02

#define	DRM_AMDGPU_BO_LIST 0x03

#define	DRM_AMDGPU_CS 0x04

#define	DRM_AMDGPU_INFO 0x05

#define	DRM_AMDGPU_GEM_METADATA 0x06

#define	DRM_AMDGPU_GEM_WAIT_IDLE 0x07

#define	DRM_AMDGPU_GEM_VA 0x08

#define	DRM_AMDGPU_WAIT_CS 0x09

#define	DRM_AMDGPU_GEM_OP 0x10

#define	DRM_AMDGPU_GEM_USERPTR 0x11

#define	DRM_AMDGPU_WAIT_FENCES 0x12

#define	DRM_AMDGPU_VM 0x13

#define	DRM_AMDGPU_FENCE_TO_HANDLE 0x14

#define	DRM_AMDGPU_SCHED 0x15

#define	DRM_AMDGPU_USERQ 0x16

#define	DRM_AMDGPU_USERQ_SIGNAL 0x17

#define	DRM_AMDGPU_USERQ_WAIT 0x18

#define	DRM_AMDGPU_GEM_LIST_HANDLES 0x19

#define	DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)

#define	DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)

#define	DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)

#define	DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)

#define	DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)

#define	DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)

#define	DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)

#define	DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)

#define	DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)

#define	DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)

#define	DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)

#define	DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)

#define	DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)

#define	DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)

#define	DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)

#define	DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)

#define	DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)

#define	DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)

#define	DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)

#define	DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles)

#define	AMDGPU_GEM_DOMAIN_CPU 0x1

#define	AMDGPU_GEM_DOMAIN_GTT 0x2

#define	AMDGPU_GEM_DOMAIN_VRAM 0x4

#define	AMDGPU_GEM_DOMAIN_GDS 0x8

#define	AMDGPU_GEM_DOMAIN_GWS 0x10

#define	AMDGPU_GEM_DOMAIN_OA 0x20

#define	AMDGPU_GEM_DOMAIN_DOORBELL 0x40

#define	AMDGPU_GEM_DOMAIN_MASK

#define	AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)

#define	AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)

#define	AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)

#define	AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)

#define	AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)

#define	AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)

#define	AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)

#define	AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8)

#define	AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)

#define	AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)

#define	AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11)

#define	AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12)

#define	AMDGPU_GEM_CREATE_COHERENT (1 << 13)

#define	AMDGPU_GEM_CREATE_UNCACHED (1 << 14)

#define	AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15)

#define	AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16)

#define	AMDGPU_BO_LIST_OP_CREATE 0

#define	AMDGPU_BO_LIST_OP_DESTROY 1

#define	AMDGPU_BO_LIST_OP_UPDATE 2

#define	AMDGPU_CTX_OP_ALLOC_CTX 1

#define	AMDGPU_CTX_OP_FREE_CTX 2

#define	AMDGPU_CTX_OP_QUERY_STATE 3

#define	AMDGPU_CTX_OP_QUERY_STATE2 4

#define	AMDGPU_CTX_OP_GET_STABLE_PSTATE 5

#define	AMDGPU_CTX_OP_SET_STABLE_PSTATE 6

#define	AMDGPU_CTX_NO_RESET 0

#define	AMDGPU_CTX_GUILTY_RESET 1

#define	AMDGPU_CTX_INNOCENT_RESET 2

#define	AMDGPU_CTX_UNKNOWN_RESET 3

#define	AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)

#define	AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)

#define	AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)

#define	AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)

#define	AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)

#define	AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5)

#define	AMDGPU_CTX_PRIORITY_UNSET -2048

#define	AMDGPU_CTX_PRIORITY_VERY_LOW -1023

#define	AMDGPU_CTX_PRIORITY_LOW -512

#define	AMDGPU_CTX_PRIORITY_NORMAL 0

#define	AMDGPU_CTX_PRIORITY_HIGH 512

#define	AMDGPU_CTX_PRIORITY_VERY_HIGH 1023

#define	AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf

#define	AMDGPU_CTX_STABLE_PSTATE_NONE 0

#define	AMDGPU_CTX_STABLE_PSTATE_STANDARD 1

#define	AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2

#define	AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3

#define	AMDGPU_CTX_STABLE_PSTATE_PEAK 4

#define	AMDGPU_USERQ_OP_CREATE 1

#define	AMDGPU_USERQ_OP_FREE 2

#define	AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK 0x3

#define	AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0

#define	AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0

#define	AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1

#define	AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2

#define	AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */

#define	AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2)

#define	AMDGPU_VM_OP_RESERVE_VMID 1

#define	AMDGPU_VM_OP_UNRESERVE_VMID 2

#define	AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1

#define	AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2

#define	AMDGPU_GEM_USERPTR_READONLY (1 << 0)

#define	AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)

#define	AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)

#define	AMDGPU_GEM_USERPTR_REGISTER (1 << 3)

#define	AMDGPU_TILING_ARRAY_MODE_SHIFT 0

#define	AMDGPU_TILING_ARRAY_MODE_MASK 0xf

#define	AMDGPU_TILING_PIPE_CONFIG_SHIFT 4

#define	AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f

#define	AMDGPU_TILING_TILE_SPLIT_SHIFT 9

#define	AMDGPU_TILING_TILE_SPLIT_MASK 0x7

#define	AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12

#define	AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7

#define	AMDGPU_TILING_BANK_WIDTH_SHIFT 15

#define	AMDGPU_TILING_BANK_WIDTH_MASK 0x3

#define	AMDGPU_TILING_BANK_HEIGHT_SHIFT 17

#define	AMDGPU_TILING_BANK_HEIGHT_MASK 0x3

#define	AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19

#define	AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3

#define	AMDGPU_TILING_NUM_BANKS_SHIFT 21

#define	AMDGPU_TILING_NUM_BANKS_MASK 0x3

#define	AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0

#define	AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f

#define	AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5

#define	AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF

#define	AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29

#define	AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF

#define	AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43

#define	AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1

#define	AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44

#define	AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1

#define	AMDGPU_TILING_SCANOUT_SHIFT 63

#define	AMDGPU_TILING_SCANOUT_MASK 0x1

#define	AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0

#define	AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7

#define	AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3

#define	AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */

#define	AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5

#define	AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */

#define	AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8

#define	AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */

#define	AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT 14

#define	AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK 0x1

#define	AMDGPU_TILING_GFX12_SCANOUT_SHIFT 63

#define	AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1

#define	AMDGPU_TILING_SET(field, value) (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)

#define	AMDGPU_TILING_GET(value, field) (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)

#define	AMDGPU_GEM_METADATA_OP_SET_METADATA 1

#define	AMDGPU_GEM_METADATA_OP_GET_METADATA 2

#define	AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0

#define	AMDGPU_GEM_OP_SET_PLACEMENT 1

#define	AMDGPU_GEM_OP_GET_MAPPING_INFO 2

#define	AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT (1 << 0)

#define	AMDGPU_VA_OP_MAP 1

#define	AMDGPU_VA_OP_UNMAP 2

#define	AMDGPU_VA_OP_CLEAR 3

#define	AMDGPU_VA_OP_REPLACE 4

#define	AMDGPU_VM_DELAY_UPDATE (1 << 0)

#define	AMDGPU_VM_PAGE_READABLE (1 << 1)

#define	AMDGPU_VM_PAGE_WRITEABLE (1 << 2)

#define	AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)

#define	AMDGPU_VM_PAGE_PRT (1 << 4)

#define	AMDGPU_VM_MTYPE_MASK (0xf << 5)

#define	AMDGPU_VM_MTYPE_DEFAULT (0 << 5)

#define	AMDGPU_VM_MTYPE_NC (1 << 5)

#define	AMDGPU_VM_MTYPE_WC (2 << 5)

#define	AMDGPU_VM_MTYPE_CC (3 << 5)

#define	AMDGPU_VM_MTYPE_UC (4 << 5)

#define	AMDGPU_VM_MTYPE_RW (5 << 5)

#define	AMDGPU_VM_PAGE_NOALLOC (1 << 9)

#define	AMDGPU_HW_IP_GFX 0

#define	AMDGPU_HW_IP_COMPUTE 1

#define	AMDGPU_HW_IP_DMA 2

#define	AMDGPU_HW_IP_UVD 3

#define	AMDGPU_HW_IP_VCE 4

#define	AMDGPU_HW_IP_UVD_ENC 5

#define	AMDGPU_HW_IP_VCN_DEC 6

#define	AMDGPU_HW_IP_VCN_ENC 7

#define	AMDGPU_HW_IP_VCN_JPEG 8

#define	AMDGPU_HW_IP_VPE 9

#define	AMDGPU_HW_IP_NUM 10

#define	AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1

#define	AMDGPU_CHUNK_ID_IB 0x01

#define	AMDGPU_CHUNK_ID_FENCE 0x02

#define	AMDGPU_CHUNK_ID_DEPENDENCIES 0x03

#define	AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04

#define	AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05

#define	AMDGPU_CHUNK_ID_BO_HANDLES 0x06

#define	AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07

#define	AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08

#define	AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09

#define	AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a

#define	AMDGPU_IB_FLAG_CE (1<<0)

#define	AMDGPU_IB_FLAG_PREAMBLE (1<<1)

#define	AMDGPU_IB_FLAG_PREEMPT (1<<2)

#define	AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)

#define	AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)

#define	AMDGPU_IB_FLAGS_SECURE (1 << 5)

#define	AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)

#define	AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0

#define	AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1

#define	AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2

#define	AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1

#define	AMDGPU_IDS_FLAGS_FUSION 0x01

#define	AMDGPU_IDS_FLAGS_PREEMPTION 0x02

#define	AMDGPU_IDS_FLAGS_TMZ 0x04

#define	AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x08

#define	AMDGPU_IDS_FLAGS_GANG_SUBMIT 0x10

#define	AMDGPU_IDS_FLAGS_MODE_MASK 0x300

#define	AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8

#define	AMDGPU_IDS_FLAGS_MODE_PF 0x0

#define	AMDGPU_IDS_FLAGS_MODE_VF 0x1

#define	AMDGPU_IDS_FLAGS_MODE_PT 0x2

#define	AMDGPU_INFO_ACCEL_WORKING 0x00

#define	AMDGPU_INFO_CRTC_FROM_ID 0x01

#define	AMDGPU_INFO_HW_IP_INFO 0x02

#define	AMDGPU_INFO_HW_IP_COUNT 0x03

#define	AMDGPU_INFO_TIMESTAMP 0x05

#define	AMDGPU_INFO_FW_VERSION 0x0e

#define	AMDGPU_INFO_FW_VCE 0x1

#define	AMDGPU_INFO_FW_UVD 0x2

#define	AMDGPU_INFO_FW_GMC 0x03

#define	AMDGPU_INFO_FW_GFX_ME 0x04

#define	AMDGPU_INFO_FW_GFX_PFP 0x05

#define	AMDGPU_INFO_FW_GFX_CE 0x06

#define	AMDGPU_INFO_FW_GFX_RLC 0x07

#define	AMDGPU_INFO_FW_GFX_MEC 0x08

#define	AMDGPU_INFO_FW_SMC 0x0a

#define	AMDGPU_INFO_FW_SDMA 0x0b

#define	AMDGPU_INFO_FW_SOS 0x0c

#define	AMDGPU_INFO_FW_ASD 0x0d

#define	AMDGPU_INFO_FW_VCN 0x0e

#define	AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f

#define	AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10

#define	AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11

#define	AMDGPU_INFO_FW_DMCU 0x12

#define	AMDGPU_INFO_FW_TA 0x13

#define	AMDGPU_INFO_FW_DMCUB 0x14

#define	AMDGPU_INFO_FW_TOC 0x15

#define	AMDGPU_INFO_FW_CAP 0x16

#define	AMDGPU_INFO_FW_GFX_RLCP 0x17

#define	AMDGPU_INFO_FW_GFX_RLCV 0x18

#define	AMDGPU_INFO_FW_MES_KIQ 0x19

#define	AMDGPU_INFO_FW_MES 0x1a

#define	AMDGPU_INFO_FW_IMU 0x1b

#define	AMDGPU_INFO_FW_VPE 0x1c

#define	AMDGPU_INFO_NUM_BYTES_MOVED 0x0f

#define	AMDGPU_INFO_VRAM_USAGE 0x10

#define	AMDGPU_INFO_GTT_USAGE 0x11

#define	AMDGPU_INFO_GDS_CONFIG 0x13

#define	AMDGPU_INFO_VRAM_GTT 0x14

#define	AMDGPU_INFO_READ_MMR_REG 0x15

#define	AMDGPU_INFO_DEV_INFO 0x16

#define	AMDGPU_INFO_VIS_VRAM_USAGE 0x17

#define	AMDGPU_INFO_NUM_EVICTIONS 0x18

#define	AMDGPU_INFO_MEMORY 0x19

#define	AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A

#define	AMDGPU_INFO_VBIOS 0x1B

#define	AMDGPU_INFO_VBIOS_SIZE 0x1

#define	AMDGPU_INFO_VBIOS_IMAGE 0x2

#define	AMDGPU_INFO_VBIOS_INFO 0x3

#define	AMDGPU_INFO_NUM_HANDLES 0x1C

#define	AMDGPU_INFO_SENSOR 0x1D

#define	AMDGPU_INFO_SENSOR_GFX_SCLK 0x1

#define	AMDGPU_INFO_SENSOR_GFX_MCLK 0x2

#define	AMDGPU_INFO_SENSOR_GPU_TEMP 0x3

#define	AMDGPU_INFO_SENSOR_GPU_LOAD 0x4

#define	AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5

#define	AMDGPU_INFO_SENSOR_VDDNB 0x6

#define	AMDGPU_INFO_SENSOR_VDDGFX 0x7

#define	AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8

#define	AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9

#define	AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa

#define	AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb

#define	AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc

#define	AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E

#define	AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F

#define	AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20

#define	AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)

#define	AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)

#define	AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)

#define	AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)

#define	AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)

#define	AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)

#define	AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)

#define	AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)

#define	AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)

#define	AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)

#define	AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)

#define	AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)

#define	AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)

#define	AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)

#define	AMDGPU_INFO_VIDEO_CAPS 0x21

#define	AMDGPU_INFO_VIDEO_CAPS_DECODE 0

#define	AMDGPU_INFO_VIDEO_CAPS_ENCODE 1

#define	AMDGPU_INFO_MAX_IBS 0x22

#define	AMDGPU_INFO_GPUVM_FAULT 0x23

#define	AMDGPU_INFO_UQ_FW_AREAS 0x24

#define	AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0

#define	AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff

#define	AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8

#define	AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff

#define	AMDGPU_VRAM_TYPE_UNKNOWN 0

#define	AMDGPU_VRAM_TYPE_GDDR1 1

#define	AMDGPU_VRAM_TYPE_DDR2 2

#define	AMDGPU_VRAM_TYPE_GDDR3 3

#define	AMDGPU_VRAM_TYPE_GDDR4 4

#define	AMDGPU_VRAM_TYPE_GDDR5 5

#define	AMDGPU_VRAM_TYPE_HBM 6

#define	AMDGPU_VRAM_TYPE_DDR3 7

#define	AMDGPU_VRAM_TYPE_DDR4 8

#define	AMDGPU_VRAM_TYPE_GDDR6 9

#define	AMDGPU_VRAM_TYPE_DDR5 10

#define	AMDGPU_VRAM_TYPE_LPDDR4 11

#define	AMDGPU_VRAM_TYPE_LPDDR5 12

#define	AMDGPU_VRAM_TYPE_HBM3E 13

#define	AMDGPU_VRAM_TYPE_HBM4 14

#define	AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6

#define	AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0

#define	AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1

#define	AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2

#define	AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3

#define	AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4

#define	AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5

#define	AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6

#define	AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7

#define	AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8

#define	AMDGPU_VMHUB_TYPE_MASK 0xff

#define	AMDGPU_VMHUB_TYPE_SHIFT 0

#define	AMDGPU_VMHUB_TYPE_GFX 0

#define	AMDGPU_VMHUB_TYPE_MM0 1

#define	AMDGPU_VMHUB_TYPE_MM1 2

#define	AMDGPU_VMHUB_IDX_MASK 0xff00

#define	AMDGPU_VMHUB_IDX_SHIFT 8

#define	AMDGPU_FAMILY_UNKNOWN 0

#define	AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */

#define	AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */

#define	AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */

#define	AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */

#define	AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */

#define	AMDGPU_FAMILY_AI 141 /* Vega10 */

#define	AMDGPU_FAMILY_RV 142 /* Raven */

#define	AMDGPU_FAMILY_NV 143 /* Navi10 */

#define	AMDGPU_FAMILY_VGH 144 /* Van Gogh */

#define	AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */

#define	AMDGPU_FAMILY_YC 146 /* Yellow Carp */

#define	AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */

#define	AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */

#define	AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */

#define	AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */

#define	AMDGPU_FAMILY_GC_11_5_4 154 /* GC 11.5.4 */

#define	AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */

Macro Definition Documentation

◆ AMDGPU_BO_LIST_OP_CREATE

#define AMDGPU_BO_LIST_OP_CREATE 0

Opcode to create new residency list.

◆ AMDGPU_BO_LIST_OP_DESTROY

#define AMDGPU_BO_LIST_OP_DESTROY 1

Opcode to destroy previously created residency list

◆ AMDGPU_BO_LIST_OP_UPDATE

#define AMDGPU_BO_LIST_OP_UPDATE 2

Opcode to update resource information in the list

◆ AMDGPU_CHUNK_ID_BO_HANDLES

#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06

◆ AMDGPU_CHUNK_ID_CP_GFX_SHADOW

#define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a

◆ AMDGPU_CHUNK_ID_DEPENDENCIES

#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03

◆ AMDGPU_CHUNK_ID_FENCE

#define AMDGPU_CHUNK_ID_FENCE 0x02

◆ AMDGPU_CHUNK_ID_IB

#define AMDGPU_CHUNK_ID_IB 0x01

◆ AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES

#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07

◆ AMDGPU_CHUNK_ID_SYNCOBJ_IN

#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04

◆ AMDGPU_CHUNK_ID_SYNCOBJ_OUT

#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05

◆ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL

#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09

◆ AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT

#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08

◆ AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW

#define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1

◆ AMDGPU_CTX_GUILTY_RESET

#define AMDGPU_CTX_GUILTY_RESET 1

◆ AMDGPU_CTX_INNOCENT_RESET

#define AMDGPU_CTX_INNOCENT_RESET 2

◆ AMDGPU_CTX_NO_RESET

#define AMDGPU_CTX_NO_RESET 0

◆ AMDGPU_CTX_OP_ALLOC_CTX

#define AMDGPU_CTX_OP_ALLOC_CTX 1

◆ AMDGPU_CTX_OP_FREE_CTX

#define AMDGPU_CTX_OP_FREE_CTX 2

◆ AMDGPU_CTX_OP_GET_STABLE_PSTATE

#define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5

◆ AMDGPU_CTX_OP_QUERY_STATE

#define AMDGPU_CTX_OP_QUERY_STATE 3

◆ AMDGPU_CTX_OP_QUERY_STATE2

#define AMDGPU_CTX_OP_QUERY_STATE2 4

◆ AMDGPU_CTX_OP_SET_STABLE_PSTATE

#define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6

◆ AMDGPU_CTX_PRIORITY_HIGH

#define AMDGPU_CTX_PRIORITY_HIGH 512

◆ AMDGPU_CTX_PRIORITY_LOW

#define AMDGPU_CTX_PRIORITY_LOW -512

◆ AMDGPU_CTX_PRIORITY_NORMAL

#define AMDGPU_CTX_PRIORITY_NORMAL 0

◆ AMDGPU_CTX_PRIORITY_UNSET

#define AMDGPU_CTX_PRIORITY_UNSET -2048

◆ AMDGPU_CTX_PRIORITY_VERY_HIGH

#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023

◆ AMDGPU_CTX_PRIORITY_VERY_LOW

#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023

◆ AMDGPU_CTX_QUERY2_FLAGS_GUILTY

#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)

◆ AMDGPU_CTX_QUERY2_FLAGS_RAS_CE

#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)

◆ AMDGPU_CTX_QUERY2_FLAGS_RAS_UE

#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)

◆ AMDGPU_CTX_QUERY2_FLAGS_RESET

#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)

◆ AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS

#define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5)

◆ AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST

#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)

◆ AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK

#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf

◆ AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK

#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3

◆ AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK

#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2

◆ AMDGPU_CTX_STABLE_PSTATE_NONE

#define AMDGPU_CTX_STABLE_PSTATE_NONE 0

◆ AMDGPU_CTX_STABLE_PSTATE_PEAK

#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4

◆ AMDGPU_CTX_STABLE_PSTATE_STANDARD

#define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1

◆ AMDGPU_CTX_UNKNOWN_RESET

#define AMDGPU_CTX_UNKNOWN_RESET 3

◆ AMDGPU_FAMILY_AI

#define AMDGPU_FAMILY_AI 141 /* Vega10 */

◆ AMDGPU_FAMILY_CI

#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */

◆ AMDGPU_FAMILY_CZ

#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */

◆ AMDGPU_FAMILY_GC_10_3_6

#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */

◆ AMDGPU_FAMILY_GC_10_3_7

#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */

◆ AMDGPU_FAMILY_GC_11_0_0

#define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */

◆ AMDGPU_FAMILY_GC_11_0_1

#define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */

◆ AMDGPU_FAMILY_GC_11_5_0

#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */

◆ AMDGPU_FAMILY_GC_11_5_4

#define AMDGPU_FAMILY_GC_11_5_4 154 /* GC 11.5.4 */

◆ AMDGPU_FAMILY_GC_12_0_0

#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */

◆ AMDGPU_FAMILY_KV

#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */

◆ AMDGPU_FAMILY_NV

#define AMDGPU_FAMILY_NV 143 /* Navi10 */

◆ AMDGPU_FAMILY_RV

#define AMDGPU_FAMILY_RV 142 /* Raven */

◆ AMDGPU_FAMILY_SI

#define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */

◆ AMDGPU_FAMILY_UNKNOWN

#define AMDGPU_FAMILY_UNKNOWN 0

◆ AMDGPU_FAMILY_VGH

#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */

◆ AMDGPU_FAMILY_VI

#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */

◆ AMDGPU_FAMILY_YC

#define AMDGPU_FAMILY_YC 146 /* Yellow Carp */

◆ AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD

#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2

◆ AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ

#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0

◆ AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD

#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1

◆ AMDGPU_GEM_CREATE_COHERENT

#define AMDGPU_GEM_CREATE_COHERENT (1 << 13)

◆ AMDGPU_GEM_CREATE_CP_MQD_GFX9

#define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8)

◆ AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED

#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)

◆ AMDGPU_GEM_CREATE_CPU_GTT_USWC

#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)

◆ AMDGPU_GEM_CREATE_DISCARDABLE

#define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12)

◆ AMDGPU_GEM_CREATE_ENCRYPTED

#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)

◆ AMDGPU_GEM_CREATE_EXPLICIT_SYNC

#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)

◆ AMDGPU_GEM_CREATE_EXT_COHERENT

#define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15)

◆ AMDGPU_GEM_CREATE_GFX12_DCC

#define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16)

◆ AMDGPU_GEM_CREATE_NO_CPU_ACCESS

#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)

◆ AMDGPU_GEM_CREATE_PREEMPTIBLE

#define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11)

◆ AMDGPU_GEM_CREATE_UNCACHED

#define AMDGPU_GEM_CREATE_UNCACHED (1 << 14)

◆ AMDGPU_GEM_CREATE_VM_ALWAYS_VALID

#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)

◆ AMDGPU_GEM_CREATE_VRAM_CLEARED

#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)

◆ AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS

#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)

◆ AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE

#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)

◆ AMDGPU_GEM_DOMAIN_CPU

#define AMDGPU_GEM_DOMAIN_CPU 0x1

DOC: memory domains

AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. Memory in this pool could be swapped out to disk if there is pressure.

AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the GPU's virtual address space via gart. Gart memory linearizes non-contiguous pages of system memory, allows GPU access system memory in a linearized fashion.

AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory carved out by the BIOS.

AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data across shader threads.

AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the execution of all the waves on a device.

AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines for appending data.

AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for signalling user mode queues.

◆ AMDGPU_GEM_DOMAIN_DOORBELL

#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40

◆ AMDGPU_GEM_DOMAIN_GDS

#define AMDGPU_GEM_DOMAIN_GDS 0x8

◆ AMDGPU_GEM_DOMAIN_GTT

#define AMDGPU_GEM_DOMAIN_GTT 0x2

◆ AMDGPU_GEM_DOMAIN_GWS

#define AMDGPU_GEM_DOMAIN_GWS 0x10

◆ AMDGPU_GEM_DOMAIN_MASK

#define AMDGPU_GEM_DOMAIN_MASK

Value:

                     (AMDGPU_GEM_DOMAIN_CPU | \
                     AMDGPU_GEM_DOMAIN_GTT | \
                     AMDGPU_GEM_DOMAIN_VRAM | \
                     AMDGPU_GEM_DOMAIN_GDS | \
                     AMDGPU_GEM_DOMAIN_GWS | \
                     AMDGPU_GEM_DOMAIN_OA | \
                     AMDGPU_GEM_DOMAIN_DOORBELL)

◆ AMDGPU_GEM_DOMAIN_OA

#define AMDGPU_GEM_DOMAIN_OA 0x20

◆ AMDGPU_GEM_DOMAIN_VRAM

#define AMDGPU_GEM_DOMAIN_VRAM 0x4

◆ AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT

#define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT (1 << 0)

◆ AMDGPU_GEM_METADATA_OP_GET_METADATA

#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2

◆ AMDGPU_GEM_METADATA_OP_SET_METADATA

#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1

◆ AMDGPU_GEM_OP_GET_GEM_CREATE_INFO

#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0

◆ AMDGPU_GEM_OP_GET_MAPPING_INFO

#define AMDGPU_GEM_OP_GET_MAPPING_INFO 2

◆ AMDGPU_GEM_OP_SET_PLACEMENT

#define AMDGPU_GEM_OP_SET_PLACEMENT 1

◆ AMDGPU_GEM_USERPTR_ANONONLY

#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)

◆ AMDGPU_GEM_USERPTR_READONLY

#define AMDGPU_GEM_USERPTR_READONLY (1 << 0)

◆ AMDGPU_GEM_USERPTR_REGISTER

#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)

◆ AMDGPU_GEM_USERPTR_VALIDATE

#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)

◆ AMDGPU_HW_IP_COMPUTE

#define AMDGPU_HW_IP_COMPUTE 1

◆ AMDGPU_HW_IP_DMA

#define AMDGPU_HW_IP_DMA 2

◆ AMDGPU_HW_IP_GFX

#define AMDGPU_HW_IP_GFX 0

◆ AMDGPU_HW_IP_INSTANCE_MAX_COUNT

#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1

◆ AMDGPU_HW_IP_NUM

#define AMDGPU_HW_IP_NUM 10

◆ AMDGPU_HW_IP_UVD

#define AMDGPU_HW_IP_UVD 3

◆ AMDGPU_HW_IP_UVD_ENC

#define AMDGPU_HW_IP_UVD_ENC 5

◆ AMDGPU_HW_IP_VCE

#define AMDGPU_HW_IP_VCE 4

◆ AMDGPU_HW_IP_VCN_DEC

#define AMDGPU_HW_IP_VCN_DEC 6

◆ AMDGPU_HW_IP_VCN_ENC

#define AMDGPU_HW_IP_VCN_ENC 7

◆ AMDGPU_HW_IP_VCN_JPEG

#define AMDGPU_HW_IP_VCN_JPEG 8

◆ AMDGPU_HW_IP_VPE

#define AMDGPU_HW_IP_VPE 9

◆ AMDGPU_IB_FLAG_CE

#define AMDGPU_IB_FLAG_CE (1<<0)

◆ AMDGPU_IB_FLAG_EMIT_MEM_SYNC

#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)

◆ AMDGPU_IB_FLAG_PREAMBLE

#define AMDGPU_IB_FLAG_PREAMBLE (1<<1)

◆ AMDGPU_IB_FLAG_PREEMPT

#define AMDGPU_IB_FLAG_PREEMPT (1<<2)

◆ AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID

#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)

◆ AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE

#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)

◆ AMDGPU_IB_FLAGS_SECURE

#define AMDGPU_IB_FLAGS_SECURE (1 << 5)

◆ AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD

#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x08

◆ AMDGPU_IDS_FLAGS_FUSION

#define AMDGPU_IDS_FLAGS_FUSION 0x01

◆ AMDGPU_IDS_FLAGS_GANG_SUBMIT

#define AMDGPU_IDS_FLAGS_GANG_SUBMIT 0x10

◆ AMDGPU_IDS_FLAGS_MODE_MASK

#define AMDGPU_IDS_FLAGS_MODE_MASK 0x300

◆ AMDGPU_IDS_FLAGS_MODE_PF

#define AMDGPU_IDS_FLAGS_MODE_PF 0x0

◆ AMDGPU_IDS_FLAGS_MODE_PT

#define AMDGPU_IDS_FLAGS_MODE_PT 0x2

◆ AMDGPU_IDS_FLAGS_MODE_SHIFT

#define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8

◆ AMDGPU_IDS_FLAGS_MODE_VF

#define AMDGPU_IDS_FLAGS_MODE_VF 0x1

◆ AMDGPU_IDS_FLAGS_PREEMPTION

#define AMDGPU_IDS_FLAGS_PREEMPTION 0x02

◆ AMDGPU_IDS_FLAGS_TMZ

#define AMDGPU_IDS_FLAGS_TMZ 0x04

◆ AMDGPU_INFO_ACCEL_WORKING

#define AMDGPU_INFO_ACCEL_WORKING 0x00

◆ AMDGPU_INFO_CRTC_FROM_ID

#define AMDGPU_INFO_CRTC_FROM_ID 0x01

◆ AMDGPU_INFO_DEV_INFO

#define AMDGPU_INFO_DEV_INFO 0x16

◆ AMDGPU_INFO_FW_ASD

#define AMDGPU_INFO_FW_ASD 0x0d

◆ AMDGPU_INFO_FW_CAP

#define AMDGPU_INFO_FW_CAP 0x16

◆ AMDGPU_INFO_FW_DMCU

#define AMDGPU_INFO_FW_DMCU 0x12

◆ AMDGPU_INFO_FW_DMCUB

#define AMDGPU_INFO_FW_DMCUB 0x14

◆ AMDGPU_INFO_FW_GFX_CE

#define AMDGPU_INFO_FW_GFX_CE 0x06

◆ AMDGPU_INFO_FW_GFX_ME

#define AMDGPU_INFO_FW_GFX_ME 0x04

◆ AMDGPU_INFO_FW_GFX_MEC

#define AMDGPU_INFO_FW_GFX_MEC 0x08

◆ AMDGPU_INFO_FW_GFX_PFP

#define AMDGPU_INFO_FW_GFX_PFP 0x05

◆ AMDGPU_INFO_FW_GFX_RLC

#define AMDGPU_INFO_FW_GFX_RLC 0x07

◆ AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL

#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f

◆ AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM

#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10

◆ AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM

#define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11

◆ AMDGPU_INFO_FW_GFX_RLCP

#define AMDGPU_INFO_FW_GFX_RLCP 0x17

◆ AMDGPU_INFO_FW_GFX_RLCV

#define AMDGPU_INFO_FW_GFX_RLCV 0x18

◆ AMDGPU_INFO_FW_GMC

#define AMDGPU_INFO_FW_GMC 0x03

◆ AMDGPU_INFO_FW_IMU

#define AMDGPU_INFO_FW_IMU 0x1b

◆ AMDGPU_INFO_FW_MES

#define AMDGPU_INFO_FW_MES 0x1a

◆ AMDGPU_INFO_FW_MES_KIQ

#define AMDGPU_INFO_FW_MES_KIQ 0x19

◆ AMDGPU_INFO_FW_SDMA

#define AMDGPU_INFO_FW_SDMA 0x0b

◆ AMDGPU_INFO_FW_SMC

#define AMDGPU_INFO_FW_SMC 0x0a

◆ AMDGPU_INFO_FW_SOS

#define AMDGPU_INFO_FW_SOS 0x0c

◆ AMDGPU_INFO_FW_TA

#define AMDGPU_INFO_FW_TA 0x13

◆ AMDGPU_INFO_FW_TOC

#define AMDGPU_INFO_FW_TOC 0x15

◆ AMDGPU_INFO_FW_UVD

#define AMDGPU_INFO_FW_UVD 0x2

◆ AMDGPU_INFO_FW_VCE

#define AMDGPU_INFO_FW_VCE 0x1

◆ AMDGPU_INFO_FW_VCN

#define AMDGPU_INFO_FW_VCN 0x0e

◆ AMDGPU_INFO_FW_VERSION

#define AMDGPU_INFO_FW_VERSION 0x0e

◆ AMDGPU_INFO_FW_VPE

#define AMDGPU_INFO_FW_VPE 0x1c

◆ AMDGPU_INFO_GDS_CONFIG

#define AMDGPU_INFO_GDS_CONFIG 0x13

◆ AMDGPU_INFO_GPUVM_FAULT

#define AMDGPU_INFO_GPUVM_FAULT 0x23

◆ AMDGPU_INFO_GTT_USAGE

#define AMDGPU_INFO_GTT_USAGE 0x11

◆ AMDGPU_INFO_HW_IP_COUNT

#define AMDGPU_INFO_HW_IP_COUNT 0x03

◆ AMDGPU_INFO_HW_IP_INFO

#define AMDGPU_INFO_HW_IP_INFO 0x02

◆ AMDGPU_INFO_MAX_IBS

#define AMDGPU_INFO_MAX_IBS 0x22

◆ AMDGPU_INFO_MEMORY

#define AMDGPU_INFO_MEMORY 0x19

◆ AMDGPU_INFO_MMR_SE_INDEX_MASK

#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff

◆ AMDGPU_INFO_MMR_SE_INDEX_SHIFT

#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0

◆ AMDGPU_INFO_MMR_SH_INDEX_MASK

#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff

◆ AMDGPU_INFO_MMR_SH_INDEX_SHIFT

#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8

◆ AMDGPU_INFO_NUM_BYTES_MOVED

#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f

◆ AMDGPU_INFO_NUM_EVICTIONS

#define AMDGPU_INFO_NUM_EVICTIONS 0x18

◆ AMDGPU_INFO_NUM_HANDLES

#define AMDGPU_INFO_NUM_HANDLES 0x1C

◆ AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS

#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E

◆ AMDGPU_INFO_RAS_ENABLED_ATHUB

#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)

◆ AMDGPU_INFO_RAS_ENABLED_DF

#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)

◆ AMDGPU_INFO_RAS_ENABLED_FEATURES

#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20

◆ AMDGPU_INFO_RAS_ENABLED_FUSE

#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)

◆ AMDGPU_INFO_RAS_ENABLED_GFX

#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)

◆ AMDGPU_INFO_RAS_ENABLED_HDP

#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)

◆ AMDGPU_INFO_RAS_ENABLED_MMHUB

#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)

◆ AMDGPU_INFO_RAS_ENABLED_MP0

#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)

◆ AMDGPU_INFO_RAS_ENABLED_MP1

#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)

◆ AMDGPU_INFO_RAS_ENABLED_PCIE

#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)

◆ AMDGPU_INFO_RAS_ENABLED_SDMA

#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)

◆ AMDGPU_INFO_RAS_ENABLED_SEM

#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)

◆ AMDGPU_INFO_RAS_ENABLED_SMN

#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)

◆ AMDGPU_INFO_RAS_ENABLED_UMC

#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)

◆ AMDGPU_INFO_RAS_ENABLED_XGMI

#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)

◆ AMDGPU_INFO_READ_MMR_REG

#define AMDGPU_INFO_READ_MMR_REG 0x15

◆ AMDGPU_INFO_SENSOR

#define AMDGPU_INFO_SENSOR 0x1D

◆ AMDGPU_INFO_SENSOR_GFX_MCLK

#define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2

◆ AMDGPU_INFO_SENSOR_GFX_SCLK

#define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1

◆ AMDGPU_INFO_SENSOR_GPU_AVG_POWER

#define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5

◆ AMDGPU_INFO_SENSOR_GPU_INPUT_POWER

#define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc

◆ AMDGPU_INFO_SENSOR_GPU_LOAD

#define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4

◆ AMDGPU_INFO_SENSOR_GPU_TEMP

#define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3

◆ AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK

#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb

◆ AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK

#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa

◆ AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK

#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9

◆ AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK

#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8

◆ AMDGPU_INFO_SENSOR_VDDGFX

#define AMDGPU_INFO_SENSOR_VDDGFX 0x7

◆ AMDGPU_INFO_SENSOR_VDDNB

#define AMDGPU_INFO_SENSOR_VDDNB 0x6

◆ AMDGPU_INFO_TIMESTAMP

#define AMDGPU_INFO_TIMESTAMP 0x05

◆ AMDGPU_INFO_UQ_FW_AREAS

#define AMDGPU_INFO_UQ_FW_AREAS 0x24

◆ AMDGPU_INFO_VBIOS

#define AMDGPU_INFO_VBIOS 0x1B

◆ AMDGPU_INFO_VBIOS_IMAGE

#define AMDGPU_INFO_VBIOS_IMAGE 0x2

◆ AMDGPU_INFO_VBIOS_INFO

#define AMDGPU_INFO_VBIOS_INFO 0x3

◆ AMDGPU_INFO_VBIOS_SIZE

#define AMDGPU_INFO_VBIOS_SIZE 0x1

◆ AMDGPU_INFO_VCE_CLOCK_TABLE

#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A

◆ AMDGPU_INFO_VIDEO_CAPS

#define AMDGPU_INFO_VIDEO_CAPS 0x21

◆ AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1

#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7

◆ AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT

#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8

◆ AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC

#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4

◆ AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG

#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5

◆ AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2

#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0

◆ AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4

#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1

◆ AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC

#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3

◆ AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1

#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2

◆ AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9

#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6

◆ AMDGPU_INFO_VIDEO_CAPS_DECODE

#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0

◆ AMDGPU_INFO_VIDEO_CAPS_ENCODE

#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1

◆ AMDGPU_INFO_VIS_VRAM_USAGE

#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17

◆ AMDGPU_INFO_VRAM_GTT

#define AMDGPU_INFO_VRAM_GTT 0x14

◆ AMDGPU_INFO_VRAM_LOST_COUNTER

#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F

◆ AMDGPU_INFO_VRAM_USAGE

#define AMDGPU_INFO_VRAM_USAGE 0x10

◆ AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE

#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2

◆ AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE

#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1

◆ AMDGPU_TILING_ARRAY_MODE_MASK

#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf

◆ AMDGPU_TILING_ARRAY_MODE_SHIFT

#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0

◆ AMDGPU_TILING_BANK_HEIGHT_MASK

#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3

◆ AMDGPU_TILING_BANK_HEIGHT_SHIFT

#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17

◆ AMDGPU_TILING_BANK_WIDTH_MASK

#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3

◆ AMDGPU_TILING_BANK_WIDTH_SHIFT

#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15

◆ AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK

#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1

◆ AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT

#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44

◆ AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK

#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1

◆ AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT

#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43

◆ AMDGPU_TILING_DCC_OFFSET_256B_MASK

#define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF

◆ AMDGPU_TILING_DCC_OFFSET_256B_SHIFT

#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5

◆ AMDGPU_TILING_DCC_PITCH_MAX_MASK

#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF

◆ AMDGPU_TILING_DCC_PITCH_MAX_SHIFT

#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29

◆ AMDGPU_TILING_GET

#define AMDGPU_TILING_GET	(	value,
		field
	)	(((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)

◆ AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK

#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */

◆ AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT

#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8

◆ AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK

#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */

◆ AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT

#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3

◆ AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK

#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */

◆ AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT

#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5

◆ AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK

#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK 0x1

◆ AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT

#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT 14

◆ AMDGPU_TILING_GFX12_SCANOUT_MASK

#define AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1

◆ AMDGPU_TILING_GFX12_SCANOUT_SHIFT

#define AMDGPU_TILING_GFX12_SCANOUT_SHIFT 63

◆ AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK

#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7

◆ AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT

#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0

◆ AMDGPU_TILING_MACRO_TILE_ASPECT_MASK

#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3

◆ AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT

#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19

◆ AMDGPU_TILING_MICRO_TILE_MODE_MASK

#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7

◆ AMDGPU_TILING_MICRO_TILE_MODE_SHIFT

#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12

◆ AMDGPU_TILING_NUM_BANKS_MASK

#define AMDGPU_TILING_NUM_BANKS_MASK 0x3

◆ AMDGPU_TILING_NUM_BANKS_SHIFT

#define AMDGPU_TILING_NUM_BANKS_SHIFT 21

◆ AMDGPU_TILING_PIPE_CONFIG_MASK

#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f

◆ AMDGPU_TILING_PIPE_CONFIG_SHIFT

#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4

◆ AMDGPU_TILING_SCANOUT_MASK

#define AMDGPU_TILING_SCANOUT_MASK 0x1

◆ AMDGPU_TILING_SCANOUT_SHIFT

#define AMDGPU_TILING_SCANOUT_SHIFT 63

◆ AMDGPU_TILING_SET

#define AMDGPU_TILING_SET	(	field,
		value
	)	(((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)

◆ AMDGPU_TILING_SWIZZLE_MODE_MASK

#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f

◆ AMDGPU_TILING_SWIZZLE_MODE_SHIFT

#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0

◆ AMDGPU_TILING_TILE_SPLIT_MASK

#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7

◆ AMDGPU_TILING_TILE_SPLIT_SHIFT

#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9

◆ AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH

#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */

◆ AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW

#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1

◆ AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK

#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK 0x3

◆ AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH

#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2

◆ AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW

#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0

◆ AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT

#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0

◆ AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE

#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2)

◆ AMDGPU_USERQ_OP_CREATE

#define AMDGPU_USERQ_OP_CREATE 1

◆ AMDGPU_USERQ_OP_FREE

#define AMDGPU_USERQ_OP_FREE 2

◆ AMDGPU_VA_OP_CLEAR

#define AMDGPU_VA_OP_CLEAR 3

◆ AMDGPU_VA_OP_MAP

#define AMDGPU_VA_OP_MAP 1

◆ AMDGPU_VA_OP_REPLACE

#define AMDGPU_VA_OP_REPLACE 4

◆ AMDGPU_VA_OP_UNMAP

#define AMDGPU_VA_OP_UNMAP 2

◆ AMDGPU_VCE_CLOCK_TABLE_ENTRIES

#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6

◆ AMDGPU_VM_DELAY_UPDATE

#define AMDGPU_VM_DELAY_UPDATE (1 << 0)

◆ AMDGPU_VM_MTYPE_CC

#define AMDGPU_VM_MTYPE_CC (3 << 5)

◆ AMDGPU_VM_MTYPE_DEFAULT

#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)

◆ AMDGPU_VM_MTYPE_MASK

#define AMDGPU_VM_MTYPE_MASK (0xf << 5)

◆ AMDGPU_VM_MTYPE_NC

#define AMDGPU_VM_MTYPE_NC (1 << 5)

◆ AMDGPU_VM_MTYPE_RW

#define AMDGPU_VM_MTYPE_RW (5 << 5)

◆ AMDGPU_VM_MTYPE_UC

#define AMDGPU_VM_MTYPE_UC (4 << 5)

◆ AMDGPU_VM_MTYPE_WC

#define AMDGPU_VM_MTYPE_WC (2 << 5)

◆ AMDGPU_VM_OP_RESERVE_VMID

#define AMDGPU_VM_OP_RESERVE_VMID 1

◆ AMDGPU_VM_OP_UNRESERVE_VMID

#define AMDGPU_VM_OP_UNRESERVE_VMID 2

◆ AMDGPU_VM_PAGE_EXECUTABLE

#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)

◆ AMDGPU_VM_PAGE_NOALLOC

#define AMDGPU_VM_PAGE_NOALLOC (1 << 9)

◆ AMDGPU_VM_PAGE_PRT

#define AMDGPU_VM_PAGE_PRT (1 << 4)

◆ AMDGPU_VM_PAGE_READABLE

#define AMDGPU_VM_PAGE_READABLE (1 << 1)

◆ AMDGPU_VM_PAGE_WRITEABLE

#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)

◆ AMDGPU_VMHUB_IDX_MASK

#define AMDGPU_VMHUB_IDX_MASK 0xff00

◆ AMDGPU_VMHUB_IDX_SHIFT

#define AMDGPU_VMHUB_IDX_SHIFT 8

◆ AMDGPU_VMHUB_TYPE_GFX

#define AMDGPU_VMHUB_TYPE_GFX 0

◆ AMDGPU_VMHUB_TYPE_MASK

#define AMDGPU_VMHUB_TYPE_MASK 0xff

◆ AMDGPU_VMHUB_TYPE_MM0

#define AMDGPU_VMHUB_TYPE_MM0 1

◆ AMDGPU_VMHUB_TYPE_MM1

#define AMDGPU_VMHUB_TYPE_MM1 2

◆ AMDGPU_VMHUB_TYPE_SHIFT

#define AMDGPU_VMHUB_TYPE_SHIFT 0

◆ AMDGPU_VRAM_TYPE_DDR2

#define AMDGPU_VRAM_TYPE_DDR2 2

◆ AMDGPU_VRAM_TYPE_DDR3

#define AMDGPU_VRAM_TYPE_DDR3 7

◆ AMDGPU_VRAM_TYPE_DDR4

#define AMDGPU_VRAM_TYPE_DDR4 8

◆ AMDGPU_VRAM_TYPE_DDR5

#define AMDGPU_VRAM_TYPE_DDR5 10

◆ AMDGPU_VRAM_TYPE_GDDR1

#define AMDGPU_VRAM_TYPE_GDDR1 1

◆ AMDGPU_VRAM_TYPE_GDDR3

#define AMDGPU_VRAM_TYPE_GDDR3 3

◆ AMDGPU_VRAM_TYPE_GDDR4

#define AMDGPU_VRAM_TYPE_GDDR4 4

◆ AMDGPU_VRAM_TYPE_GDDR5

#define AMDGPU_VRAM_TYPE_GDDR5 5

◆ AMDGPU_VRAM_TYPE_GDDR6

#define AMDGPU_VRAM_TYPE_GDDR6 9

◆ AMDGPU_VRAM_TYPE_HBM

#define AMDGPU_VRAM_TYPE_HBM 6

◆ AMDGPU_VRAM_TYPE_HBM3E

#define AMDGPU_VRAM_TYPE_HBM3E 13

◆ AMDGPU_VRAM_TYPE_HBM4

#define AMDGPU_VRAM_TYPE_HBM4 14

◆ AMDGPU_VRAM_TYPE_LPDDR4

#define AMDGPU_VRAM_TYPE_LPDDR4 11

◆ AMDGPU_VRAM_TYPE_LPDDR5

#define AMDGPU_VRAM_TYPE_LPDDR5 12

◆ AMDGPU_VRAM_TYPE_UNKNOWN

#define AMDGPU_VRAM_TYPE_UNKNOWN 0

◆ DRM_AMDGPU_BO_LIST

#define DRM_AMDGPU_BO_LIST 0x03

◆ DRM_AMDGPU_CS

#define DRM_AMDGPU_CS 0x04

◆ DRM_AMDGPU_CTX

#define DRM_AMDGPU_CTX 0x02

◆ DRM_AMDGPU_FENCE_TO_HANDLE

#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14

◆ DRM_AMDGPU_GEM_CREATE

#define DRM_AMDGPU_GEM_CREATE 0x00

◆ DRM_AMDGPU_GEM_LIST_HANDLES

#define DRM_AMDGPU_GEM_LIST_HANDLES 0x19

◆ DRM_AMDGPU_GEM_METADATA

#define DRM_AMDGPU_GEM_METADATA 0x06

◆ DRM_AMDGPU_GEM_MMAP

#define DRM_AMDGPU_GEM_MMAP 0x01

◆ DRM_AMDGPU_GEM_OP

#define DRM_AMDGPU_GEM_OP 0x10

◆ DRM_AMDGPU_GEM_USERPTR

#define DRM_AMDGPU_GEM_USERPTR 0x11

◆ DRM_AMDGPU_GEM_VA

#define DRM_AMDGPU_GEM_VA 0x08

◆ DRM_AMDGPU_GEM_WAIT_IDLE

#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07

◆ DRM_AMDGPU_INFO

#define DRM_AMDGPU_INFO 0x05

◆ DRM_AMDGPU_SCHED

#define DRM_AMDGPU_SCHED 0x15

◆ DRM_AMDGPU_USERQ

#define DRM_AMDGPU_USERQ 0x16

◆ DRM_AMDGPU_USERQ_SIGNAL

#define DRM_AMDGPU_USERQ_SIGNAL 0x17

◆ DRM_AMDGPU_USERQ_WAIT

#define DRM_AMDGPU_USERQ_WAIT 0x18

◆ DRM_AMDGPU_VM

#define DRM_AMDGPU_VM 0x13

◆ DRM_AMDGPU_WAIT_CS

#define DRM_AMDGPU_WAIT_CS 0x09

◆ DRM_AMDGPU_WAIT_FENCES

#define DRM_AMDGPU_WAIT_FENCES 0x12

◆ DRM_IOCTL_AMDGPU_BO_LIST

#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)

◆ DRM_IOCTL_AMDGPU_CS

#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)

◆ DRM_IOCTL_AMDGPU_CTX

#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)

◆ DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE

#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)

◆ DRM_IOCTL_AMDGPU_GEM_CREATE

#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)

◆ DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES

#define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles)

◆ DRM_IOCTL_AMDGPU_GEM_METADATA

#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)

◆ DRM_IOCTL_AMDGPU_GEM_MMAP

#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)

◆ DRM_IOCTL_AMDGPU_GEM_OP

#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)

◆ DRM_IOCTL_AMDGPU_GEM_USERPTR

#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)

◆ DRM_IOCTL_AMDGPU_GEM_VA

#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)

◆ DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE

#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)

◆ DRM_IOCTL_AMDGPU_INFO

#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)

◆ DRM_IOCTL_AMDGPU_SCHED

#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)

◆ DRM_IOCTL_AMDGPU_USERQ

#define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)

◆ DRM_IOCTL_AMDGPU_USERQ_SIGNAL

#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)

◆ DRM_IOCTL_AMDGPU_USERQ_WAIT

#define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)

◆ DRM_IOCTL_AMDGPU_VM

#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)

◆ DRM_IOCTL_AMDGPU_WAIT_CS

#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)

◆ DRM_IOCTL_AMDGPU_WAIT_FENCES

#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)

Classes

Macros